Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of the LDMOS region and the CMOS region; and forming a second well in the CMOS region, wherein a depth of the first well is larger than a depth of the second well and the second well is a retrograde well formed by a high energy ion implantation method.

Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.

Abstract: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

Abstract: In a high-voltage NMOS transistor with low threshold voltage, it is proposed to realize the body doping that defines the channel region in the form of a deep p-well, and to arrange an additional shallow p-doping as a channel stopper on the transistor head, wherein this additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.

Abstract: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device.

Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

Abstract: Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.

Abstract: A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.

Abstract: Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo ion are performed after source/drain anneals. In the inventive method, source/drain spacers on MOS gate sidewalls are removed prior to halo ion implant processes. Spacers to offset metal silicide are formed after halo implants and may be of low-k dielectric material to reduce gate to drain capacitance. A compressive stress layer may be deposited on MOS gates after source/drain spacers are removed for greater stress transfer efficiency to the MOS gates. An integrated circuit embodying the inventive method is also disclosed.

Abstract: A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.

Abstract: A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area, a second area adjacent to the first area, and a third area adjacent to the second area in each of the layers. The semiconductor layer, the insulating layer, and an upper portion of the bulk layer in the first area are removed to form the removal portion. A part of the bulk layer in the second area is removed to form the cavity adjacent to the removal portion. The first semiconductor element is formed in the bulk layer in the removal portion as an ESD protection element. The second semiconductor element is formed partially in the semiconductor layer in the second area.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.

Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Abstract: A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is not more than 1 micrometer, and a gate length that is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the sourced/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.

Abstract: An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.

Abstract: The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.

Abstract: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.

Abstract: A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.

Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.

Abstract: A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.

Abstract: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).

Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.

Abstract: A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation interlayer in a P+ pickup region when a sense amplifier of a semiconductor device is formed. Yield ratio of semiconductor devices is improved.

Abstract: A DMOS device and a method for fabricating the same are provided. A drift region and a well region are formed simultaneously to provide a DMOS device with the drift and well regions having the same depth. This DMOS device includes a high voltage transistor area and a low voltage transistor area, a drift diffused region formed in the high voltage transistor area, and a well region formed in the low voltage transistor area. A drift diffused region and a well region in the low voltage area are formed simultaneously to reduce the number of ion implantation processes, thereby simplifying the manufacturing process.

Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: An oscillator capable of reducing a noise component when partly formed by using the CMOS process or the MOS process. A high-frequency amplifier circuit, a mixing circuit, a local oscillator 13, intermediate-frequency filters, an intermediate-frequency amplifier circuit, a limit circuit, an FM detection circuit, and a stereo demodulation circuit which constitute an FM receiver are formed as a one-chip component. The local oscillator 13 is formed on a semiconductor substrate by using the CMOS process or the MOS process and the transistors constituting the circuit are p-channel type FETs 21, 22. Moreover, the local oscillator 13 has a resonance circuit whose one end is connected to a DC bias circuit composed of a resistor 27 and the center voltage of the oscillation is set to a value higher than 0 V.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

Abstract: A semiconductor device having a simple structure with selectively formed full-silicide (FUSI) and partial silicide gate electrodes and a manufacturing method thereof are provided. According to one aspect, there is provided a semiconductor device includes a first field effect transistor (MOSFET), and a second MOSFET, the first MOSFET including a first gate electrode provided on a gate insulator on a semiconductor substrate and formed of a first metal silicide layer, a first insulator provided to be adjacent to the first gate electrode, and a first sidewall including the first insulator, the second MOSFET including a second gate electrode provided on a gate insulator on the semiconductor substrate and formed of a conductor film including a polysilicon layer and a second metal silicide layer, a second insulator provided to be adjacent to the second gate electrode, and a second sidewall including the second insulator.

Abstract: A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first conduction type second well region formed in the first well region; a second conduction type third well region formed in the second well region; a drain region formed in the second well region; a source region formed in the third well region; a gate electrode formed through a gate insulating film over the third well region between the drain region and the source region; and an insulating layer formed between the gate electrode and the drain region. Parasitic capacitances between the semiconductor substrate and the source region and those between the substrate and the drain region are respectively in series.

Abstract: An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a driver configured to provide a drive signal to the switch and embodied in a transistor. The transistor includes a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor also includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

Abstract: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.

Abstract: A lateral CMOS-compatible RF-DMOS transistor (RFLDMOST) with low ‘on’ resistance, characterised in that disposed in the region of the drift space (20) which is between the highly doped drain region (5) and the control gate (9) and above the low doped drain region LDDR (22, 26) of the transistor is a doping zone (24) which is shallow in comparison with the penetration depth of the source/drain region (3, 5), of inverted conductivity type to the LDDR (22, 26) (hereinafter referred to as the inversion zone) which has a surface area-related nett doping which is lower than the nett doping of the LDDR (22, 26) and does not exceed a nett doping of 8E12 At/cm2.

Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

Abstract: A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.

Abstract: An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress are provided to underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

Abstract: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.

Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.