Plural Sections Connected In Parallel (e.g., Power Mosfet) Patents (Class 257/341)
  • Patent number: 8525257
    Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: September 3, 2013
    Assignee: Micrel, Inc.
    Inventors: Martin Alter, Paul Moore
  • Patent number: 8518777
    Abstract: A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: August 27, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Praveen Muraleedharan Shenoy
  • Patent number: 8519477
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The multiple trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprises at least one trenched channel stop gate around outside of the trenched floating gates and connected to at least one sawing trenched gate extended into scribe line for prevention of leakage path formation between drain and source regions.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 27, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8513735
    Abstract: A structure of a power semiconductor device, in which a P-well region having a large area and a gate electrode are opposed to each other through a field oxide film having a larger thickness than that of a gate insulating film such that the P-well region having a large area and the gate electrode are not opposed to each other through the gate insulating film, or the gate electrode is not provided above the gate insulating film that includes the P-well region having a large area therebelow.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: August 20, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shuhei Nakata, Shoyu Watanabe, Kenichi Otsuka, Naruhisa Miura
  • Patent number: 8513736
    Abstract: A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8513730
    Abstract: A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: August 20, 2013
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Helmut Strack, Armin Willmeroth, Hans-Joachim Schulze
  • Patent number: 8513090
    Abstract: An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8513734
    Abstract: A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 20, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Jiang-Kai Zuo
  • Patent number: 8507981
    Abstract: A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 13, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Lu-An Chen, Tai-Hsiang Lai, Tien-Hao Tang
  • Patent number: 8507986
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 13, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Peter Micah Sandvik, Zachary Matthew Stum, Peter Almren Losee, James Jay McMahon
  • Patent number: 8502313
    Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: August 6, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred C. Session
  • Patent number: 8502312
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: August 6, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 8502315
    Abstract: A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Rudolf Berger, Franz Hirler, Ralf Siemieniec, Hans-Joachim Schulze
  • Patent number: 8502281
    Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Holger Kapels
  • Patent number: 8502306
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a first semiconductor element provided on the semiconductor substrate. The first semiconductor element includes: a first semiconductor; a second semiconductor layer; a third semiconductor layer; a first insulating layer; a first base region; a first source region; a first gate electrode; a first drift layer; a first drain region; a first source; and a first drain electrode. A concentration of an impurity element of the first conductivity type included in the first drift layer is lower than a concentration of an impurity element of the first conductivity type included in the first semiconductor layer. The concentration of the impurity element of the first conductivity type included in the first drift layer is higher than a concentration of an impurity element of the first conductivity type included in the second semiconductor layer.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki Yamaura
  • Patent number: 8502314
    Abstract: This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: August 6, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Jayson S. Preece
  • Patent number: 8497552
    Abstract: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 30, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8492837
    Abstract: Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: July 23, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs, John L. Benjamin
  • Publication number: 20130181289
    Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8482029
    Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization. The semiconductor body also includes a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A voltage tap including a semiconductor region within the semiconductor body is electrically coupled to a first gate electrode of the first field-effect structure by an intermediate inverter structure.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 9, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Joachim Weyers
  • Patent number: 8476705
    Abstract: A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: July 2, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsuehi Huang, Yin-Fu Huang, Shih-Chin Lien
  • Publication number: 20130161742
    Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super junction area may include pillars of different doping types that are alternately disposed. One of the pillars of the super junction area may have a doping concentration that gradually decreases and then increases from bottom to top in a vertical direction of the semiconductor device.
    Type: Application
    Filed: March 29, 2012
    Publication date: June 27, 2013
    Inventors: Moon-soo CHO, Kwang-yeon JUN, Hyuk WOO, Chang-sik LIM
  • Patent number: 8471344
    Abstract: Disclosed is an integrated circuit device having stacked fin-type field effect transistors (FINFETs) with integrated voltage equalization and a method. A multi-layer fin includes a semiconductor layer, an insulator layer above the semiconductor layer and a high resistance conductor layer above the insulator layer. For each FINFET, a gate is positioned on the sidewalls and top surface of the fin and source/drain regions are within the semiconductor layer on both sides of the gate. Thus, the portion of the semiconductor layer between any two gates contains a source/drain region of one FINFET abutting a source/drain region of another. Conductive straps are positioned on opposing ends of the fin and also between adjacent gates in order to electrically connect the semiconductor layer to the conductor layer. Contacts electrically connect the conductive straps at the opposing ends of the fin to positive and negative supply voltages, respectively.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8471333
    Abstract: A trench is formed so as to reach a p?-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8466513
    Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: June 18, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Zia Hossain, Kirk K. Huang, Balaji Padmanabhan, Francine Y. Robb, Prasad Venkatraman
  • Patent number: 8466510
    Abstract: A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: June 18, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Hamza Yilmaz
  • Patent number: 8466516
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, an element isolation insulator, a source layer of a second conductivity type, a drain layer of the second conductivity type, a contact layer of the first conductivity type and a gate electrode. The element isolation insulator is formed on the semiconductor substrate. The source layer is formed on the semiconductor substrate and is in contact with a side surface of the element isolation insulator. The drain layer is formed on the semiconductor substrate, is in contact with the side surface, and is spaced from the source layer. The contact layer is formed between the source layer and the drain layer. The gate electrode is provided on the element isolation insulator along the side surface.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: June 18, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutoshi Nakamura, Norio Yasuhara
  • Patent number: 8461648
    Abstract: A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to the drift region in the semiconductor body. An accumulation dielectric is arranged between the drift region and the drift control region.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: June 11, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Anton Mauder, Armin Willmeroth, Hans-Joachim Schulze, Stefan Sedlmaier, Markus Zundel, Franz Hirler, Arunjai Mittal
  • Publication number: 20130140633
    Abstract: In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N? type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: VISHAY-SILICONIX
    Inventor: Deva N. Pattanayak
  • Patent number: 8455946
    Abstract: A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: June 4, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8455320
    Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: June 4, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 8455318
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 8455956
    Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera
  • Patent number: 8450797
    Abstract: To realize forming a trench MOSFET in which a depth of a P-body is changed on the same surface as a CMOS by employing steps with good controllability and without greatly increasing the number of manufacturing steps, provided is a trench MOSFET including an extended body region (10), which is a part of a P-body region (4) and is provided in a vicinity of a deep trench (5) with a distance, the extended body region (10) being diffused deeper than the P-body region (4).
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 28, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Naoto Saitoh
  • Patent number: 8445939
    Abstract: A method of forming a semiconductor device comprises forming a control electrode over a portion of a semiconductor layer, forming recesses extending into the semiconductor layer on opposing sides of the control electrode, and forming doped regions in the semiconductor layer through the recesses. The doped regions form current electrode regions of the semiconductor device and each doped region extends into the semiconductor layer from at least a base of a recess. The method further comprises forming, after forming the doped regions, strained semiconductor regions in the recesses, wherein a junction between each doped region and the semiconductor layer is formed below an interface between a strained semiconductor region and the semiconductor layer.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: May 21, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: John M. Grant
  • Patent number: 8436423
    Abstract: A backside-illuminated image sensor is disclosed having improved quantum efficiency (QE) in the near infrared wavelengths (NIR: 750-1100 nm) with minimal optical interference fringes produced by multiple reflected rays within the photosensitive Si region of the sensor, which may be a charge-coupled device, a complementary metal oxide sensor or an electron-multiplication sensor. The invention comprises a fringe suppression layer applied to the backside surface of the photosensitive Si region of a detector (Si substrate) whereby the fringe suppression layer functions in concert with the Si substrate to reduce the occurrence of interference fringes in the NIR while maintaining a high QE over a broad range of wavelengths (300-1100 nm). The combination of a fringe suppression layer applied to a Si substrate provides a new class of back illuminated solid state detectors for imaging.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: May 7, 2013
    Assignee: Roper Scientific, Inc.
    Inventors: William Edward Asher, Michael Alan Case, Jason McClure
  • Patent number: 8436367
    Abstract: A SiC Power Semiconductor device of the Field Effect Type (MOSFET, IGBT or the like) with “muted” channel conduction, negative temperature coefficient of channel mobility, in situ “ballasted” source resistors and optimized thermal management of the cells for increased Safe Operating Area is described. Controlling the location of the Zero Temperature Crossover Point (ZTCP) in relationship to the drain current is achieved by the partition between the “active” and “inactive” channels and by adjusting the mobility of the carriers in the channel for the temperature range of interest. The “Thermal management” is realized by surrounding the “active” cells/fingers with “inactive” ones and the “negative” feedback of the drain/collector current due to local increase of the gate bias is achieved by implementing in-situ “ballast” resistors inside of each source contact.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 7, 2013
    Assignee: Microsemi Corporation
    Inventors: Dumitru Sdrulla, Bruce Odekirk, Marc Vandenberg
  • Patent number: 8431973
    Abstract: A high frequency semiconductor device includes: a field effect transistor including gate terminal electrodes, source terminal electrodes, and a drain terminal electrode; an input circuit pattern and an output circuit pattern which are disposed adjoining of the field effect transistor; a plurality of input bonding wires configured to connect the plurality of the gate terminal electrodes and the input circuit pattern; and a plurality of output bonding wires configured to connect the drain terminal electrode and the output circuit pattern, which makes matching an input/output signal phase by adjusting an inductance distribution of a plurality of input/output bonding wires, and improves gain and output power, and suppresses an oscillation by unbalanced operation of each FET cell.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: April 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8431991
    Abstract: A semiconductor device includes a peripheral voltage withstanding structure, which includes an n? SiC layer, an n SiC layer and a p SiC layer are provided successively on an n+ SiC layer. A trench is formed in the peripheral voltage withstanding structure portion so that the trench passes through the p SiC layer 15 and the n SiC layer 14 and reaches the n? SiC layer. This trench is wider than a trench having a trench gate structure in the active region portion. A p+ SiC region is provided along a bottom of the trench so as to be located under the trench. A sidewall and the bottom of the trench are covered with an oxide film and an insulating film having a total thickness not smaller than 1.1 ?m. The oxide film and insulating film absorb a large part of a voltage applied between a source and a drain.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: April 30, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 8431998
    Abstract: A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: April 30, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Takuji Miyata
  • Patent number: 8431993
    Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: April 30, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao
  • Patent number: 8431992
    Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: April 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Tokano, Tetsuo Matsuda, Wataru Saito
  • Patent number: 8431974
    Abstract: According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: April 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuma Suzuki, Hiroshi Kono, Takashi Shinohe
  • Patent number: 8426910
    Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8426960
    Abstract: A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 23, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Ming Sun, Tao Feng, François Hébert, Yueh-Se Ho
  • Patent number: 8421154
    Abstract: A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: April 16, 2013
    Assignee: DENSO CORPORATION
    Inventor: Takeshi Miyajima
  • Patent number: 8421150
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 16, 2013
    Assignee: Richtek Technology Corporation R.O.C.
    Inventors: Tsung-Yi Huang, Huan-Ping Chu
  • Patent number: 8421145
    Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: April 16, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kenji Hatori
  • Patent number: 8421148
    Abstract: A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: April 16, 2013
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Andrei Konstantinov, Jan-Olov Svederg
  • Patent number: RE44300
    Abstract: A power device is formed by a thyristor and by a MOSFET transistor, series-connected between a first and a second current-conduction terminal. The power device moreover has a control terminal connected to an insulated-gate electrode of the MOSFET transistor and receiving a control voltage for turning on/off the device, and a third current-conduction terminal connected to the thyristor for fast extraction of charges during turning-off. Thereby, upon turning off, there are no current tails, and turning off is very fast. The power device does not have parasitic components and consequently has a very high reverse-bias safe-operating area.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: June 18, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventor: Cesare Ronsisvalle