Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate.

Abstract: A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.

Abstract: A process for producing a metal oxide semiconductor (MOS) transistor is provided. At least two trenches are formed at a surface of a first substrate. Oxide is deposited onto the at least two trenches. The at least two trenches each have a surface spaced apart from the surface of the first substrate. A second substrate is placed onto the surface of the first substrate. A layer is delaminated from the first substrate. The layer includes the at least two oxide-filled trenches and a portion of the first substrate. The layer is then bonded to a second substrate. First and second active regions are then formed, in the portion of the first substrate, overlaying the surfaces of the at least two trenches.

Abstract: A stacked semiconductor structure is designed for component arrangement of an IC (integrated circuit) device having a large number of various types of junction devices, such as diodes, well resistors, N.sup.+ resistors, and BJTs (bipolar junction transistors) and MOS (metal-oxide semiconductor) transistors. The stacked semiconductor structure is constructed on an SOI (silicon-on-insulator) structure which includes a semiconductor substrate; a buried insulator layer formed over the substrate; and a silicon film formed over the buried insulator layer. Based on this SOI structure, the various types of junction devices are arranged in the substrate beneath the buried insulator layer; while the MOS transistors are arranged in the silicon film above the buried insulator layer, with the silicon film further being further formed with a plurality of trenches for isolating the MOS transistors from each other.

Abstract: A high-quality thin-film transistor array. The gate insulating film below the pixel electrode is etched off in its entirely or along a slit extending along a drain bus line in order to simultaneously remove the residual a-Si produced due to defective patterning. The insulating film is interposed between a drain bus line and a pixel electrode to form a boundary separating layer therebetween. The reject ratio is suppressed by reducing the occurrence of point defects of semi-bright spots, ascribable to capacitative coupling to the pixel electrodes as a result of interconnection of the residual a-Si produced by defective patterning to the drain bus line.

Abstract: A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide.

Abstract: Prevents deterioration of the element characteristics of the gate voltage tolerance and the like which is caused by the metallic contaminants that are sealed in the element forming region at the time of applying a trench separator in a SOI substrate. Polysilicon 12 is formed on the side walls of the trench 5, and the metallic contaminants within the element forming region are collected in this polysilicon 12.

Abstract: A semiconductor device and a method for fabricating the same, wherein a thick side wall oxide film or polysilicon film is formed on the edge portion of the second silicon substrate. At the side wall of the oxide film or polysilicon film, the thickness of an active semiconductor substrate at its edge portion increases, thereby obtaining an increased threshold voltage at the edge portion. That is, the formation of the side wall oxide film is carried out to prevent a gate oxide film of the semiconductor device from being directly formed on each side wall of the active silicon substrate. As a result, it is possible to prevent a degradation in electrical characteristic due to a degradation in threshold voltage caused by a reduced thickness of the active semiconductor substrate at its edge portion.

Abstract: An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10.sup.10 Ohms-um divided by the width of the pass-gate.

Abstract: A liquid crystal display (LCD) includes silicide-preventing regions between an amorphous silicon layer and source and drain regions. The silicide-preventing regions, which may be thin oxide regions, act as silicide barriers without degrading the contact resistance characteristics. The doped amorphous silicon layer and the amorphous layer may then be uniformly etched by reducing and preferably preventing the formation of silicide when forming the source and drain electrodes.

Abstract: A substrate-triggering ESD protection circuit is provided for use on a deep-submicron integrated circuit for ESD protection of the integrated circuit. The ESD protection circuit is incorporated between an input end and the internal circuit of the integrated circuit formed on a substrate. The ESD protection circuit utilizes a featured substrate-triggering operation to trigger the ESD-protection transistors formed in N-wells of the substrate into conducting state so as to bypass the ESD current to the ground. The ESD protection circuit allows a simplified semiconductor structure to fabricate, while nonetheless providing an increased level of ESD protection capability for the deep-submicron integrated circuit.

Abstract: In a method for producing a semiconductor substrate completed through a bonding process for joining a semiconductor wafer to a support substrate by performing heat treatment thereto in a state in which the semiconductor wafer is closely joined to the support substrate, the method according to the present invention includes the following steps, i.e., a depositing process for depositing a poly-crystal semiconductor which covers all areas of a surface to be bonded on the surface of the semiconductor wafer; a heat treatment process for performing the heat treatment to the semiconductor wafer provided after the depositing process, during a predetermined time under a temperature equal to or higher than the heat treatment temperature at the bonding process; and a polishing process for flattening the surface of the poly-crystal semiconductor provided after the heat treatment process. After the above processes were performed in order, the bonding process is performed after the polishing process.

Abstract: A semiconductor device comprises a composite substrate comprising a semiconductor substrate and a semiconductor layer on said semiconductor substrate with a dielectric layer interposed therebetween; a plurality of element regions formed in the semiconductor layer and each having formed a field effect transistor including a source region and a drain region of a first conduction type; and an impurity-diffused region of a second conduction type which is formed directly under an element isolating film isolating respective elements. The impurity-diffused region having the opposite conduction type and formed under the element separating film restrain formation of parasitic transistors and prevent a decrease in threshold value.

Abstract: A semiconductor device array having silicon device islands isolated from the substrate by an insulator. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and programming such arrays.

Abstract: A semiconductor device which can prevent formation of a parasitic transistor and degradation in its threshold voltage is obtained. In the semiconductor device, a sidewall insulating film the width of which is increased toward its lower portion is formed on a side wall of a semiconductor layer, and a gate electrode layer is formed such that it extends on the semiconductor layer and the sidewall insulating film.

Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

Abstract: The number of mask steps used to fabricate a TFT in an AMLCD is reduced. In particular, source and drain metallizations, as well as doped and undoped semiconductor layers are patterned at the same time, and the source and drain metallizations and the doped semiconductor layer are etched in a single etching step using an insulating passivation layer as a mask to form source and drain electrodes. Manufacturing costs can be reduced and the manufacturing yield can be improved.

Abstract: A thin film transistor and its fabrication method are disclosed wherein the thin film transistor includes a semiconductor substrate, an active layer formed on an upper surface of the semiconductor substrate, a membrane layer formed on a portion of the active layer and defining an offset region in the active layer, a gate insulation layer formed on portions of the membrane layer and the active layer, a gate electrode formed on a portion of the gate insulation layer, and a source region and a drain region formed in the active layer.

Abstract: A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from the surface of the semiconductor substrate. The element isolation oxide film which is an element isolation insulating film for defining an element forming region on the semiconductor substrate has a projection portion above the surface of the semiconductor substrate. The projection portion has the width wider than that of the trench. The projection portion and a contact portion made in contact with the semiconductor substrate within the trench are made of thermal oxide films, and a portion other than the projection portion and the contact portion is made of a CVD dioxide film.

Abstract: A semiconductor-on-insulator (SOI) device is fabricated by forming spaced apart trenches in a first face of a semiconductor substrate. An insulating layer is formed on the first face of the semiconductor substrate, including on the trenches. A second substrate is bonded to the insulating layer, opposite the semiconductor substrate. The semiconductor substrate is thinned at a second face thereof which is opposite the first face, until a semiconductor film remains on the insulating layer, having alternating thin and thick film semiconductor regions on the insulating layer. Source/drains are formed in the thin film semiconductor regions. Insulated gates are formed on the thick film semiconductor regions, such that a respective insulated gate is located between adjacent source/drains. SOI devices which can suppress floating body effects and yet provide dense integration may thereby be formed.

Abstract: An insulating gate field effect semiconductor device having a gate insulating film of high resistance to moisture adsorption, wherein trap densities in the gate insulator film and at the interface between a channel semiconductor film and the gate insulator film are lowered, and causing no degradation of device characteristics and no lowering of reliability are caused. A SiO.sub.2 film including fluorine atoms is used as the gate insulator film to compensate defects in the gate insulator film and at the interface between the channel semiconductor film and the gate insulator film.

Abstract: A high frequency MOSFET device includes a Silicon-On-Insulator substrate. The MOSFET device has a source electrode connected to the substrate by a conductive region penetrating the insulator layer for dissipating heat from the drive section of an MOSFET to the substrate. The conductive region may be in a grid pattern or lattice configuration, surrounding the drive section of each MOSFET on the SOI substrate, opposite the source electrode of the MOSFET.

Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

Abstract: A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the body region, with the source and drain regions being characterized by a second conductivity type. A transition region is disposed near the body region above the SOI layer, and the conductivity type of the transition region is established to be the first conductivity type for suppressing floating body effects in the body region and the second conductivity type for isolating the body region. An ohmic connector contacts the transition region and is connected to a drain power supply when the source and drain are doped with N-type dopants. On the other hand, the power supply is a source power supply when the source and drain are doped with P-type dopants.

Abstract: An active silicon-on-insulator region isolation structure is provided that includes an active bulk substrate region (24), an active silicon-on-insulator region (22), and a transition region positioned between the active bulk substrate region (24) and the active silicon-on-insulator region (22). The active silicon-on-insulator region (22) includes a silicon-on-insulator film (16) positioned above a buried insulator layer (18). The transition region includes a sloping portion of the buried insulator layer (18) and a tapered edge portion of the silicon-on-insulator film (16).

Abstract: A high voltage integrated circuit is provided which includes a first conductivity type semiconductor substrate, a first conductivity type isolation region that extends continuously from the first conductivity type semiconductor substrate, a substrate electrode formed on a surface of the first conductivity type isolation region, a second conductivity type island-like region that is formed on the first conductivity type semiconductor substrate, such that the entire periphery of the island-like region is surrounded by the first conductity type isolation region, and a plurality of high voltage MOSFETs that are connected to a common power source and operate independently of each other.

Abstract: An SOI-type MISFET with a body contact has a Si active layer arranged on an insulating layer. A pair of source and drain regions interposing a main channel region are arranged in the active layer. An additional channel region and a body-contact region are also arranged in the active layer. A gate electrode is arranged to have first and second portions facing the main and additional channel regions, respectively, through a gate insulating film. A main MIS capacitor and a parasitic MIS capacitor are formed under the first and second portions of the gate electrode, respectively. The additional channel region is doped with an impurity under a condition different from that of the main channel region such that electrical charges necessary for charging and discharging the parasitic MIS capacitor are decreased, in an operation voltage range of the device.

Abstract: An MOS device including a p-channel semiconductor device and an n-channel semiconductor device, which are formed on top of an SOI substrate consisting of a supporting substrate, an insulation film, and a semiconductor layer patterned in a plurality of islands. In the peripheral region of respective islands of the semiconductor layer, boundary films, thicker than respective gate oxide films, are formed, and a boundary film formed on the semiconductor layer for the n-channel semiconductor device is thinner than another boundary film formed on the semiconductor layer for the p-channel semiconductor device. A field doped layer 11 may be preferably provided in the peripheral region of the semiconductor layer of the n-channel semiconductor device 41. In the MOS device fabricated as above, leakage current that occurs in a parasitic MOS region in an environment under exposure to radiation is reduced, ensuring stable operation.

Abstract: Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the wafer, is formed on an overall surface of the substrate.

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a source region (44) and a drain region (45) that contact the corners (13) of the pedestal structure (16). Electrical connection to the source region (44) and the drain region (45) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).

Abstract: A semiconductor device (120) is formed in a silicon-on-insulator (SOI) substrate (135). The semiconductor device (120) has a channel region (126) that is controlled by a gate structure (129). The channel region (126) has a doping profile that is essentially uniform where the channel region (126) is under the gate structure (129). This eliminates the parasitic channel region that is common with conventional field effect transistors (FETs) that are formed in SOI substrates. Consequently, the semiconductor device (120) of the present invention does not suffer from the "kink" problem that is common to conventional FET devices.

Abstract: A thin-film transistor of a type constructed of the semiconductor region on top of an insulating substrate and the gate electrode on the gate insulating layer on top of the channel of the semiconductor region. The thin-film transistor contains an impurity region of opposite semiconductor type of a source region and a drain region, at least where the side wall of the semiconductor region borders the gate electrode via the insulating layer. The impurity region is doped with a higher impurity concentration than the other semiconductor regions. The above arrangement dramatically lowers current leak in the thin-film transistor, and offers a substantially improved manufacturing yield of thin-film transistor.

Abstract: A semiconductor device including a conductive substrate, an insulator layer, a silicon layer doped with impurities and forming a first transistor and a second transistor, an isolation volume between said first transistor and said second transistor, and a conductive stud extending from the doped silicon layer to the substrate.

Abstract: A MOS-based active pixel sensor cell utilizes the parasitic bipolar action of the cell to produce a horizontal current in lieu of the vertical image current associated with conventional bipolar-based active pixel sensor cells. Image data is collected during an integration period by applying a negative voltage to the gate of the MOS transistor which is sufficient to reverse-bias both the source/body and drain/body junctions. Following this, the image data is read out by raising the gate voltage such that the source/body junction remains reverse-biased, and the drain/body junction becomes forward-biased. Under these bias conditions, an amplified horizontal image current flows from the source, through the body, and out of the drain.

Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

Abstract: A semiconductor device includes a flat, square n-type diffusion layer, a p-type channel stopper region, and an electrode. The n-type diffusion layer is formed to be isolated in a check element region of a p-type semiconductor substrate or a p-type well covered with a field oxide film and having circuit element regions and the check element region sandwiched therebetween. The p-type channel stopper region is formed to contact at least one side of the n-type diffusion layer. The electrode is extracted from the n-type diffusion layer through a contact hole. The n-type diffusion layer, the p-type channel stopper region, and the electrode constitute the check element for checking a state of the p-type channel stopper region by measuring a junction breakdown voltage of the n-type diffusion layer.

Abstract: A thin film semiconductor device includes a thin film semiconductor, a gate insulating film, and a gate electrode. The thin film semiconductor includes a source region of a first conductivity type connected to a source electrode/wiring, a drain region of the first conductivity connected to a drain electrode/wiring, a base region being intrinsic or having a conductivity type opposite to the first conductivity and disposed between the source region and the drain region, and a floating island region having the first conductivity type and divided from the source region and the drain region by the base region. The gate electrode is provided upper or under the base region through the gate insulating film. According to such a structure, an ON/OFF ratio of the thin film semiconductor device can be increased.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices.

Abstract: A semiconductor device having the SOI structure is provided, which enables to reduce the size of components compared with the conventional semiconductor devices. The device contains a first insulator film formed on a semiconductor substrate, and semiconductor islands formed on the first insulator film. Each of the islands has an electronic component. The device further contains semiconductor sidewalls formed to surround the respective islands. The sidewalls are contacted with outer sides of the corresponding islands. Electrodes are formed outside the islands to be contacted with the corresponding sidewalls. A second insulator film is formed on the exposed first insulator film from the islands to laterally isolate the respective islands and the corresponding sidewalls from each other. The electronic components are electrically connected to the respective electrodes through the corresponding sidewalls.

Abstract: The semiconductor device of this invention includes a substrate having an insulating surface and a thin film transistor formed on the substrate, wherein the thin film transistor has a semiconductor island including a channel region and source/drain regions, a gate insulating film formed on the semiconductor island and a gate electrode covering the channel region of the semiconductor island interposing the gate insulating film therebetween, and wherein a distance between an edge of the channel region of the semiconductor island and the gate electrode is larger then a distance between a central portion of the channel region of the semiconductor island and the gate electrode.

Abstract: An integrated thin film transistor on insulator circuit made up of a number of thin film transistors formed with small feature size and densely packed so as to allow interconnection as a complex circuit. An insulating substrate, preferably flexible, serves as the support layer for the integrated circuit. Control gate metallization is carried on the insulating substrate, a dielectric layer is deposited over the control gate, and an amorphous silicon layer with doped source and drain regions deposited on the dielectric layer. Trenches are formed to remove the amorphous silicon material between transistors to allow highly dense circuit packing. An upper interconnect level which forms connections to the source and drain and gate regions of the thin film transistors, also interconnects the transistors to form more complex circuit structures. Due to the dense packing of the transistors allowed by the trench isolation, the interconnecting foils can be relatively short, increasing the speed of the circuit.

Abstract: A semiconductor dynamic random access memory device has a memory cell array fabricated on a silicon-on-insulator region and peripheral and interface circuits fabricated on a bulk region; even if the circuit components of the peripheral circuit are increased together with the memory cells, the bulk region effectively radiates the heat generated by the peripheral and interface circuits, thereby preventing the memory cells from a temperature rise.

Abstract: A semiconductor device which includes a mesa type silicon film with a source/drain region and a channel region formed therein, a gate oxide film formed on the mesa type silicon film, and a gate electrode provided on the mesa type silicon film through the gate oxide film, wherein an oxide film having a thickness greater than that of the gate film is formed at the top edge section of the mesa type silicon which is present under the gate electrode, as well as a method for manufacturing it.

Abstract: The invention provides an n-channel MOS field effect transistor with an improved anti-radioactivity. Such transistor includes a p-type silicon substrate. An isolation oxide film is selectively formed on a surface of the p-type silicon substrate. Source and drain diffusion layers of n+-type are formed on first opposite sides of a channel region in the p-type silicon substrate. A gate made of polycrystalline silicon is formed over the channel region through a gate oxide film. Leak guard diffusion layers of p-type are formed on second opposite sides of the channel region in the p-type silicon substrate. The p-type leak guard diffusion layer has a junction surface to the isolation oxide film. The junction surface of the p-type leak guard diffusion layer and the isolation oxide film exists up to a level which is deeper than a depth of the n+-type source and drain diffusion layers.

Abstract: A combination of a doping process and the use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

Abstract: The present invention relates to a method of manufacturing a semiconductor device for forming an insulated gate field effect transistor in a completely isolated SOI layer, and has for its object to prevent depletion or inversion surely by introducing impurities of sufficiently high concentration into an SOI layer adjacent to an isolating film filled up between element regions of the SOI layer and a backing insulating layer and to aim at flattening of the SOI substrate surface, and further, includes the steps of implanting impurity ions into a semiconductor layer from an oblique direction so as to reach the semiconductor layer under an oxidation-preventive mask using the oxidation-preventive mask as a mask for ion implantation, heating the semiconductor layer in an oxidizing atmosphere with the oxidation-preventive mask so as to form a local oxide film to isolate the semiconductor layer, and also forming a impurity region with impurities implanted into the semiconductor layer in a region adjacent to the local

Abstract: A semiconductor device of SOI structure formed by the mesa isolation method, which can sufficiently reduce the wiring capacitance even if the width of the isolation trench is large. An SOI layer which constitutes an element region is formed by forming a buried oxide film in a silicon substrate, forming an isolation trench in the buried oxide film and burying an isolating material in the isolation trench. By the formation of the SOI layer with the isolating material, a dummy SOI layer is formed in a field part other than the element region. Then, by the formation of a MOSFET gate wiring on the dummy SOI layer, the wiring capacitance is reduced. Furthermore, the dummy SOI layer is completely depleted when the MOSFET threshold value is applied to the gate wiring.

Abstract: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating film.