Abstract: A semiconductor device, such as a MOS integrated circuit, provides an internal circuit whose primary stage is configured by an inverter circuit consisting of p-channel and n-channel MOS transistors. The sources of the MOS transistors are connected with a first pair of power-supply terminals respectively, while the gates of the MOS transistors are connected together to form a common gate terminal to which a voltage input applied to an input is terminal. The MOS integrated circuit provides first and second input protection circuits which are connected together between the input terminal and common gate terminal. The first input protection circuit is connected with a second pair of power-supply terminals which is provided independently of the first pair of power-supply terminals. When an abnormal voltage input is applied to the input terminal, the first input protection circuit is activated to perform a voltage clamping by releasing an electric current.

Abstract: A semiconductor device which can prevent formation of a parasitic transistor and degradation in its threshold voltage is obtained. In the semiconductor device, a sidewall insulating film the width of which is increased toward its lower portion is formed on a side wall of a semiconductor layer, and a gate electrode layer is formed such that it extends on the semiconductor layer and the sidewall insulating film.

Abstract: Generation of parasitic transistor in active layer edge is prevented, in an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the Latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Abstract: A semiconductor integrated circuit device has a test component associated with a dummy test pattern for evaluating corresponding circuit components of the integrated circuit, and the test component and the dummy test pattern is surrounded by a peripheral dummy pattern so that a micro loading effect on the test component is equivalent to the corresponding circuit components.

Abstract: Amorphous silicon in impurity regions (source and drain regions or N-type or p-type regions) of TFT and TFD are crystallized and activated to lower electric resistance, by depositing film having a catalyst element such as nickel (Ni), iron (Fe), cobalt (Co) or platinum (Pt) on or beneath an amorphous silicon film, or introducing such a catalyst element into the amorphous silicon film by ion implantation and subsequently crystallizing the same by applying heat annealing at an appropriate temperature.

Abstract: Disclosed is a semiconductor device in which dummy regions which are lower than an isolated element region are formed around the isolated element region. Another dummy region which has a height nearly equal to those of element regions may be formed at a non-element-region-existing region, accompanying with lower dummy regions. The method for making the semiconductor device has the steps of suitably forming the element regions and dummy regions on a insulating layer on a substrate, depositing a insulator on the entire surface of the insulating layer and polishing the insulator to obtain a plane surface.

Abstract: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating film.

Abstract: A semiconductor device comprises a transparent insulating substrate, a first insulating layer, a semiconductor layer, a second insulating layer, and an island-like semiconductor layer in order from the side of the substrate. When the laser light is irradiated from the upper side of the semiconductor device the laser light irradiated to the portions having no island-like semiconductor layer thereon is absorbed by the semiconductor layer after being transmitted through the second insulating layer and the heat generates in the semiconductor layer. Heat diffusion occurs thereafter. At the same time, the energy of laser light by laser radiation from the upper side of the semiconductor device is absorbed in the island-like semiconductor layer. The energy is accumulated as the heat in the island-like semiconductor layer and the second insulating layer to suppress the heat diffusion into the substrate.

Abstract: A semiconductor member with a monocrystalline semiconductor layer for forming a functional element. The main plane of the monocrystalline semiconductor layer has a center line average surface roughness Ra of not more than 0.4 nm when the main plane is washed with an aqueous ammonia-hydrogen peroxide solution in a ratio of NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O of 1:1:5 by volume at a washing temperature of 85.degree. C. for a washing time of 10 minutes.

Abstract: A p-well region is formed in a main surface of a semiconductor substrate. A contact electrode is electrically connected to a predetermined n-type impurity region formed in a surface of the p-well region. A diffusion preventing layer is formed between the contact electrode and a drain region of a TFT. An interconnection layer is formed on the semiconductor substrate with an interlayer insulating film therebetween. A diffusion preventing layer is also formed between the interconnection layer and a source region of the TFT. Diffusion preventing layers are further formed between a channel region of the TFT and the source/drain regions of the TFT.

Abstract: A semiconductor device includes a semiconductor layer which has a first surface, and a second surface which is comparatively lower than the first surface. The semiconductor device also has a first material layer formed over the second surface, which includes a first inorganic material which has a hardness exceeding that of the semiconductor layer. The semiconductor device also includes a second material layer which has a hardness less than that of the first material layer, and which is formed in a gap between a sidewall of the first material layer and a sidewall between the first and second surfaces. The first surface of the semiconductor layer is formed by lapping until the first surface of the semiconductor layer is impeded by the first material layer so that the first surface of the semiconductor layer is substantially flush with a top surface of the first material layer.

Abstract: On a semiconductor substrate (1), there are provided field oxide films (2,3,4), a gate oxide film (5), thin oxide films (6, 6) with film thickness almost equal to that of the gate oxide film (5), and a gate electrode (7). An oxide film (8) of the same thickness as the gate oxide film (5) is also provided so as to separate the field oxide films (3) and (4), to overlap a portion of the gate electrode (7). A high-concentration impurity layer (11, 12) is formed under each of the thin oxide films (6, 8). Source-drain areas (9, 10) are provided with end portions separated from the high-concentration impurity layer (12) and the field oxide films (3, 4).

Abstract: A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

Abstract: In the channel layer of a thin film transistor (TFT), a channel and its drain meet at a transition within a transition region. The channel extends in a first, or horizontal, dimension away from the drain and extends in a second, or vertical, dimension from a side away from the gate to a side toward the gate. The charge carrier densities in the transition region vary in the second dimension in a way that reduces leakage current, because the position of the maximum electric field is moved away from the gate and its magnitude is reduced. Variation of densities in the second dimension can be produced by high angle implantation of a dopant and a counterdopant, providing a transition region between the drain and the channel underneath the gate.

Abstract: An image sensor comprises photo sensing elements, having charge storage capability, for transducing received light into electrical quantities. First switching elements have charge storage capability for transferring the charge stored in the photo sensing elements. Second switching elements have charge storage capability for resetting the photo sensing elements by removing the charge still left in the photo sensing elements after the charge transfer. The image sensor further comprises a first gate pulse generator for generating a first pulse signal to be applied to the first switching elements, and a second gate pulse generator for generating a second pulse signal to be applied to the second switching elements, the amplitude of the second pulse signal being different from that of the first pulse signal. The potential applied to the source electrodes of the second switching elements is different from ground potential.

Abstract: A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and a semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.

Abstract: Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

Abstract: A thin film transistor comprising a multi-layer structure including an amorphous silicon layer and a metal layer both forming source and drain regions. The source and drain regions have opposite exposed edges with a slant shape. An active semiconductor layer is disposed at a channel region defined between the source region and the drain region so that it is overlapped with the upper surface portions of the source and drain regions adjacent to their edges faced to each other. In a CMOS type thin film transistor, its n type TFT has a gate overlapped with the source and drain regions and its p type TFT has a gate offsetted from the source and drain region.

Abstract: A TFT array has a plurality of gate lines and a plurality of drain lines formed on a transparent insulating substrate. The gate lines intersect with the drain lines. TFTs are formed at the intersections of the gate lines and the drain lines. An opaque film is formed above the gate lines, the drain lines, and the TFTs, allowing no passage of light passing through the gaps between the transparent electrode, on the one hand, and the gate and drain lines, on the other hand. Therefore, when the TFT array is incorporated into a liquid-crystal display, the display will display high-contrast images.

Abstract: Two preferred embodiments for an alternative body contact are disclosed for fully-depleted silicon-on-insulator transistors. In one preferred embodiment, body contact is made by extending the mesa ends of the body ties down to, and merging them with, mesa regions of an nFET source and using self-aligned silicide (commonly known as salicide) to make a connection to an underlying nFET well. In this first embodiment, the mesas of the body ties merge with the mesa of the source and salicide is used to short out these regions. In another preferred embodiment, body contact is made by extending the mesa ends of the body ties down to the nFET source; however, the mesas are not merged. In this second embodiment, metal routing, which is commonly used to electrically connect circuit elements, is extended to connect to the mesa regions of the body ties. In both embodiments, the body ties are active until the onset of full depletion; however, at the onset of full depletion, the body ties are electrically severed.

Abstract: A thin film transistor having an inverted stagger type structure is formed on a substrate. A gate film having a gate electrode portion is formed on the substrate. A gate insulating film is formed on the gate electrode portion of the gate film such that the gate insulating film is located entirely inside a perimeter defied by the outer edges of the gate electrode portion. A polycrystalline semiconductor film, which is an active layer of the transistor, is formed on the gate insulating film such that it is entirely inside a perimeter defined by the outer edges of the gate insulating layer. The polycrystalline semiconductor film, gate insulating film and gate film are selectively photoetched after being formed on the substrate. Source and drain electrode films are formed so that the electrode films electrically connect with the polycrystalline semiconductor film.

Abstract: A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second memory cell array block (50b). The other bit line (25) of a bit line pair is kept in unloaded state in the first memory cell array block (50a) and is connected to a predetermined memory cell in a first memory cell array block (50b). In these structures, the load state is kept same in both bit lines of the bit line pair. In the memory cell array, four memory cells are disposed in a cross-relationship, and are connected to the bit line (24) through a contact portion (17) used in common by the four memory cells. The word lines (20a and 20b) are formed to obliquely cross the bit lines and to extend perpendicularly to each other. Capacitors (3) in the memory cells have portions extended over the word lines.

Abstract: A field-effect semiconductor device of this invention includes a first insulating film formed on a semiconductor substrate, a source region of a second conductivity type and a drain region of the second conductivity type, which are arranged on the insulating film and are formed on both the sides of a semiconductor active layer of a first conductivity type, a second insulating film for covering the top and side surfaces of the semiconductor active layer, the source region, and the drain region, a gate electrode arranged on the second insulating film corresponding to the semiconductor active layer, a non-oxidizable third insulating film arranged on the second insulating film for covering the side surfaces of the semiconductor active layer and the source and drain regions, and the other regions, a fourth insulating film arranged on the non-oxidizable third insulating film, a fifth insulating film for covering a portion of the third insulating film located on the side surfaces of the source and drain regions, the

Abstract: An integrated circuit has a silicon mesa disposed on a substrate and a field insulator structure in proximity to the mesa and having an opening over a top mesa surface. The opening, which exposes sidewalls in the structure, is positioned with respect to the mesa and has dimensions such that the structure is disposed to overlap a region of the mesa along an outer mesa periphery. A layer of polysilicon extends along a top surface of the structure and into the opening and adjacent to the mesa top surface. An insulator is disposed between the poly layer and the mesa top surface, the insulator having a layer of thermal gate oxide disposed adjacent to the poly layer and having a layer of pyrogenic oxide disposed between the thermal gate oxide layer and the mesa top surface.

Abstract: A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer. In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region.