Abstract: A circuit protects against electrostatic discharge and includes a transistor connected to the circuit to be protected. A semiconductor body of a first conductivity type serves as the collector. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter. The first doped region includes a generally H-shaped doped region and a generally ring-shaped doped region forming an opening in which the second doped region serving as the emitter is received. The H-shaped doped region has a deeper junction surface than the junction surface of the ring-shaped doped region, and a dopant concentration that is less than the dopant concentration of the ring-shaped doped region. The H-shaped doped region achieves a low collector-to-base breakdown voltage and the ring-shaped doped region achieves a low snap-back voltage.

Abstract: The present invention provides an electrostatic breakdown protecting device which has a high electrostatic breakdown resistance, a high latch up resistance and an excellent protective ability and which has no dead space in the vicinity of protective elements. The present invention includes an I/O terminal directly connected to a protective diode comprising a p-type diffusion layer 103a and an n-type diffusion layer 102b, and an NPN protective bipolar transistor comprising n-type diffusion layers 102b, 102c and a p-type well 113 and connected to an NMOSFET for protection comprising n-type diffusion layers 102c, 102d and a gate electrode 105 via an input resistor 114. These protective elements are formed on the p-type well 113 separated from a substrate for an internal circuit by an n-type buried diffusion layer 111 and an n-type well 112. The internal circuit to be protected is connected to a drain 102d of the NMOSFET for protection.

Abstract: An electro static discharge (ESD)-protecting circuit includes a semiconductor substrate of a first conductivity type, a well of a second conductivity type formed within the semiconductor substrate, a first impurity diffusion region of the first conductivity type formed in the well, second and third impurity diffusion regions of the second conductivity type spaced apart from the first impurity diffusion region in the well, an input port connected to the first impurity diffusion region, and a ground port connected to the third impurity diffusion region.

Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

Abstract: A special rail is provided along each edge of an integrated circuit chip with bias circuits connected to the ends of each special rail. The bias circuits charge the special rail to the V.sub.DD voltage level during normal operation, and clamp the special rail to the V.sub.SS rail upon the occurrence of an overvoltage event. Input bonding pads are provided along each edge of the chip and are connected through diodes to the special rail so that 5 volt signals applied to the input bonding pads do not cause damage to the device when operated from a 3.3 volt supply. A signal line of extended length is provided between each input bonding pad and its receiver circuit and includes folded portions for adding to the length of the signal line to form a high frequency inductor to protect the receiver circuit at the onset of an overvoltage event before clamping becomes effective.

Abstract: A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Abstract: An electrostatic discharge (ESD) protecting transistor and a method for fabricating the same, capable of consuming a high voltage or overcurrent applied to a semiconductor circuit device and thereby protecting the circuit device from the high voltage or overcurrent. The ESD protecting transistor is of an asymmetric charge coupled MOS transistor structure having a highly doped buried layer capable of dispersing a current flux, thereby removing an instant ESD impact and reducing generation of heat caused by a concentration of high current flux. Accordingly, an effect of improving the resistance characteristic to the ESD impact is provided.

Abstract: A multi-terminal surge protection device able to absorb surges of either polarity between lines and between a line and ground, in which the difference in operating time between the device elements connected to lines is reduced. A plurality of unipolar surge protection device elements are used which only operate to absorb surges of a specific polarity, and do not exhibit a reverse withstand characteristic upon application of a reverse-polarity voltage. One element is connected to a first line and another element to a second line, while a different element is connected to ground. A semiconductor substrate and second electrode are used that are common to all elements. To prevent lateral interference between elements, at least the element connected to ground is isolated from the line elements.

Abstract: The present invention relates to a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter, a sensor of the voltage between the terminals, and a mechanism for inhibiting the conduction of the current limiter when the voltage sensed exceeds a given threshold.

Abstract: An apparatus and method are disclosed for enhancing the operation of ESD protective circuits in a VLSI chip, having first and second CMOS devices therein which prevent damage due to ESD events, the first device being connected between a Vss contact and an I/O Pad contact and the second device being connected between a Vcc contact and the I/O Pad contact, and including diffusions in the chip that form a first diode which turns ON when negative ESD stresses develops between one of the first and second contacts and the I/O Pad contact, and which form a NPN transistor and a second diode that turn ON when positive ESD stresses develop between one of the first and second contacts and the I/O Pad contact, and additionally having the Vss and Vcc sources capacitively coupled.

Abstract: In an input protection circuit, a bipolar protection device is constituted of a semiconductor substrate of a first conductivity type, a first diffused layer of a second conductivity type formed in the substrate and connected to an input signal pad, a second diffused layer of the second conductivity type formed in the substrate to extend in parallel to the first diffused layer but separately from the first diffused layer by a first space, and a third diffused layer of a high impurity concentration and of the first conductivity type formed in the first space in the substrate to extend in parallel to the first and second diffused layers, in junction with the second diffused layer but separately from the first diffused layer. When a backward biasing voltage is applied, the thickness of a depletion layer formed is made large, so that generation of hot carriers is minimized.

Abstract: A structure and method for fabricating an ESD device for FET transistors by forming a silicon germanium region 40 under a channel region 44 of a field effect transistor (FET). The silicon germanium region 40 comprises the base of a parasitic bipolar 200 transistor that increases the turn on speed. The method comprises:a) forming a gate dielectric layer 20 over a substrate 10;b) forming a gate 30 over the gate 30; the substrate having a channel region under the gate; the channel region extending from the surface of the substrate to a channel depth below the substrate surface;c) forming a silicon germanium region 40 under the channel region 44 using a tilt angle ion implant of Germanium ions;d) forming source and drain doped regions 50 70 adjacent to the channel region and the silicon germanium region whereby the silicon germanium region comprises a base of a parasitic bipolar transistor 40.

Abstract: Disclosed are a semiconductor integrated circuit device capable of including both a bipolar transistor and a MOS transistor while maintaining high performances of then both and a method of fabricating the device. On a p-type silicon substrate a plurality of n.sup.+ -type regions are formed below the buried collector region of a bipolar transistor and the n-type well region of a MOS transistor. A plurality of p-type regions are formed below the isolation region of the bipolar transistor and the p-type well region of the MOS transistor. An epitaxial layer is formed on the substrate including these n.sup.+ -type and p-type regions. This epitaxial layer forms element region layers having a bipolar transistor region and a MOS transistor region. The thickness of the layer of the bipolar transistor region is smaller than that of the layer of the MOS transistor region.

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.0E17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 um. The thickness of the third (p+) region should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.

Abstract: A semiconductor integrated circuit device having an SOI structure is capable of preventing occurrence of leak current flowing from a diffusion layer even when a semiconductor element having a pn-junction is included in the semiconductor substrate. The semiconductor integrated circuit device having the SOI structure is formed with a semiconductor layer, or SOI layer, on a p-type semiconductor substrate through a buried insulating film and further with semiconductor circuit elements serving as functional elements at the SOI layer thus formed. As a protection transistor to protect the semiconductor circuit elements, a MOSFET may be formed in which n-type diffusion layers are formed in the semiconductor substrate. The n-type diffusion layers of the MOSFET are to be surrounded by p-type diffusion layers more highly doped than the semiconductor substrate.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

Abstract: An ESD protection device is provided which reduces the layout area required, utilizing multiple-node configurations and multiple node electrical couplings.

Abstract: An ESD protection network (20) provides energy discharge paths for an ESD event at an external circuit port (42). The paths include one portion (28) into an integrated circuit substrate (72) and other portions (29, 30) from the substrate to external power supply ports (43, 44). In particular, these paths include energy discharge routes around on-circuit voltage sources.

Abstract: An embodiment of the instant invention is an ESD protection circuit (100) for protecting a circuit from negative stress, the ESD protection circuit comprising: a first terminal (102); a second terminal (104), the circuit to be protected connected between the first and the second terminals; a substrate (202) of a first conductivity type; a first doped region (206) of a second conductivity type opposite the first conductivity type and formed in the substrate, the first doped region forming the source of a transistor; a second doped region (208) of the second conductivity and formed in the substrate spaced from the first doped region by a channel region, the second doped region forming the drain of the transistor; a first diode region (210) of the first conductivity type and formed in the substrate, the first diode region being spaced a minimum distance from the second doped region and wherein the first diode region forms the anode of a diode (108) and the second doped region forms the cathode of the diode; and

Abstract: An object of this invention is the creation of an input protection circuit for highly dense integrated circuits that has improved ESD immunity. This is accomplished by the addition of a P.sup.+ diffusion adjacent to the emitter of a field device to make the base resistance of each of the field devices approximately equal. When an ESD source is contacted to the input protection circuit, the field devices will conduct simultaneously and with equal currents, thus preventing high current densities that can cause circuit failure.

Abstract: One embodiment of the instant invention is an electrostatic discharge protection device (10) which includes a field-effect transistor, the field-effect transistor comprising: a substrate (12) of a first conductivity type and having a surface and a backside; a gate structure (18) insulatively disposed on the substrate; a blocking region (30) disposed on the substrate and adjacent to the gate structure; a lightly-doped region (32) of a second conductivity type opposite the first conductivity type and disposed within the substrate and beneath the blocking region; a channel region (14) disposed within the substrate, under the gate structure, and adjacent the lightly-doped region; a first doped region (38) of the second conductivity type and disposed within the substrate and adjacent to the lightly doped region, the first doped region spaced away from the channel region by the lightly-doped region; and a second doped region (22) of the second conductivity type and disposed within the substrate, the second doped re

Abstract: A device for protecting an integrated circuit against electrostatic discharges, and adapted for connection between a terminal and a ground of the integrated circuit, which includes a first transistor (Q2) connected between that terminal and ground by its emitter terminal and collector terminal, respectively, and a second transistor (Q1) which has its base terminal connected to the base terminal of the first transistor. The emitter and collector terminals of the second transistor (Q2) are connected to the collector of the first transistor (Q1).

Abstract: An electrostatic discharge (ESD) protection device includes a drain region and a source region, each having a heavily-doped region and a lightly-doped region, wherein the junction depth of the lightly-doped region is deeper than that of the heavily doped region. Accordingly, the ESD current density will be decreased owing to the enlarged junction area during the ESD event. In addition, the heat dissipation can be spread over the enlarged junction area instead of being focused on the drain cylindrical edge. Moreover, low parasitic capacitance in the bond pad is achieved because the junction capacitance of the lightly-doped region is smaller than that of the heavily-doped region. Furthermore, conducting blocks are arranged between the lightly-doped regions and the source/drain electrodes, respectively, to prevent the metal melt filament from spiking the junction.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.

Abstract: An input protection circuit which protects a first-stage inverter circuit against an electrostatic surge. The input protection circuit includes n-channel MIS type punch-through transistor for discharging the electrostatic surge to a ground terminal and a p-channel MIS type load transistor coupled between a signal input pad and the n-channel MIS type punch-through transistor, the p-channel MIS type load transistor having a gate and a back-gate concurrently applied with the electrostatic surge so that a dielectric breakdown hardly takes place in a gate insulating film.

Abstract: A protection device which protects against charge build up on a thin oxide gate during plasma etching is provided. The protection device may be described as a floating well PMOS device. When the PMOS transistor is formed, a lateral parasitic pnp transistor is also formed. In the lateral pnp device the base is floating, the collector is connected to ground and the emitter is connected to the gates of the host PMOS protection device and the device to be protected. In operation, the gate of the PMOS transistor is tied to the source of the PMOS transistor so that the PMOS transistor is off. Thus, the lateral pnp transistor controls the charging and discharging of the charge stored on the gate oxide. Excessive charge build up is prevented by the breakdown voltage of the lateral pnp transistor. Because protection is achieved by pnp breakdown operation, the size of the pnp protection device can be substantially lower than other protection devices.

Abstract: Protecting device structures are disclosed for protecting one or more protected nodes of an integrated circuit to be protected against electrostatic discharges (ESD). Typically the integrated circuit includes n channel MOS transistors having terminals connected to the protected nodes. In a specific embodiment, the protecting device structure includes an MOS diode structure having source and drain regions and at least a pair of localized auxiliary region. Each of this pair of localized auxiliary regions has a conductivity type that is opposite from that of the source and drain regions. These localized auxiliary regions are located contiguous with the source and drain regions, respectively, and in the channel between the source and drain regions. The protecting device structure is integrated in the integrated circuit and has a terminal that is connected to a terminal of each of the one or more protected nodes of the integrated circuit.

Abstract: An electrostatic discharge (ESD) protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, and which includes an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit driven by the transient detection circuit and connected between the VDD and VSS lines, wherein the discharge circuit includes a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein the bipolar transistor is implemented by a structure selected from a group consisting of a vertical bipolar transistor and a field oxide device, and wherein the bipolar transistor has a base that is driven by the transient detection circuit.

Abstract: A punchthrough-triggered ESD protection circuit which disposes an NMOS transistor at the anode gate of an lateral silicon-controlled rectifier, and a control circuit which provides a gate voltage for the gate of the NMOS transistor. By changing the channel length of the NMOS transistor as well as the gate voltage, the punchthrough voltage of the NMOS transistor is readily adjusted to a predetermined level. When ESD stress is present at the IC pad, the NMOS transistor goes into breakdown because of punchthrough and then triggers on the lateral silicon controlled rectifier. Thus, the trigger voltage of the ESD voltage can be lowered to the punchthrough voltage of the NMOS transistor. Accordingly, the ESD stress at the IC pad is bypassed by the conduction of the ESD protection circuit to allow an internal circuit to be protected from ESD damage.

Abstract: A semiconductor device with a semiconductor body (3) including a surface region (5) of a first conductivity type which adjoins a surface (4) and in which a field effect transistor (1) with insulated gate (6) is provided. The field effect transistor (1) has source and drain regions (7, 8, respectively) of the second, opposed conductivity type situated in the surface region (5), and a channel region (9) of the first conductivity type situated between the source and drain regions. A metal gate electrode (6) separated from the channel region (9) by an insulating layer (10) is provided over the channel region (9) and is provided with a protection device (2) against excessive voltages applied to the gate electrode (6).

Abstract: A structure is used for electrostatic discharge protection of an integrated circuit. The modified ladder structure includes drain regions which extend from an output pad. These are interleaved with source regions. For example, for a structure with two drain regions and two source regions, a first drain region extending from the output pad is separated from a first source region by a first gate region. A second drain region extending from the output pad is separated from the first drain region by a first insulating region. A second source region is separated from the second drain region by a second gate structure. For a structure with four drain regions and three source regions, there is additionally, a third drain region extending from the output pad. The third drain region is separated from the second source region by a third gate region. A fourth drain region extending from the output pad is separated from the third drain region by a second insulating region.

Abstract: A semiconductor device includes a metallic main line connected between an external terminal and an internal circuit, and a plurality of divided protection bipolar transistors connected in parallel to one another. Each of the divided protection bipolar transistors includes a collector and an emitter composed of first and second N diffused regions formed in a semiconductor substrate which are separated from each other. Each of the divided protection bipolar transistors also includes a base formed of a portion of a semiconductor substrate between the collector and the emitter. The collector is connected to a metallic sub line branched from the main line, and the emitter is connected to ground. The plurality of divided protection bipolar transistors have an equal breakdown voltage between the collector of the divided protection bipolar transistor and the semiconductor substrate.

Abstract: A horizontal MOSFET prevents itself from breakdown caused by an avalanche current which flows to a base of a parasitic bipolar transistor when avalanche breakdown of a diode formed between a drain and a substrate occurs. A current path, comprised of a back electrode or a layer with high impurity concentration, is disposed on the side of a back surface of a semiconductor substrate. This current path reduces the base current of the parasitic transistor. Due to this, heat generation caused by an operation of the parasitic transistor is suppressed, and the avalanche withstand capability of the MOSFET is improved corresponding to reduction of the internal resistance component of the MOSFET.

Abstract: An input protection circuit comprises an internal circuit and an input terminal, between which a pair of rectifying devices are interposed with polygonal diffusion regions of one and the other conduction types, which diffusion regions are formed longer along the width thereof orthogonal to the direction of current flow in the wiring than along the direction of current flow. The width of the contacts between said wiring and said diffusion regions is greater than the width of the wiring not having the contacts, thereby achieving a high electrostatic breakdown voltage.

Abstract: The present invention provides an input protection circuit including a first MOS FET including a source electrically connected to an input terminal and a drain and a gate both electrically connected to a grounding line, a second MOS FET including a source electrically connected to the input terminal and a drain and a gate, and a third MOS FET including a source electrically connected to a power line and a drain and a gate to both of which are electrically connected a drain and a gate of the second MOS FET. The input protection circuit shares a parasitic p-MOS transistor with an internal circuit, and hence it is no longer necessary to form a parasitic MOS transistor to be used only for an input protection circuit. Thus, the input protection circuit decreases the number of photomask using steps by one relative to a conventional protection circuit.

Abstract: Disclosed herein is an input protection circuit for a semiconductor device, which includes a first node, a second node, a power supply line, an input terminal connected to directly said first node, a first resistor connected between said first node and second node for decreasing surge voltage to said internal circuit from said input terminal, a first discharge circuit connected between said second node and said power supply line, and a second discharge circuit connected between said first node and said power supply line. The second node is in turn connected to an internal circuit having a MOS transistor to be protected.

Abstract: A protective circuit for a semiconductor integrated circuit having a MOS transistor is constructed of a protective device having a first conducting type of protective device region provided in the surface of a substrate and a second conducting type of first diffused part and second diffused part provided in the surface of the protective device region. The first diffused part is connected to a power line of the MOS transistor, and the second diffused part is connected to a signal line between an external input terminal and the MOS transistor. The bipolar operation of the protective device allows electric charge accumulated in the power line to be discharged from the external input terminal, and also allows electric charge accumulated in the external input terminal to be discharged from the power line. Accordingly, the occurrence of electrostatic breakdown in the semiconductor integrated circuit can be prevented.

Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.

Abstract: In a semiconductor device such as a CCD solid-state imager having terminals connected with protection transistors, a strength against a static electricity applied between a terminal and a ground (GND) and a strength against a static electricity applied between a terminal and a substrate and a strength against a static electricity between terminals can be improved.

Abstract: An integrated structure protection circuit suitable for protecting a power device against overvoltages comprises a plurality of serially connected junction diodes, each having a first electrode, represented by a highly doped region of a first conductivity type, and a second electrode represented by a medium doped or low doped region of a second conductivity type. A first diode of said plurality has its first electrode connected to a gate layer of said power device and its second electrode connected to the second electrode of at least one second diode of said plurality, and said at least one second diode has its first electrode connected to a drain region of the power device. The doping level of the second electrode of the diodes of said plurality is suitable to achieve sufficiently high breakdown voltage values.

Abstract: A semiconductor apparatus connected between a signal input line and a grounding line is formed on a semiconductor substrate with a protection circuit connected between the signal input line and the grounding line, in parallel with the semiconductor apparatus. The protection circuit is formed, for example, of bipolar transistors, diodes, or MOS transistors. The protection circuit is designed to prevent an excess signal supplied on the signal line from damaging the semiconductor apparatus, such as by breaking down a dielectric layer formed at a gate of a MOS transistor. The protection circuit may further be connected to a potential line that is connected to an external source of voltage.

Abstract: A semiconductor component for switching an inductive load, comprises first and second external terminals, first and second control terminals and a node. A vertical bipolar transistor has a base region and is disposed between the first external terminal and the node. A first vertical transistor is disposed between the node and the second external terminal. A zener diode and a second vertical transistor are connected parallel between the base and the node.

Abstract: A protection device, circuit, and a method of forming the same. A field oxide drain extended nMOS (FODENMOS) transistor (10) is located in an epitaxial region (16). The FODENMOS transistor (10) comprises a field oxide region (36a) that extends from the source diffused regions (22) to over a portion of the extended drain region (20). A drain diffused region (24) is located within the extended drain region (20). A gate electrode (40) may be located above the field oxide region (36a) if desired. Accordingly, there is no thin oxide interface between the gate electrode (40) and the extended drain region (20) that can lead to low ESD protection.

Abstract: An electrical overstress (EOS) protection circuit includes a pair of contra-directed diode-connected bipolar EOS transistors connected between two integrated circuit (IC) terminals. One of the EOS transistors has a reverse-biased junction and the other has a forward-biased junction when a voltage is applied across the IC terminals. A pair of parasitic bipolar transistors are formed in series to provide a current path between the EOS transistors. When the voltage difference between the IC terminals exceeds the breakdown voltage of the EOS transistor with a reverse-biased junction as during an electrostatic discharge event, the parasitic transistors activate the EOS transistor with a reverse-biased junction to divert ESD current from the IC.

Abstract: According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: An electrostatic discharge protection device for protecting the input of a circuit comprises a p-channel MOSFET (P-FET). The n-well with P+ implants of the P-FET provides a functional lateral PNP bipolar transistor that is coupled between the input of the circuit and a supply node of the circuit. Biasing circuitry controls biasing of the gate and n-well body of the P-FET in accordance with the voltage at the input of the circuit.

Abstract: A transistor circuit comprises a MOS transistor with an open back gate, and control means for controlling a voltage to be applied to the control gate of the MOS transistor, whereby the control means controls the avalanche breakdown voltage of a parasitic bipolar transistor formed by the drain, back gate and source of the MOS transistor.

Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.