Abstract: A semiconductor on insulator substrate has improved electrostatic performance without sacrificing the performance of commonly integrated high-speed integrated circuitry. The semiconductor on insulator substrate includes a single crystal semiconductor thin film having an integrated circuit region and an electrostatic protection region. The thickness of the single crystal semiconductor thin film is greater in the electrostatic protection region than in the integrated circuit region to thereby allow high-speed operation of devices formed in the integrated circuit region. Such a substrate has particular application as a driving substrate for a light valve. In such a device, the integrated circuit region includes thin film switching transistors for selectively applying a voltage to the liquid crystal layer and thin film driving transistors for driving the thin film switching transistors.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. Floating NMOS gates are capacitively coupled to V.sub.SS by a first-level metalization pattern. The metal-to-gate overlap capacitance and the gate-to-drain overlap capacitance define a voltage divider that leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer enter a conducting bipolar mode before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with gate array designs.

Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

Abstract: A thick-oxide ESD transistor for a BiCMOS integrated circuit has its source/drain contacts formed of the BiCMOS base or emitter polysilicon and its source/drain formed by an outdiffusion of the respective polysilicon contact. In one embodiment the BiCMOS resistor doping deepens the ESD source/drains, and in another embodiment the BiCMOS collector reach through doping deepens the ESD source/drains. The entire ESD transistor is fabricated from a standard BiCMOS process without any additional steps, has an area of about 100 square microns, can shunt up to 6000 volts, and has a turn-on time of about 10 picoseconds.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: A semiconductor device has protective devices formed in a P-type semiconductive region maintained at a ground potential and disposed adjacent to bonding pads connected to internal circuitry through respective signal lines. A plurality of first N+ diffusion regions connected to respective signal lines and a second diffusion region connected to a ground line are disposed in the P-type semiconductive region. A separating region having a thick insulating layer is disposed between the first diffusion regions and the second diffusion region. The protective devices formed as NPN transistors have a common emitter at the second N+ diffusion region, which has enough area for storing and discharging electric charges to the ground, while the occupied area of the protective devices is maintained small. The protective devices can be formed as so-called field MOS transistors having a common source.

Abstract: A semiconductor device for influencing the breakdown voltage of a transistor with a surface electrode arranged over a space charge region, separated from the same by an oxide layer. The surface electrode is at a potential, as determined by a voltage divider, between the potentials of the base and collector of the transistor. The surface electrode includes two electrode plates insulated from one another, with the first electrode plate extending over a junction between a highly doped n.sup.+ collector region and a lightly doped n.sup.- collector region, and a junction between the lightly doped n.sup.- collector region and a p-type base region. The second electrode plate is bonded partly over the oxide layer and partly with the highly doped n.sup.+ collector region.

Abstract: A protective device for protecting a CMOS circuit included in an internal circuit of an IC against overvoltage applied to a power source wiring and preventing the CMOS from being latched-up by surge voltage due to external noise during a normal operation of the IC is disclosed. An N channel MOS FET and a P channel MOS FET are arranged in parallel to each other and connected between a power source wiring and a ground wiring. Gate electrodes of the N channel and the P channel MOS FETs are connected to the ground wiring and the power source wiring, respectively. Positive overvoltage or surge voltage applied to the power source wiring is relieved by breakdown of drain junctions of both the MOS FETs.

Abstract: A buried contact module is provided that includes a dopant-diffusion buffer layer. The dopant-diffusion buffer layer is formed with a thin dielectric region fabricated between the polysilicon contact region and the well region. The dielectric region formed of, for example, silicon dioxide, limits the amount of phosphorous diffusion into the well region. Thus, a buried contact junction can be formed in an integrated circuit having a high punch-through voltage characteristic, a low junction leakage current characteristic and a low polysilicon resistance. In addition, the buried contact junction maintains a relatively low buried contact resistance.

Abstract: A semiconductor apparatus includes multiple protection devices to protect against electrostatic discharge to an internal circuit contained in the semiconductor apparatus. The semiconductor apparatus includes plural terminals including a ground terminal, a substrate bias terminal, a power supply terminal, and an input/output signal terminal. Plural protection devices are connected between various ones of these terminals to provide the necessary discharge protection for a variety of discharge scenarios.

Abstract: The protection device comprises a MOS transistor formed on the substrate of the integrated circuit and connected between a circuit pad and a reference terminal of the integrated circuit. A thyristor formed on the substrate is connected between the pad and the reference terminal. The control electrode of this thyristor consists of a region of the substrate in such a way that the thyristor can be triggerred by a current of charge carriers produced in the substrate by avalanche when a voltage rise occurs between the substrate and the drain of the MOS transistor.

Abstract: In an input/output protection circuit, since the drain of an input protection MOS transistor is directly connected to the cathode of input protection diode and the source and gate of the input protection MOS transistor and the anode of the input protection diode are respectively grounded, an excessive voltage supplied from an external electrode is received by the cathode of the input protection diode and the drain of the input protection MOS transistor before it reaches the internal circuit of a semiconductor device, so that the input/output protection circuit is free from the increase of junction capacitance due to the pattern of the input protection diode. Moreover, when an excessive voltage is input to the device, the input protection diode breaks down prior thereto so as to reduce the voltage at which the input protection MOS transistor starts to conduct. As a result, a high-speed and certain input protection is realized.

Abstract: An integrated structure protection device suitable for protecting a power MOS device from electrostatic discharges comprises a junction diode comprising a first electrode made of a highly doped region of a first conductivity type surrounded by a body region of a second conductivity type and representing a second electrode of the junction diode, which in turn is surrounded by a highly doped deep body region of said second conductivity type. The highly doped region is connected to a polysilicon gate layer representing the gate of the power MOS device, while the deep body region is connected to a source region of the power MOS.

Abstract: A protective circuit protects a plurality of protected portions having different withstand voltages and operation voltages of an active portion of a CCD solid state imaging device or the like by protective elements (e.g., transistors). The respective protected portions can be protected in an optimum fashion in response to the withstand voltages and operation voltages thereof. The breakdown voltages of the respective protective transistors are made different in response to the withstand voltages and operation voltages of the protected portions.

Abstract: An electrostatic discharge (ESD) protection device for protecting a high voltage operating circuit having a high voltage input terminal is disclosed. The ESD protection circuit has a substrate, a first diffusion region formed in the substrate connected to the high voltage input terminal, a second diffusion region formed in the substrate connected to ground, a field oxide layer over the substrate having a thickened region extending into the substrate between the first and second diffusion regions, and a drift region formed in the substrate and located between the first diffusion region and the thickened field oxide layer. These regions are so arranged to move the point of avalanche breakdown away from the first diffusion/field oxide interface, so that the avalanche breakdown voltage is lower than that of the protected circuit while simultaneously preventing avalanche included bipolar feedback in the protection device.

Abstract: A semiconductor component (1a) has first and second insulated gate field effect devices (T1 and T2) formed within the same seminconductor body (2). The devices (T1 and T2) have a common first main electrode (D) and an arrangement (20) provides a resistive connection (20b) between a second main electrode (S2)of the second device (T2) and the insulated gate (G1) of the first device (T1). The second device (T2) is formed so as to be more susceptible than the first device (T1) to parasitic bipolar transistor action for causing, when the first and second devices (T1 and T2) are turned off and a voltage exceeding a critical voltage (V.sub.

Abstract: A semiconductor input protective device has an NPN type blpolar transistor and an N-channel MOS transistor. In the NPN type bipolar transistor, the collector is connected to a signal line and the emitter and the base are commonly connected to a ground line. In the N-channel MOS transistor, either the drain or the source is connected to the signal line and the other of either the drain or the source is connected to the signal line and the gate is connected to either the signal line or the power source line. The N-channel MOS transistor has a threshold voltage higher than the power source voltage. The NPN type bipolar transistor and the N-channel MOS transistor having a thick gate insulation film are used as input protection elements so that, even when a high voltage interface is effected, the function of the protective MOS transistor is not interfered with.

Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.

Abstract: A circuit utilizable for protecting an integrated circuit feature from electrostatic discharge is disclosed. A first bipolar transistor has its emitter connected to the IC feature and its collector connected to ground. A second bipolar transistor has its emitter connected to the IC feature and its collector connected to its base and to the base of the first bipolar transistor. A field effect transistor has its gate and drain connected to the IC feature and its body connected to its source and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor. A diode has its cathode connected to the body and the source of the field effect transistor and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor.

Abstract: An ESD protection circuit and structure for implementation within an integrated circuit is disclosed. The protection circuit includes a diode, serving as a triggering device, and a lateral bipolar transistor. The triggering voltage of said diode is selected by an implant underlying a first field oxide structure adjacent a first diffused region to which the external terminal is connected. The lateral bipolar transistor uses the first diffused region to which the external terminal is connected as the collector region, a second diffused region opposite the first field oxide structure from said first diffused region as the emitter, and the substrate, or epitaxial layer, as the base. A second field oxide structure encircles the emitter region and has a distance thereacross which is selected in order to provide sufficient base resistance that, upon junction breakdown of the diode, the base-emitter junction of the lateral transistor is forward biased and the transistor turned on.

Abstract: The invention relates to an integrated circuit connected via a first connection conductor (61) to a first contact area. Between the first connection conductor (61) and a second connection conductor (63), a protection element (8) is connected, which protects the circuit especially from electrostatic discharges. The protection element (8) comprises an active zone (81), which is covered with metal silicide (15) and forms a pn junction (86) with the adjoining part (83) of the semiconductor body (10). On the metal silicide (15), the active zone (81) is provided with an electrode (16), through which the zone (81) is connected to the first connection conductor (61). The use of metal silicide in the integrated circuit in itself has great advantages, but in the protection element the metal silicide layer is found to give rise to a considerably lower reliability. The invention has for its object to obviate this disadvantage without it being necessary to modify the manufacturing process.

Abstract: Disclosed is a MOS transistor with high threshold voltage comprising, in a semiconductor substrate with a first type of conductivity, surface drain and source regions with the second type of conductivity having a high doping concentration, separated by a thick oxide zone in which there is formed, in the substrate, an overdoped region with the first type of conductivity. Each of the drain and source regions is inserted in a well with the second type of conductivity, having a low doping concentration, formed in the substrate.

Abstract: A technique for providing electrostatic discharge (ESD) protection for an open-drain CMOS I/O buffer circuit. having an output terminal. An NMOS enhancement-mode transistor has its drain connected to the VDD power bus for the buffer circuit, its source connected to the output terminal, and its gate connected to a noise-free internal VSS power bus (VSSI). The bulk region is connected to the VSS power bus (VSSE) for the I/O buffer circuit. ESD protection is provided by a parasitic lateral npn bipolar transistor that is inherent to the NMOS transistor. The parasitic lateral npn bipolar transistor has an emitter formed from the drain-to-bulk junction of the NMOS transistor, a collector formed from the source-to-bulk junction of the NMOS transistor, and a base formed in the bulk region.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: A semiconductor device equipped with an input protection circuit having a high withstand voltage and an improved reliability. The input protection circuit of the semiconductor device includes a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device, where one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.

Abstract: An input protection circuit includes an input protection resistor and an input protection element. The input protection resistor is connected at one end to an input pad and connected at the other end to the gate of a MOS transistor provided at the input stage of an internal circuit. The input protection element is connected between the gate of the MOS transistor and at least one of a ground terminal and a power source. The input protection resistor includes a first impurity diffused region of a second conductivity type formed in the main surface area of a semiconductor substrate of a first conductivity type, and a second impurity diffused region of the second conductivity type which is formed in the first impurity diffused region to have an impurity concentration higher than the first impurity diffused region and have a diffusion depth smaller than the first impurity diffused region.

Abstract: An integrated circuit electrostatic discharge (ESD) protection circuit employs a capacitor and a zener diode to trigger a thick oxide ESD shunt field effect transistor (FET). When an ESD induced voltage at an input or output node reaches the turn-on voltage determined by the zener diode breakdown voltage, the shunting transistor is turned on by current capacitively coupled to the base of the parasitic bipolar transistor inherently formed in the thick oxide FET. The parasitic bipolar transistor is turned on in its saturated mode, substantially shorting the node to ground. At the end of the ESD event when the ESD induced current is no longer sufficient to keep the shunting transistor in its saturated mode, the shunting transistor turns off and the ESD protection circuit returns to its off mode, monitoring the input or output node for the occurrence of another ESD event.