Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of a substrate. A pad oxide film is grown on the first surface of the substrate covering the p-wells and/or n-wells. A diffusion barrier(s) is deposited on the first surface of the substrate and a second surface of the substrate to form an encapsulated structure. The encapsulated structure is annealed to activate the n-type and/or p-type areas. A mask material is applied over the diffusion barrier on the first surface of the substrate to define active device areas and a dry etch process is used to etch away the unmasked potions of the diffusion barrier. The mask material is stripped and a field oxide is grown on the first surface of the substrate. A portion of the field oxide and all of the diffusion barrier is removed, resulting in active areas surrounded by a field isolation structure.

Abstract: A method is provided for manufacturing a semiconductor device that can secure a high breakdown voltage and yet optimize wells. The semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type, a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a source/drain layer of the second conductivity type formed in the semiconductor substrate. The well of the first conductivity type includes a channel region and is formed in a manner not to overlap the source/drain layers.

Abstract: A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.

Abstract: A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semiconductor substrate and having a first well of a second conductivity type and a second well of the first conductivity type formed within the first well, a second triple well formed in the semiconductor substrate and having a third well of the second conductivity type and a fourth well of the first conductivity type formed within the third well, a low breakdown voltage transistor of the second conductivity type formed at the second well, and a high breakdown voltage transistor of the second conductivity type formed at the fourth well. The first well of the first triple well can have an impurity concentration higher than an impurity concentration of the third well of the second triple well.

Abstract: A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is formed within and proximate to the trench structure to electrically connect surface portions of the substrate to the buried layer. The buried layer is used to provide a voltage source to an integrated circuit. In one application, a P-type buried layer provides ground potential or VSS to a source region of an N-channel FET transistor. In a second application, an N-type buried layer provides supply potential or VCC to a source of a P-channel FET transistor.

Abstract: A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.

Abstract: A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.

Abstract: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.

Abstract: A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.

Abstract: A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P?? blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P?? blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

Abstract: A substrate contains dissolved oxygen at a concentration of not more than 8×1017 atoms/cm3 and an impurity which is used as an acceptor or donor at a concentration of not more than 1×1015 atoms/cm3. In the substrate, an oxygen precipitation layer used to suppress occurrence of a slip starting from the rear surface of the substrate is formed. On the substrate, a silicon layer in which circuit elements are formed and which contains dissolved oxygen with at concentration of not more than 8×1017 atoms/cm3 and an impurity which is used as an acceptor or donor at a concentration of not more than 1×1015 atoms/cm3 is formed.

Abstract: A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.

Abstract: In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.

Abstract: An integrated MOS power transistors, in particular a lateral PMOS power transistor and a lateral n-DMOS power transistor, in which the bulk node is disposed in a manner spatially isolated from the source electrode zone. The particular integration structure of the MOS power transistor avoids a parasitic drain-bulk diode, a parasitic body diode and a substrate diode and thereby achieves an area-saving protection against over-currents in the event of reverse voltage polarity between drain and source.

Abstract: A method of fabricating a trench flash memory device, where the method includes forming a patterned mask layer on the substrate and using it as the mask for form a trench in the substrate. Next, a source region is formed in the substrate near the bottom of the trench, followed by forming a tunnel oxide layer, a floating gate, a gate dielectric layer and a control in the trench. After removing the mask layer to expose the substrate, a drain region is further formed in the substrate. In this invention, since the trench flash memory device has a cylindrical shape with the tunnel oxide layer, the floating gate and the gate dielectric layer wrapping around the control gate, the overlap area between the floating gate and the control gate is increased, resulting in a higher gate coupling rate (GCR), a lower required operation voltage and a higher device operation speed and efficiency.

Abstract: An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a well to isolate the transistor from the integrated circuit substrate. The transistor can be fabricated with a lower breakdown voltage level and still reduce a high voltage. The transistor can also be fabricated in the same manner as other transistors in the integrated circuit. A voltage regulator circuit is also described which incorporates the reduction circuit to allow the use of transistors which are not designed to handle an external voltage Vpp.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N?S and/or a second drain layer N?D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.

Abstract: A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.

Abstract: A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a semiconductor substrate, an isolation region for isolating the first and second transistors from each other, a slit formed in the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, a conductive film formed on the inner walls of the slit, and an interconnect layer having first and second portions, each of which is electrically connected with a corresponding one of the paired active regions, and a third portion which is formed along the slit on the isolation region to connect the first and second portions with each other.

Abstract: The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

Abstract: A semiconductor device includes a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films which is thicker than that of the lower threshold level MOSFET and, in addition, the gate oxide film of the higher threshold level MOSFET of n-type is thicker than that of the higher threshold level MOSFET of p-type. To fabricate the semiconductor device, implantation treatments of fluorine ions are carried out before the gate oxide treatment. Specifically, as for the higher threshold level MOSFETs of n- and p-types, implantation treatments of fluorine ions are independently carried out with unique implantation conditions.

Abstract: A semiconductor circuit arrangement includes a circuit element embedded in a semiconductor substrate of a first conductivity type in an integrated manner and is provided with at least one gate electrode and first and second terminal electrodes. The first terminal electrode includes a well region that is embedded in the semiconductor substrate and is of a second conductivity type which is opposite the first conductivity type. A sub-well region is embedded in the well region of the first terminal electrode and is of the second conductivity type and has a higher doping than said well region. The sub-well region is embedded in the surface of the substrate and ends without reaching a well region of the gate electrode which is of the first conductivity type.

Abstract: A manufacturing method for a dual-gate CMOS semiconductor device that suppresses mutual diffusion of P type impurities and N type impurities in a gate electrode. An NMOS part and a PMOS part are formed on a semiconductor substrate. A polycrystalline silicon layer is formed on the NMOS part and the PMOS part, and consists of an N type impurity containing polycrystalline silicon layer and a P type impurity containing polycrystalline silicon layer. A first conductive layer is formed on the polycrystalline silicon layer so as to include a groove region, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer and the P type impurity containing polycrystalline silicon layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. The semiconductor device includes: a semiconductor substrate of a first conductivity type; a first well of a second conductivity type formed in the semiconductor substrate; a second well of the first conductivity type formed within the first well; a third well of the second conductivity type formed within the first well; a low breakdown voltage transistor of the second conductivity type formed at the second well; a low breakdown voltage transistor of the first conductivity type formed at the third well; and a high breakdown voltage transistor of the first conductivity type formed at the first well. The second well and the third well have an impurity concentration higher than an impurity concentration of the first well.

Abstract: A MOSFET device including a semiconductor substrate, an SiGe layer provided on top of the semiconductor substrate, an Si layer provided on top of the SiGe layer; and a first isolation region for separating the Si layer into a first region and a second region, wherein the Si layer in the second region is turned into an Si epitaxial layer greater in thickness than the Si layer in the first region. The MOSFET device further includes at least one first MOSFET with the Si layer in the first region serving as a strained Si channel, and at least one second MOSFET with the Si epitaxial layer serving as an Si channel.

Abstract: Standard cell layout efficiency is improved by utilization of a MOS interconnect that minimizes features and geometries requiring compliance with space intensive design rules. Source diffusion regions of MOS structures have a substantially constant width extension extending toward a substrate pick-up diffusion and shares a common silicidation therewith to effect an ohmic contact thereto.

Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

Abstract: A semiconductor device with p-channel and n-channel field effect devices formed on a common substrate, where the drain and source regions of the n-channel field effect device are formed within a silicon epitaxial layer formed on a silicon layer germanium relax which is formed on a silicon germanium buffer layer with a graduated germanium concentration. Additionally, drain and source regions of the p-channel field effect device are formed within a silicon-germanium compound layer formed on the substrate and the silicon epitaxial cap layer formed on the silicon-germanium compound layer.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: To manufacture a liquid crystal display device with high thin film transistor accumulation, high productivity and high reliability by efficiently gettering a catalyst element, which promotes crystallization of an amorphous silicon film, from a channel region. In order to solve the above object, a step of providing a gettering sink on the outside of a p-channel thin film transistor region, and a step of removing a region provided on the outside of the thin film transistor region within the region where the catalyst element is gettered in a self-aligning manner by a source wiring or a drain wiring, are combined.

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal suicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal suicide can be formed.

Abstract: A method of forming medium breakdown voltage vertical transistors (11) and lateral transistors (12, 13) on the same substrate (14) provides for optimizing the epitaxial layer (16) for the lateral transistors (12, 13). The vertical transistor (11) is formed in a well (18) that has a lower resistivity than the epitaxial layer (16) to provide the required low on-resistance for the vertical power transistor (11).

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A method for fabricating a semiconductor device including a step of forming an interconnection having the upper surface covered with an insulation film on a base substrate, a step of sequentially depositing an insulation film and an insulation film on the base substrate with the interconnection formed on, a step of etching the insulation film with the insulation film as a stopper to form openings in a region containing a region where the interconnection is formed, and the step of etching the insulation film in the opening to form sidewall insulation films of the insulation film on the side walls of the interconnection and to form contact holes to be connected to the base substrate in alignment with the interconnection.

Abstract: A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.

Abstract: A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively.

Abstract: According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region.

Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.

Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.

Abstract: The invention relates to an integrated CMOS circuit comprising, in a semiconductor substrate (1) with a first type of conductivity, a casing (2) of a second type of retrograde-doped conductivity, the end of said casing being covered by an inter-casing insulating region (4). The components contained in said casing are separated from each other by means of intra-casing insulating regions (6,7). The first insulating elements (15) of the second type of high-level doping conductivity extend under each intra-casing insulating region. A second region (21) of the second type of high-level doping conductivity partially extends under the inter-casing insulator beyond the periphery of each casing.

Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.

Abstract: A semiconductor device has a p-type substrate, a low-concentration n-type region formed in the p-type substrate, a first high-concentration p-type region formed in the low-concentration n-type region and connected to a first electrode, a first high-concentration n-type region formed in the low-concentration n-type region and connected via a resistive element to the first electrode, a low-concentration p-type region formed contiguously with the first high-concentration n-type region, a second high-concentration n-type region and a second high-concentration p-type region formed in the p-type substrate and connected to a second electrode, and an element separator portion formed between the low-concentration p-type region and the second high-concentration n-type region. This makes it possible to control the switching characteristic of the electrostatic protection circuit with high accuracy and thus to cope with the thinning of the gate oxide film protected by the protection circuit.

Abstract: A semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device includes a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. The second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is equal in depth to the second well. The second and third wells are formed down to a level lower than the device isolation structure.