Abstract: A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state. In addition, the SRAM is fabricated in a process the emphasizes mismatches so that each individual cell assumes a non-random logic state when power is applied.

Abstract: A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is not more than 1 micrometer, and a gate length that is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the sourced/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.

Abstract: A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer.

Abstract: A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).

Abstract: A semiconductor is provided. The semiconductor device includes a transistor, a first strain layer and a second strain layer on a substrate. The first strain layer is configured at the periphery of the transistor. The second strain layer covers the transistor and a region exposed by the first strain layer. The stress provided by the second strain layer is different from that by the first strain layer.

Abstract: By depositing and forming a spacer out of a semiconductor material layer or a dielectric material layer on the edges of an inter-well isolation area while forming a plug over an intra-well isolation area, a narrow intra-well isolation trench having a normal depth is formed in the intra-well isolation area, while a wider inter-well isolation trench having an extended portion is formed in the inter-well isolation area. The extended portion of the inter-well isolation trench provides enhanced inter-well isolation due to the presence of the extended portion beneath the normal depth. The extended portion of the inter-well isolation trench enables reduction of the width of the intra-well isolation trench structure relative to prior art inter-well isolation structures having a normal depth.

Abstract: Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p? substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

Abstract: A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order to connect a junction to a gate layer weak to plasma damages, the gate layer is connected to the N+ or P+ junction when a first wiring layer after a transistor is formed. As a result, when the gate layer is charged up by plasma damages, the gate layer is discharged by the junction or provided to receive (?) ions or electrons so that a gate oxide is not affected by plasma damages.

Abstract: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film is formed to cover the n-type FET and p-type FET forming regions; exposing the surface of the semiconductor substrate by selectively removing the substrate protection film in the p-type FET forming region, leaving the film only on side walls of the second gate electrode; forming a pair of p-type extension regions at both sides of the second gate electrode, by doping impurities to the semiconductor substrate, with the resist film, the second gate electrode, and the substrate protection film formed on side walls of the second electrode; and removing the resist film formed on the n-type FET forming region.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET. A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

Abstract: A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

Abstract: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.

Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semiconductor region; a first gate insulating film formed on the n-type semiconductor region between the first source region and the first drain region; and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first nickel silicide layer having a Ni/Si composition ratio of 1 or greater, and a silicide layer formed on the first nickel silicide layer. The silicide layer contains a metal having a larger absolute value of oxide formation energy than that of Si, and a composition ratio of the metal to Si is smaller than the Ni/Si composition ratio.

Abstract: Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

Abstract: An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.

Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Abstract: The invention provides a semiconductor device and a method of forming the same. The method of forming the semiconductor device includes preparing a P-type semiconductor substrate including a low-voltage NMOS region, low-voltage PMOS region, high-voltage NMOS region, and high-voltage PMOS region; forming an N-well in the low-voltage PMOS region and high-voltage PMOS region; forming a P-well in the low-voltage NMOS region and high-voltage NMOS region; and forming a bouncing protection layer in a lower portion of the P-well of the low-voltage PMOS region.

Abstract: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.

Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.

Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.

Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Abstract: Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.

Abstract: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

Abstract: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Abstract: A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gate electrode that is formed on the second semiconductor layer; first conductive-source and drain layers that are formed in the second semiconductor layer and are arranged at sides of the gate electrode; and a first wiring layer that connects the first gate electrode to the first semiconductor layer.

Abstract: A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations.

Abstract: A current dissipation circuit that dissipates excess current to or from a circuit node when that monitored circuit node experiences abnormal voltage conditions, rather than having that excess current being dissipated through other protected circuitry. The current dissipation circuit may use single well technology, and may even provide reverse voltage protection without necessarily triggering more significant current dissipation. In another embodiment, the current dissipation circuit is provided by a series connection of at least five alternating p-type and n-type regions provided between the monitored circuit node and a current source or sink.

Abstract: At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circuit includes a deep n-type well located closer to the bottom side of the p-type Si substrate than the p-type well, so as to isolate the p-type well from a bottom-side region of the p-type Si substrate. The deep n-type well includes a first deep n-type well. The deep n-type well includes a second deep n-type well located closer to the bottom side of the p-type Si substrate than the first deep n-type well, and having an n-type impurity concentration, which is different from the first deep n-type well.

Abstract: A semiconductor resistor and a semiconductor process of making the same are provided. The semiconductor resistor comprises a substrate, a deep well, at least two contact regions, and a doped region. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The contact regions are heavily doped with the second type of ions, and formed in the deep well. The doped region is doped with the first type of ions, and is separated from the deep well by a distance. Wherein the first type of ions and the second type of ions are complementary, and the distance between the deep well and the doped region adjusts the breakdown voltage. In addition, the semiconductor process comprises the steps of forming a deep well containing a first type of ions; forming a doped region containing a second type of ions; forming an oxide layer; and forming at least two contact regions containing the first type of ions in the deep well.

Abstract: A CMOS semiconductor device includes: an isolation region formed in the surface layer of a semiconductor substrate to define an NMOSFET active region and a PMOSFET active region adjacent to each other; an NMOSFET structure formed in the NMOSFET active region; a PMOSFET structure formed in the PMOSFET active region; a tensile stress film covering the NMOSFET structure; and a compressive stress film covering the PMOSFET structure, wherein a border between the tensile stress film and the compressive stress film is set nearer to the PMOSFET active region than the NMOSFET active region along a gate width direction. A performance of a CMOS semiconductor device can be improved by the layout of the tensile and compressive stress films.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a driver configured to provide a drive signal to the switch and embodied in a transistor. The transistor includes a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor also includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.

Abstract: A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved by intentionally etching away field oxide outside the active area at least in the gate region so as to expose the sidewalls of the active area down to the channel-well PN junction or a buried gate which is in electrical contact with the well. Polysilicon is then deposited in the trench and doped heavily and an anneal step is used to drive impurities into the top and sidewalls of the channel region thereby creating a “wrap-around” gate region which reaches down the sidewalls of the channel region to the channel-well PN junction.

Abstract: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a second well in the LV/MV region for a logic device and a drift region for one of the HV devices using the same mask; and respectively forming gate oxide layers on the semiconductor substrate in the HV/MV/LV regions. According to the present invention, the number of photolithography processes can be reduced by replacing or combining an additional mask for forming an extended drain region of a high voltage depletion-enhancement CMOS (DECMOS) with a mask for forming a typical well of a logic device, so productivity of the total process of the device can be enhanced.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.