Abstract: A first shallow well 5, a second shallow well 3, a third deep well 4, a fourth shallow well 5' and a fifth shallow well 2 are formed on an electroconductive substrate 1, in which a first and second digital series power supplies DVDD, DVSS are each connected to the first shallow well 5 completely included by the third deep well 4 and the second shallow well 3 partially included by the third deep well 4 respectively, a first and second analog series power supplies AVDD, AVSS are each connected to the fourth and fifth shallow wells 5', 2 not included by the third deep well 4 respectively, a MOS transistor constituting a digital circuit is formed on the surface of the first and second shallow wells 5, 3 to which the digital series power supply is connected and a MOS transistor constituting an analog circuit is formed on the surface of the fourth and fifth shallow wells 5', 2 to which the analog series power supply is connected.

Abstract: A semiconductor device including a semiconductor substrate 1 and at least one first column-shaped semiconductor layer 10 of a first channel type formed on semiconductor substrate 1 in order of first, second and third regions, and having a side surface. At least one second column-shaped semiconductor layer 11 of a second channel type is selectively laminated on first semiconductor layer 10 in order of first, second and third regions, and having a side surface. A gate insulation film 8 is formed on the side surfaces of first semiconductor layer 10 and second semiconductor layer 11. A gate electrode 9 is formed on the insulation film 8 extending to an external portion of first semiconductor layer 10. A first source layer 2 and first drain layer 4 are respectively formed in the first and third regions of first semiconductor layer 10. A second source layer 7 and second drain layer 5 are respectively formed in the first and third regions of semiconductor layer 11.

Abstract: A semiconductor layer is disposed on a semiconductor substrate and a first element is formed in a region of the semiconductor layer. A second element is formed in another region of the semiconductor layer. An insulating layer surrounds the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate. An electrical shield layer surrounds the perimeter of the first element, and is adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element. An electrode is provided for applying the reference electric potential to the electrical shield layer.

Abstract: The present invention is a CMOS epitaxial silicon wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly doped monocrystalline silicon substrate (56) having a major surface (54) that supports a lightly doped monocrystalline epitaxial silicon layer (52). The substrate includes a heavily doped diffused layer (58) extending a short distance (64) into the substrate from the major surface toward a lightly doped bulk portion (66) of the substrate. CMOS integrated circuits manufactured on the epitaxial layer of the CMOS wafer of this invention have a low susceptibility to latch-up. The low susceptibility is provided by the relatively low resistivity of the diffused layer. Since the diffused layer is relatively thin and the bulk portion is lightly doped, the oxygen content of the bulk can be readily measured and controlled.

Abstract: A semiconductor integrated circuit device is fabricated from a complementary inverter circuit and an emitter coupled logic circuit, and an n-type well assigned to a p-channel type transistor extends beneath a p-type well assigned to an n-channel type transistor for partially overlapping therewith, thereby increasing capacitance across the p-n junction for eliminating noises from power voltages.

Abstract: To improve resistance to latch-up of complementary MOS semiconductor device, a high concentration buried layer (16) of same conduction type as a semiconductor substrate (1) and of concentration higher than the silicon semiconductor substrate is formed under a well region (5) of first conduction type in which MOS transistor of second conduction type is formed and a well region (3) of second conduction type in which MOS transistor of first conduction type is formed. The high concentration buried layer (16) reduces parasitic resistance of the semiconductor substrate (1), suppresses transfer of carrier due to surge or the like applied from outside and inside, and inhibits the parasitic transistors (12)(13) from turning on.

Abstract: A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.

Abstract: A semiconductor device has an upper well of a first conductivity type formed from the surface of an active region separated by an isolation oxide film at the surface of a semiconductor substrate to a predetermined depth. A first conductivity type layer of high concentration is formed along the entire region of an active region to enclose the bottom of the upper well of the first conductivity type. A lower well of the first conductivity type of a predetermined thickness is formed as a buried layer to enclose the bottom of the first conductivity type layer of high concentration. According to this structure, the spreadout of impurities into the active region due to diffusion at the time of thermal treatment is suppressed.

Abstract: In a semiconductor device, a charge transfer device, a bipolar transistor, and a MOSFET are formed on a single chip, and the peripheral portion of the charge transfer device is surrounded by an N.sup.+ -type region. Since the charge transfer device block is surrounded by the N.sup.+ -type region and the N.sup.+ -type buried layer, leaked charge of clocks from the charge transfer device is absorbed by the N.sup.+ -type region and the N.sup.+ -type buried layer.

Abstract: A complementary insulated gate field effect transistor comprises a semiconductor body having an effectively planar surface, the semiconductor body containing complementary conductivity type wells in which complementary transistors are formed. A field insulator layer is selectively formed on the surface of the body, the field insulator layer being hardened against radiation. That portion of the planar surface of the body on which the field insulator layer is formed is not lower than respective surface portions on which first and second gate insulator layers of the complementary conductivity type transistors are formed. In addition to respective gates, and source and drain region pairs, the complementary transistors have insulative spacers which abut sidewalls of the first and second gates and the field insulator layer and extend over portions of the source and drain regions.

Abstract: The impurity concentration of an n.sup.+ buried layer 51a in the region for forming a p channel MOS transistor 23 is higher than the impurity concentration of an n.sup.+ buried layer 3a in the region for forming an npn bipolar transistor 21. N.sup.+ buried layers 3a and 51a are formed on a p type silicon substrate 1. An n.sup.- well region 10 is formed as a region for forming npn bipolar transistor 21 on n.sup.+ buried layer 3a. An n well region 12 is formed as a region for forming p channel MOS transistor 23 on n.sup.+ buried layer 51a. While the performance of npn bipolar transistor 21 is maintained, the performance of a CMOS transistor formed of an n channel MOS transistor 22 and p channel MOS transistor 23 is improved. In a Bi-CMOS semiconductor device, the performance of a bipolar transistor portion is maintained, while preventing the formation of a punch through and improving the latch up tolerance of a CMOS transistor portion.

Abstract: A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.

Abstract: A semiconductor integrated circuit arrangement prevents the occurrence of latch up. The circuit includes a first semiconductor island of a first conductivity type and a second semiconductor island of the first conductivity type located within a base semiconductor region of a second conductivity type. A resistive diffusion region of the second conductivity type is located within the first semiconductor island region. The second semiconductor region is connected to ground. A high potential electrode connected to the resistive diffusion region is also connected to the first semiconductor island region. In this manner, an emitter and a base of a parasitic transistor of the integrated circuit are connected together to prevent the parasitic transistor from operating in a conductive state, thereby preventing latch up.

Abstract: A radiation hardened MOSFET is fabricated by forming a dielectric layer of boro-phosphosilicate glass (BPSG) over the field oxide layer of the MOSFET. The BPSG covers only a small part of the gate electrode of the MOSFET. The gate electrode of the MOSFET is formed from two layers of polycrystalline silicon so as to prevent contamination of the gate oxide by the BPSG dopants.

Abstract: A semiconductor device having a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on a major surface of the semiconductor subtrate, an isolation layer of the first conductivity type formed in the epitaxial layer and extending from a surface thereof to the major surface of the semiconductor substrate. The isolation layer divides the epitaxial layer into first, second, and third islands. The device further has two wells of the first conductivity type, formed in the first and second islands, respectively, and extending to the substrate, a charge transfer device having a back gate formed of the first well, an insulated-gate FET of the first conductivity type, having a back gate formed of the second island, an insulated-gate FET of the second conductivity type, having a back gate formed of the second well, and a bipolar transistor having a collector formed of the third island.

Abstract: A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.

Abstract: A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

Abstract: A semiconductor device comprises an MOSFET (13) comprising a switching gate electrode (5) and a field shield MOS structure (11) formed on an element isolating region of a semiconductor substrate (1) and performs the element isolation by applying a bias voltage to the field shield (9). The field shield (9) is provided on the element isolating region of the semiconductor substrate (1) through an insulating film (8). A sidewall spacer (12) having its width set such that the field shield (9) may be an offset gate is formed on the side portion of the field shield (9). Then, source and drain layers (6) are formed on the main surface of the semiconductor substrate (1) so as not to overlap with the field shield (9). According to the semiconductor device, since the field shield (9) is the offset gate, it is possible to set high the threshold value on a parasitic MOS transistor and miniaturize the elements.