Abstract: A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting when a metal silicide is used in the source/drain regions. A silicon wafer, is formed with a gate electrode material on a gate insulating layer before forming the trenches for isolation. Now, with an etch protective layer on the gate electrode, trenches are etched and filled with an insulating material in the gate electrode material, the gate insulating layer and the silicon wafer to isolate the active regions. After the gate electrode material is etched to define the gate electrodes, the tops of gate electrodes are in essentially the same plane as the tops of the trenches. Preferably in the fabrication process, sidewalls are formed on the walls of the trenches and the gate electrodes.

Abstract: An n well and a p well are formed in a silicon substrate. The n well has n type impurity concentration peaks and a p type impurity concentration peak. The p well has p type concentration peaks. The impurity concentration peaks serving as channel stopper regions for isolating elements exist only in proximity to the lower surface of an isolation oxide film but not in element regions.

Abstract: In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.

Abstract: A semiconductor memory device uses three different power supply voltage levels including an internal IVcc, ground Vss and a boosted level Vpp more positive than the internal Vcc. A precharge control circuit in the memory device includes at least one NMOS transistor, at least one PMOS transistor and an output node having voltage values ranging from the IVcc either to Vss or to Vpp. The NMOS transistor acts as a loading transistor to the PMOS transistor and prevents latch-up in the PMOS transistor by maintaining IVcc below Vpp during the initial power set-up period of the memory device.

Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: A semiconductor device having a butting-contact structure for stabilized contact resistance is disclosed. The semiconductor device includes, in the same number, PN regions each having a source region and a diffusion layer in the order with respect to a Y-axis positive direction and PN regions each having a source region and a diffusion layer placed reverse thereto. MOSFET elements have an identical shape in their PN contacts. The interval of the PN contacts is determined equivalent to the interval of boundary lines of the ON regions. The PN contacts are provided such that their centers substantially align with respective boundary lines of the PN regions. Therefore, even when deviation occurs between the PN region and the PN contact along the Y-axis direction, there is provided a equivalency between the sum of areas of the source contact and the sum of areas of the diffusion layer contacts throughout the device.

Abstract: An integrated circuit device has a plurality of active devices which are formed on a semiconductor body. A plurality of narrow isolating regions of insulating material are vertically formed on the semiconductor body such that at least one of the narrow isolating regions separates and thereby isolates adjacent active devices. Essentially all of said isolating regions are substantially equal in width, preferably less than or equal to about 0.5 .mu.m.

Abstract: The earth wire is a conductive lead located at the nearest position to a flat surface of the semiconductor substrate, and the earth wire and the word lines are arranged so that these are not formed on the other wires in the memory cell, the wiring resistance is reduced by shortening the wiring length, and there is little unevenness in the underlayer of the earth wire, whereby the read-out operation is stabilized. Furthermore, the earth wire is formed of a wiring layer which is near to the semiconductor substrate, so that the distance between the earth wire and a load element is set to be larger than that in the prior art. Therefore, it can be prevented that the earth wire acts as the gate electrode of a parasitic transistor and thus malfunction occurs. In addition, the shape of the field pattern can be simplified.

Abstract: A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

Abstract: The semiconductor, device comprising a P type semiconductor substrate, first and second P-wells, an N-well between the first and the second P-wells, trench element-isolating films for electrically separating the wells from each other and the first P-well from the P type semiconductor substrate, and an N type buried region formed below a first P-well between the trench element-isolating films, which is suitable to high integration and improved in operating speed.

Abstract: An integrated power semiconductor component includes a substrate of a first conduction type. At least one first region of a second conduction type is embedded in the substrate and at least one second region of the second conduction type is embedded in the substrate. A substrate contact supplies a supply voltage. Contact-making semiconductor components are embedded in the first region and in the second region. At least a portion of the semiconductor components in the first region control at least a portion of the semiconductor components in the second region. A third region of the second conduction type is disposed between the first region and the second region, and the first region and the third region are at different potentials.

Abstract: An apparatus and method for providing improved latch-up immunity in a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. An exemplary apparatus includes a first region of semiconductor material of a first conductivity type, a well of semiconductor material formed in the first region and having a second conductivity type opposite to the first conductivity type, a first MOS transistor formed in the well and including a source region and a drain region formed of semiconductor material of the first conductivity type, and a second MOS transistor formed in the first region and having a source region and a drain region formed of semiconductor material of the second conductivity type. A conductive material or other suitable routing means is connected between the source region of one of the first or second MOS transistors and a corresponding voltage supply input of the device.

Abstract: A polysilicon field ring structure is used to eliminate any type of unwanted surface current leakage in an integrated power chip having high voltage and low voltage areas and enclosed in a plastic housing. All P-type diffusions not biased to the ground potential are surrounded by rings biased to the supply potential, and all N-type diffusions not biased to the supply potential are surrounded by rings biased to the ground potential.

Abstract: Disclosed is a semiconductor device, which has: a first device-separating insulating film which is formed on a semiconductor substrate and extends in a first(Y) direction; a second device-separating insulting film which is formed on said semiconductor substrate and extends in a second(X) direction normal to the first(Y) direction; a first-conductivity-type device region which is formed on the semiconductor substrate and is sectioned by the first and second device-separating insulating films; and a first first-conductive-type high concentration impurity layer which is formed under the first device-separating insulating film and extends in the first(Y) direction; wherein the second device-separating insulating film is connected with the first device-separating insulating film through an insulating film thinner than both the first and second device-separating insulating films, the thin insulating film extending over the first high concentration impurity layer to separate the device region arranged in the second(

Abstract: An integrated circuit including a power stage, a low-voltage component separated from the power stage by an isolating region and a reference potential region at a reference potential. The power stage includes an N-type substrate region which may be biased to a terminal voltage with respect to the reference potential and the isolating region has P-type conductivity. The low-voltage component includes an N-type input region receiving an input voltage. The input voltage and the terminal voltage may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors. To prevent turning on of the parasitic transistors, switchable conductive paths are interposed between the isolating region on the one hand, and the substrate region, the input region and the reference potential region on the other, for electrically connecting the isolating region to one of the substrate region, input region and reference potential region which presents instant by instant the lowest potential.

Abstract: A MOSFET has shallow trenches of a thick oxide for isolating the MOSFET device from a surrounding substrate. The MOSFET has a gate wiring layer that includes co-aligned metallurgy of a predetermined work function at regions where the gate wiring layer passes over the oxide of the isolation trenches. The co-aligned metallurgy of predetermined work function is operative to increase the parasitic threshold voltage associated with the MOSFET's parasitic leakage currents.

Abstract: A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; the outer diffusion layer having an impurity concentration sufficient to provide a desired junction withstand voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; the impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power suppl

Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.

Abstract: A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Abstract: The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced sidewall junction capacitance and leakage, an increased junction breakdown voltage and a reduced narrow channel effect.

Abstract: A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

Abstract: In a MOS-type semiconductor device having a semiconductor substrate, a drain region, a source region, and a gate electrode between the drain region and the source region, a substrate contact region of a conductivity type the same as that of the semiconductor substrate is formed adjacent to the source region, and is wider than the source region and the drain region.

Abstract: A thin-film semiconductor device having a CMOS inverter comprising a pair of n-type and p-type thin-film transistors, wherein the gate electrode of at least one of the paired thin-film transistors comprises a plurality of gate electrode sections spaced apart along the channel length. The channel region of the n-type thin-film transistor is doped with p-type impurities. This structure serves to reduce the leakage current and maintain high OFF resistance for a high source-drain voltage. Further, since a good symmetry of characteristics is maintained between the n-type and p-type thin-film transistors that constitute the CMOS inverter, no appreciable bias is caused in the output voltage of the CMOS inverter.

Abstract: An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers.

Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Abstract: A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.

Abstract: An integrated circuit device (10) is provided that comprises an P-FET (12) and an N-FET (14) formed on a semiconductor substrate (32). The P-FET (12) is formed in an n- tank (46). The source (18) and back-gate contact (22) of the P-FET (12) are connected to the V.sub.DD supply voltage. A current sink region (50) is formed in contact with the bulk semiconductor substrate (32). Periodic back-gate contacts (30) and (52) are made to the current sink region (50). The source (26) of N-FET (14) is also connected to the back-gate contacts (30) and (52). The current sink region (50) provides a low resistance path for charge within the substrate (32) to paths to the supply voltage V.sub.SS. This low resistance path prevents voltage from building up in the substrate (32) and thereby prevents latchup from occurring.

Abstract: Efficient control of the body voltage embodiment, the body node of a first field effect transistor is connected to the gate of the first transistor through a second field effect transistor. In another embodiment, the body node (p-) of a first transistor is connected to a drain (3) of the first transistor through a second transistor in an area efficient manner. The first and second transistors have a common drain (3) and the gate of the second transistor is an extension of the gate (G) of the first transistor.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: An Electrically Erasable PROM (E.sup.2 PROM) according to the present invention includes a semiconductor substrate of a first conductivity type having a field oxide formed on a predetermined region of the main surface thereof; a memory section formed on the semiconductor substrate; and a peripheral circuit section formed in the peripheral of the memory section, wherein the peripheral circuit section has a CMOS structure in which an N-channel MOS transistor and a P-channel MOS transistor are connected to each other in a complementary manner; one of the N-channel MOS transistor and the P-channel MOS transistor is a thin film transistor formed on the field oxide and the other is a MOS transistor formed on the semiconductor substrate; and the memory section includes a plurality of non-volatile transistors formed on the semiconductor substrate.

Abstract: In a semiconductor device having a digital circuit region and an analog circuit region formed on an N type semiconductor substrate, a P type well region is formed on the semiconductor substrate and between the digital circuit region and the analog circuit region. Furthermore, an N type first diffusion layer is formed on the well region. In the semiconductor device, the isolating portion formed between the digital and analog circuit regions not only shuts off an electrical noise between the regions but also absorbs an electrostatic surge input from an external device to a power source terminal, thereby protecting the digital and analog circuit regions from electrostatic breakdown.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: The present invention is directed to a CMOS inverter in which an N-FET (Qn) formed of an N-type source region (2S), a drain region (2D) and a gate electrode (2G) and a P-FET (Qp) formed of a P-type source region (3S), a drain region (3D) and a gate electrode (3G) are formed on an N-type silicon substrate (1n). A first well region (4p) is formed under the N-FET (Qn) and P-FET (Qp). Further, an N-type well region (5n) is formed on the P-FET (Qp) within the first well region (4p). Thus, an influence exerted by a back-gate effect from the substrate can be prevented completely, whereby a phase displacement relative to a pulse response to a CMOS peripheral logic circuit and a malfunction can be avoided.

Abstract: An integrated-circuit (IC) chip formed with a fault-protected switch comprising three MOS transistors in series. An additional MOS transistor is formed adjacent the center one of the three transistors, and is arranged such that the gates of the two transistors are connected together, the source electrodes of the two transistors are connected together, the backgates form a common region, and the drain of the additional transistor is connected to those backgates.

Abstract: A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

Abstract: A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current.

Abstract: A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.

Abstract: A LOCOS oxide film is provided in a main surface of a semiconductor substrate for isolating an element region from another element region. A channel cut layer formed of a P-type impurity is provided under the element region. A P.sup.+ impurity region having a concentration thicker than that of P-type impurity of channel cut layer is formed directly under a bird's beak portion of LOCOS oxide film in the main surface of semiconductor substrate. Therefore, an isolation breakdown voltage of an N-channel transistor region is increased.

Abstract: An integrated-circuit (IC) chip formed with a fault-protected switch comprising three MOS transistors in series. Each transistor is placed in a corresponding tub of the IC chip. Each of these tubs is electrically isolated from all other sections of the IC chip, so that the MOS transistors are isolated from one another and from the chip voltage supplies.

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract: Disclosed herein is a Bi-CMOS IC which includes a semiconductor substrate of one conductivity type, a semiconductor layer of an opposite conductivity type formed on the substrate, a buried region of the opposite conductivity type formed between a first part of the semiconductor layer and the substrate and elongated under a second part of the semiconductor layer to form an elongated buried portion, a bipolar transistor formed in the first part by using the first part as a collector region thereof, a semiconductor region of the one conductivity type formed in the second part in contact with the elongated buried portion separately from the substrate, and an insulated gate transistor formed in the semiconductor region.

Abstract: An epitaxial layer is formed on a semiconductor substrate, and a CMOS circuit or a functional device is formed on an impurity layer deeply extended to reach the semiconductor substrate and on an epitaxial layer region surrounded by the impurity layer. Thus the devices are substantially equivalent to those formed on a silicon substrate having no epitaxial layer. A CMOS circuit or functional device formed on an impurity layer that does not reach the semiconductor substrate and on the epitaxial layer region is made electrically independent of the semiconductor substrate, and hence can be deemed to be substantially equivalent to the case when the epitaxial layer is made to serve as a substrate.An epitaxial layer of a conductivity type reverse to that of a silicon substrate is used, and hence a plurality of functional devices can be formed respectively thereon at the same time.

Abstract: A semiconductor memory device, e.g., a DRAM, which includes a P-type semiconductor substrate, a memory array each memory cell of which includes at least one N-channel MOS transistor, a CMOS peripheral circuit at least partially surrounding the memory array, the peripheral circuit including at least one P-channel MOS transistor formed in an N-type well region formed in the substrate, and at least one N-channel MOS transistor formed in the substrate outside of the N-type well region, and, a P-type minority carrier absorption semiconductor region formed in the substrate between the N-type well region and the memory array. The minority carrier absorption semiconductor region is preferably connected to a source of negative voltage, e.g., the substrate bias voltage, and a separate N-type region formed in the N-type well region is preferably connected to a source of positive voltage, e.g., the power supply voltage, Vdd, of the memory device.

Abstract: An object of the present invention is to provide a semiconductor integrated circuit in which an EEPROM is incorporated in a highly integrated microcomputer having a twin well structure. A twin well region including an n-well region, a p-well region, and a p-type substrate region surrounded by a p-well region are produced in a single semiconductor substrate. A supply voltage system made up of a CPU, a ROM or RAM, a UART, and EEPROM control systems to which the high voltage for the EEPROM is not applied is formed in the twin well region as a CMOS structure, enabling high density integration. A high-voltage system made up of an EEPROM memory cell array and an EEPROM peripheral high-voltage system in the p-type region have an NMOS structure. This arrangement minimizes the substrate effect and enables the high-voltage system to operate normally.

Abstract: A structure and its fabrication method of an integrated semiconductor device including circuit elements such as MOSFETs. A well is formed in the semiconductor substrate within windows of a field oxide layer. A lightly-doped semiconductor layer is selectively formed on the exposed surface of the well. A channel region and a pair of source and drain regions of a MOSFET are formed in the lightly-doped semiconductor layer. The highly-doped buried semiconductor layer of the same conductivity type as that of the lightly-doped semiconductor layer is formed under the channel region in the lightly-doped semiconductor layer. The structural features and fabrication method provides a great degree of freedom in designing a MOSFET having a further shorter-channel length without deteriorating its drivability and punch-through breakdown voltage.

Abstract: A CMOS output circuit including a pMOS transistor and an nMOS transistor connected in series between a power supply voltage and a ground voltage, is formed with a resistive component for reducing occurrence of latch-up. The resistive component is arranged at least one of the sources of the pMOS and nMOS transistors so as to be connected in series with a parasitic bipolar transistor formed between the power supply voltage and the ground voltage through its emitter. The resistive component limits the collector current of the parasitic bipolar transistor at a time that a triggering voltage is applied to an output terminal of the output circuit, so that the parasitic bipolar transistor does not turn on readily, thereby resulting in reduced possibility of occurrence of latch-up.

Abstract: First and second well regions of a second conductivity type are formed in a semiconductor substrate of a first conductivity type. An analog circuit is formed in the first well region. A digital circuit is formed in the second well region.

Abstract: A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith.