Abstract: A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Abstract: In a field effect transistor including a semiconductor substrate which is divided into an active area and an inactive area, a comb-shaped gate electrode having a trunk portion formed on the inactive area and gate fingers formed on the active area, source ohmic electrodes and drain ohmic electrodes formed on the active area and alternating with the gate fingers of the comb-shaped gate electrodes, a comb-shaped source lead-out electrode having a trunk portion formed on the inactive area and fingers each connected to one of the source ohmic electrodes and formed on the active area, and a comb-shaped drain lead-out electrode having a trunk portion formed on the inactive area and fingers each connected to one of the drain ohmic electrodes and formed on the active area, edges of the fingers of the comb-shaped source lead-out electrode recede from edges of respective ones of the source ohmic electrodes, or edges of the fingers of the comb-shaped drain lead-out electrode recede from edges of respective ones of the dr

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A novel method and system for fabricating integrated circuit devices is disclosed herein. In one embodiment, the method comprises determining at least one electrical performance characteristic of a plurality of semiconductor devices formed above at least one semiconducting substrate, providing the determined electrical performance characteristics to a controller that determines, based upon the determined electrical characteristics, across-substrate variations in an exposure dose of a stepper exposure process to be performed on at least one subsequently processed substrate, and performing the stepper exposure process comprised of the across-substrate variations in exposure dose on the subsequently processed substrates.

Abstract: Each inverter includes any of a P-channel modulation MOS transistor, a normal N-channel MOS transistor, a normal P-channel MOS transistor, and an N-channel modulation MOS transistor. A modulation substrate bias Vb of the P-channel modulation MOS transistor varies with a prescribed amplitude within the range of Vb. Vdd−Vf. A modulation substrate bias Vb′ of the N-channel modulation MOS transistor varies with a prescribed amplitude within the range of Vb′. Vss+Vf′. With a threshold value of the modulation MOS transistor being varied, the transition timing and waveform of a signal are varied, whereby the peak of the EMI radiation becomes gentler. As a result, EMI radiation is reduced while preventing malfunction such as latch-up.

Abstract: A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.

Abstract: The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Abstract: The present invention provides a circuitry comprising: a first switching transistor connected in series between an output node and a first voltage supply line which supplies a fist voltage level, the first switching transistor having a first control gate receiving a first control signal; and a second switching transistor connected in series between the output node and a second voltage supply line which supplies a second voltage level which is lower than the first voltage level, the second switching transistor having a second control gate receiving a second control signal, so that the first and second switching transistors are connected in series between the first and second voltage supply lines, wherein the first switching transistor has a first sub-gate which is connected to the output node, and the second switching transistor has a second sub-gate which is connected to the second voltage supply line.

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protective circuit is disclosed. In this semiconductor device with an ESD protective circuit, an n-well guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer. The n-well guard ring is strapped to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, and thus a PNPN path is formed toward the PMOS transistor at a positive mode of the ground voltage. Therefore, the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device. Further the layout area is reduced, and thus, the characteristics and the reliability of the semiconductor device are improved.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: The ESD protective circuit proceeds from a modified lateral pnpn “latch-up” protective structure having a highly doped n-type zone, which is arranged on the well boundary, along that section of the periphery of the well which runs between the two oppositely doped regions. The highly doped zone is formed of pads arranged with intermediate spacing along the section of the periphery of the well. The result is a low triggering voltage in conjunction with a low on resistance.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: In a semiconductor substrate of a first conductivity type, first and second high-concentration layers of a second conductivity type are formed in spaced relation to each other. A reference voltage is applied to the second high-concentration layer. A conductive layer provides an electrical connection between the first high-concentration layer and an input pad for inputting an input signal to an input circuit or input/output circuit. A first low-concentration layer of the second conductivity type is formed in the region of the semiconductor substrate immediately underlying the first high-concentration layer.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: In important applications of circuits comprising transistors of the lateral DMOST type, such as (half) bridges, the voltage on the output may become higher or lower than the supply voltage or earth in the case of an inductive load. The injection of charge carriers into the substrate can be prevented by screening the drain (18) of the Low-Side transistor from the substrate by means of a p-type buried layer (13) and an n-type buried layer (14) below said p-type buried layer. In order to avoid parasitic npn-action between the n-type buried layer (14) and the n-type drain (18), not only the back-gate regions (16a, 16c) at the edge of the transistor, but also the back-gate regions (16b) in the center of the transistor, are connected to the p-type buried layer, for example by means of a p-type well. As a result, throughout the relatively high-ohmic buried layer, the potential is well defined, so that said npn-action is prevented.

Abstract: A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a second node. A first capacitor has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal. A second transistor has a first channel terminal coupled to the second node of the charge pump, and a second channel terminal coupled to its gate and to a third node. A second capacitor has a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.

Abstract: Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffusion of the further dopant of the second conductivity type, independently of the deep concentration, since the dopant concentration at the surface can be chosen independently of the dopant concentration at depth. A low film resistance results from the great penetration depth of the semiconductor region through the combination of the two dopant profiles. The low film resistance leads to reduced pinching of the substrate current in an NMOS transistor, and to greater stability against “latch-up”, without substantially increasing the concentration of the dopants in the region of source/drain diffusions, and therefore without unfavorably affecting drain/bulk capacitance.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage Vdd, and the buried p-well is shorted to a reference voltage Vss via both the P substrate and a P+ ground tab. The proposed methods do not require additional mask or processes.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

Abstract: A CMOS integrated circuit is formed on a P-type semiconductor layer and an N-type semiconductor layer in contact with the P-type semiconductor layer to establish a junction therebetween. A PMOS transistor is formed on the N-type semiconductor layer and configured with its source terminal connected to a first voltage source. An N-type contract region is formed in the N-type semiconductor layer and connected to the first voltage source. An NMOS transistor is formed on the P-type semiconductor layer and configured with its source terminal connected to a second voltage source. A P-type contact region is formed in the P-type semiconductor layer and connected to the second voltage source. Moreover, a P-type carrier-releasing region is provided with one portion formed in the N-type semiconductor layer and another portion formed in the P-type semiconductor layer to span the junction.

Abstract: The invention relates to an ion implantation method for adjusting the threshold voltage of MOS transistors. The MOS transistor is employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprises a substrate, a gate insulating layer positioned on the substrate, and a gate conducting layer with a rectangular-shaped cross section positioned on the gate insulating layer. The method comprises performing an ion implantation process at a predetermined dosage and ion energy to implant dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the superficial portion of the substrate below the gate insulating layer.

Abstract: In a semiconductor memory device has a first contact region that is provided with a plurality of contacts in the source/drain region on one side of a third interconnect, and a second contact region that is provided with a plurality of contacts in the source/drain region on the other side of the third interconnect. The source region is connected via the contacts of a first contact region to the first interconnect, and the drain region is connected via the contacts of the first contact region to the second interconnect.

Abstract: In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.

Abstract: An MOS device has source and drain regions of a first conductivity formed in a well of a second conductivity, the well of the second conductivity being formed in an upper surface of a bulk material of the first conductivity. Source and drain potentials are applied to the source and drain regions, respectively, while a separate bias potential is routed to the well through a conductive sub-surface layer of the second conductivity which is located spaced from and beneath an upper surface of the bulk material and which is shorted to the well.

Abstract: The component has a channel zone and an oppositely doped zone in a semiconductor substrate. The channel zone and a peripheral region of the first doped zone are separated by a gate dielectric from an overlying channel gate electrode. The first doped zone is predominantly separated by a tunnel dielectric from an overlying tunnel gate electrode. When a suitable voltage is applied to the first doped zone, the tunnel current from the tunnel gate electrode generates an avalanche breakdown in the semiconductor substrate. A current results between the terminals of the channel zone and the first doped zones that is amplified by several orders of magnitude.

Abstract: A source region 3 and a back-gate region 4 are alternately arranged along one side of a gate electrode 2 in a power MOSFET. The back-gate region 4 is formed so as not to substantially include the region immediately below the gate electrode 2. Thereby, it is possible to prevent a parasitic bipolar transistor from operating while controlling the increase of a channel resistance and thus, the breakdown resistance is improved.

Abstract: A p− epitaxial layer is formed on the main surface of a p+ silicon substrate. A p-type impurity region is formed extending from the main surface into epitaxial layer. P-type impurity region has a first region having a relatively large thickness and a second region having a relatively small thickness. A p-well is formed on first region and an n-well is formed on second region. A p MOS transistor is formed on n-well and an n MOS transistor is formed on p-well.

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

Abstract: A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply.

Abstract: A semiconductor device comprises a semiconductor layer formed on an insulation layer, a pair of source and drain diffusion layer formed on a surface of the semiconductor layer, a first gate electrode disposed on the semiconductor layer region interposed between the pair of source and drain diffusion layer through a gate insulation film, a substrate potential control layer coupled to the semiconductor layer in a region interposed between the pair of the source and drain diffusion layer and formed in such a manner that the first gate electrode does not exist thereon, and a second gate electrode disposed to be in contact with the first gate electrode.

Abstract: A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

Abstract: A semiconductor device includes: a semiconductor substrate; a well region of a first conductivity type formed; a well region of a second conductivity type; a trench isolation region; a source region and a drain region of the first conductivity type; a channel region formed; a gate insulating film; and a gate electrode being electrically connected to the well region of the second conductivity type, wherein the product &tgr;, i.e.

Abstract: A dummy pattern that is inserted to stabilize the form of a transistor active region is implanted with an impurity of the same conductivity type as a well, and the impurity-doped region of the dummy pattern is supplied with a potential through a metal interconnection. Hence, fluctuation of a well potential due to noise hardly occurs, and a semiconductor device enduring latch up, for example, to a greater extent can be provided.

Abstract: In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.

Abstract: An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

Abstract: In a semiconductor device in which a source and a drain are formed on both sides of a buried gate provided in a trench, metal wires for the source and the drain are provided above the source and drain, via an intervening interlayer insulation film, a wire for a gate being provided so as to be sandwiched between the source and drain wires, this being formed on the same level of interconnect layers as the source and drain wires and being formed over the gate.

Abstract: A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region.