Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: The NMOS transistor is provided with a semiconducting substrate (12) which is p-doped and comprises a top side (14), and with a first region (16) which is n-doped and placed into the substrate by diffusion from the top side (14) of the substrate (12). Further, the transistor comprises a second region (18) arranged within the n-conducting region (16), which is n-doped and introduced into the substrate from the top side (14) of the substrate (12), and a field oxide layer (20) which is arranged on the top side (14) of the substrate (12) and limits the p-conducting region (16) on all sides. The top side comprises a source region (22) and a drain region (24) which are n-doped and arranged within the p-conducting region (18) at a distance to each other. A gate oxide layer (26) is arranged on the top side (14) of the substrate (12) between the source and the drain regions (22, 24).

Abstract: A method is provided for forming a triple well of a semiconductor memory device, where a second well of a second conductive type encloses a second well of a first conductive type. A single mask is used for ion implanting the base of the enclosing well and also the entire enclosed well, which inherently avoids misalignment. Additional doping is provided to the location where the sidewalls of the enclosing well join its base. This is accomplished either by a second, deeper ion implant of the sidewalls, or by ion implanting the base at an angle and rotating it, or both. Alternately, the single mask pattern is processed between the ion implantation steps to alter its width.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

Abstract: A semiconductor integrated circuit is made up of a plurality of input-output circuit portions which are aligned at irregular intervals between a core portion and an external portion, a first guard-ring which is formed in the respective input-output circuit portions, and a second guard-ring which is formed between the respective input-output circuit portions. Accordingly, the semiconductor integrated circuit can prevent latch-up between the respective input-output circuit portions without changing the layout of the respective input-output circuit portions.

Abstract: A semiconductor device (10) having a stacked-gate buffer (30) wherein the stacked-gate buffer (30) has a substrate (65) and a top substrate region (70) both with the same first conductivity type. The buffer (30) also has two transistors (95.105), each with a current carrying electrode and a control electrode (90, 100). A deep doped region (120) lies between the first (90) and second (100) control electrodes where the deep doped region (120) is another current carrying electrode for the first transistor (95) and another current carrying electrode for the second transistor (105) and the deep doped region (120) has a second conductivity that is opposite the first conductivity type. A deeper doped region (80) is also part of the stacked-gate buffer which has a second conductivity type and lies between the first (90) and second (100) control electrodes and is deeper than the deep doped region (120). A method of forming the device is also provided herein.

Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second a-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: There is described a semiconductor device intended to increase a degree of integration of transistor without impairing a desired element characteristic. An n-type source region and an n-type drain region are formed in a p-well which acts as a substrate region of an NMOS transistor. Further, there are formed a first contact plug to be electrically connected to the n-type source region and a second contact plug to be electrically connected to the n-type drain region. The n-type source region is provided so as to become short-circuited with the p-well. The n-type drain region is provided so as not to become short-circuited with the p-well. The n-type source region is formed so as to become smaller than the n-type drain region.

Abstract: A circuit and method for an improved inverter is provided. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (V.sub.t). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. This design provides fast switching capability for low power battery operated CMOS circuits and systems. The transistor structure offers performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: An oxidation layer 44 for masking is formed on a PNP type transistor formation region 46a together with a field oxidation layer 42 for device separation. The oxidation layer 44 for masking is formed so as to cover an upper part of an active base formation region 52a located between the emitter/collector formation region 50a. The upper part of the active base formation region 52a which is not possible to adjust impurity concentration at processes carried out later is covered with the oxidation layer 44 for masking being formed relatively thick when boron B is implanted into a PMOS type transistor formation region 48a as channel ion. So that, boron is not implanted ionically to the active base formation region 52a. Therefore, it is not necessary to carry out masking process using photo resist layer in prior to boron implantation process.

Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Abstract: An integrated circuit structure for preventing latch-up of an integrated circuit device, such as a dynamic random access memory, that is operated with a negative substrate bias in use of the device. The integrated circuit structure includes a p-type substrate having an n-well region formed therein, with a rectifying junction formed in a lightly doped portion of the n-well region and connected to provide a path to ground for clamping the substrate to ground during power-up conditions. In another embodiment, a rectifying junction formed in a lightly doped portion of the n-well region functions as a diode clamp for a pumped bias voltage for the n-well region.

Abstract: The integrated circuits array with latch up protection includes an active array and a guard array. The active array contains a plurality of integrated circuits devices having operational functions. The guard array abutting an outer peripheral portion of the active array contains a plurality of transistors for protecting the plurality of integrated circuits devices from latch up. In general, the active array can be functional circuits like a memory array or a read only memory (ROM) array. The plurality of transistors in the guard array can be formed simultaneously with transistors in the active array and have same structure with the transistors.

Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V.sub.cc through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

Abstract: An analog switching circuit comprises an insulated-gate field-effect transistor (Q20) having two n-type input-side and outpu-side semiconductor regions (201, 202) and a p-type semiconductor substrate region 203, for controlling conductiveness between an input terminal (IN) and an output terminal (OUT) based on a gate potential. A surge pulse detecting circuit (1020), responsive to an electric potential (Vi) of the input terminal (IN), produces a detection signal of a surge pulse equivalent to a forward bias of a PN junction formed between the semiconductor substrate region (203) and the input-side semiconductor region (201). A substrate potential setting circuit (1010) varies an electric potential of the semiconductor substrate region (203) in response to the electric potential (Vi) of the input terminal (IN) when aby detection signal is produced.

Abstract: A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

Abstract: The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region.

Abstract: A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

Abstract: A semiconductor device includes an N-well arranged in the principal surface of a P-type semiconductor substrate, an N.sup.+ well contact arranged in the principal surface of the N-well, and an N.sup.+ buried region arranged to the bottom of the N-well.

Abstract: A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device.

Abstract: A semiconductor device has a substrate bias generating circuit for generating a substrate bias to be applied to a p-type semiconductor substrate, a CMOS circuit formed on the semiconductor substrate, and a latch-up protection circuit. The latch-up protection circuit has an n-type first region, a highly doped n-type second region, a p-type third region apart from the second region, in the first region and an n-type fourth region surrounding said first region formed apart from the first region on the surface of the substrate. The second region is coupled with a power supply Vcc, the third region is coupled with an input line, the fourth region is coupled with a ground Vss, and the substrate is coupled with the substrate bias generating circuit.

Abstract: Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and carbon for p-type devices in addition to the p-type dopants and implanting a combination of nitrogen and fluorine for n-type devices in addition to the n-type dopants, significantly reduces the diffusion of the n-type and p-type dopants. The co-implantation of the additional impurities may be performed before patterning of the polysilicon layer to yield the gate conductors. The impurities may be implanted first, followed by the n-type or p-type dopants. Additional implantation of the impurities may be performed after the patterning of the polysilicon layer in order to reduce dopant diffusion in the source and drain regions.

Abstract: An integrated circuit includes a plurality of CMOS transistors formed in a monocrystalline substrate. Within the substrate is a plurality of complementary spaced pairs of a p-well region and a n-well region. Between each well region, each of which has a source, gate, and drain, is a self-aligned trench filled with semiconductor material. A method of fabricating a field effect transistor entails a first step of forming a layer of first insulative material over a monocrystalline substrate. Next, a layer of semiconductor material is formed over the first insulative material. A p- or n-well masking layer is formed over the semiconductor layer and patterned to expose a first portion of the underlying semiconductor layer. A first dopant of one polarity is implanted in the region of the substrate aligned with the semiconductor layer first portion, which is then converted into a second insulative material. The masking layer is removed, thereby exposing the remaining portion of the semiconductor layer.

Abstract: Disclosed is a method for manufacturing a BiCMOS in which a complementary MOS transistor and a bipolar transistor are formed on the same substrate, comprising the steps of: providing a semiconductor substrate with impurities of a first conductivity type; forming field oxides for device isolation at the substrate to define a first group active region having two active regions and a second group active region having five active regions in series arrangement; forming a first mask pattern to expose three central active regions of the second group active region; forming a buried layer of a second conductivity type at a first depth from surfaces of the three central active regions using the first mask pattern; forming a second mask pattern to expose either one active region of the first group active region and two active regions at both edge portions of the second group active region; forming first well regions of the second conductivity type in which the impurities of the second conductivity type are distributed t

Abstract: A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.

Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Abstract: A DRAM semiconductor device has: a semiconductor substrate with one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of the semiconductor substrate, the first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of the semiconductor substrate, and one of a depth and the first conductivity type impurity concentration of the local maximum of the second well is larger than that of the first well, and the other is at least equal to that of the first well; a memory cell formed in the first well; and a peripheral circuit for the memory cell formed in the second well. A DRAM semiconductor device is provided whose refresh characteristics are improved without deteriorating other characteristics.

Abstract: Disclosed is a MOSFET with double source and drain regions. Each of the source and drain regions in the MOSFET is implemented by two impurity-implanted regions. The source region has an n+ type region and a p type region which is formed beneath the n+ type region. The drain region has a p type region and an n+ type region which is formed beneath the p type region. Accordingly, the high built-in potential is induced in the source region and then the leakage current may decrease. On the other hand, because a current path is formed from the n+ type region in the source region to the n+ type region in the drain region, the hot carrier effect is reduced.

Abstract: A CMOS semiconductor device comprises a well and a MOSFET adjacent to the well, wherein the distance between the channel region of the MOSFET is larger than the distance between the well and any of the source and drain of the MOSFET. The larger distance between the channel region and the well provides less fluctuation of the threshold voltage of the MOSFET.

Abstract: A CMOS device includes a first MOS transistor of a surface channel type and a second MOS transistor of a buried channel type on a common substrate wherein a doped layer is provided underneath a first channel layer of the first MOS transistor and a second channel layer of the second MOS transistor, such that the first channel layer is provided at a level closer to a principal surface of the substrate as compared with source and drain regions of the first and second MOS transistors.

Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

Abstract: A memory cell having a low storage node resistance and a method of manufacturing the same are provided. A trench type memory cell, in addition to storage node polysilicon, has other conductive material embedded in the storage node. Conductive material may be one of WSi, TiSi, W, Ti, and TiN. The additional conductive material provides a low storage node resistance which facilitates the realization of 256 Mbit memory cells and beyond.

Abstract: A complementary metal-oxide-semiconductor device having a semiconductor region of an n conductivity type connected to a high-potential power supply, in which a p-channel MOSFET is formed, and a semiconductor region of a p conductivity type connected to a low-potential power supply, in which an n-channel MOSFET is formed, characterized in that at least one of the following two states, that is, one state in which a source of said p-channel MOSFET is connected to a lower high-potential power supply having a potential lower than that of said high-potential power supply and another state in which a source of said n-channel MOSFET is connected to a higher low-potential power supply having a potential higher than that of said low-potential power supply is realized.

Abstract: In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an active mode. A ground voltage is applied to back gates of N-channel MOS transistors in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel MOS transistors in an active mode.

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Abstract: A titanium silicide (4) covers surfaces of P.sup.+ -type diffusion region (7) and N.sup.+ -type diffusion region (8) to electrically connect the diffusion regions (7, 8) through the titanium silicide (4), and a surface of the titanium silicide (4) is covered with an insulation film (10). A power supply potential applied to a metal wire (2) is thereby applied to an N.sup.+ -type diffusion region (6), an N well (12) and the N.sup.+ -type diffusion region (8) through a contact hole (3) and further supplied for the P.sup.+ -type diffusion region (7) serving as a source region of PMOS transistor through the titanium silicide (4). That eliminates the need for providing any contact for supplying the diffusion regions 7 and 8 with the power supply potential to attain reduction in layout size, while preventing a latch-up. Thus, the N well-source structure of a semiconductor integrated circuit device including an SRAM with Full CMOS structure eliminates the need for providing a contact on the surfaces of the P.sup.

Abstract: A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

Abstract: A semiconductor device comprises a semiconductor substrate having N- and P-channel regions formed therein; a plurality of first transistors formed in the N-channel region; a first field shield element-isolation structure having a first shield plate electrode and formed in the N-channel region for isolating the first transistors from each other; a plurality of second transistors formed in the P-channel region; and a second field shield element-isolation structure having a second shield plate electrode electrically connected to the first shield plate electrode and formed in the P-channel region for isolating the second transistors from each other; wherein respective values of a threshold voltage V.sub.tN of a parasitic transistor formed in a field region of the N-channel region, a threshold voltage V.sub.tP of a parasitic transistor formed in a field region of the P-channel region and a potential V.sub.sP of the first or second shield plate electrode are determined so as to meet V.sub.tN -V.sub.tP >V.sub.

Abstract: An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.

Abstract: A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0 V. In an active state, potentials that render the voltage between the source and substrate lower than the built-in potential are applied to respective substrates of the P and NMOS transistors. Therefore, the threshold voltage of the transistor is lowered in an active state than in a standby state, and almost no leakage current flows between the source and substrate.

Abstract: A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A semiconductor integrated circuit has a semiconductor substrate on which macrocells are formed. At least one of the macrocells is surrounded by a first diffused region, which may be surrounded by a second diffused region. The first and second diffused regions are connected to power source terminals, respectively. Semiconductor elements included in each macrocell are connected to power source terminals that are independent of the terminals connected to the diffused regions. Alternatively, a voltage is supplied to the diffused regions through power lines that are different from power lines for the semiconductor elements. This arrangement absorbs short-circuit current in CMOS circuitry and/or substrate current produced by the semiconductor elements.

Abstract: An arrangement that prevents triggering of latchup in internal circuits by input/output buffers on an integrated circuit chip provides a space surrounding each active device connected to a bond pad. A ring well surrounds the space and separates the active device from the internal circuits of the chip. The ring well serves as a collector to prevent triggering latchup by the active device of the internal circuits located outside the ring well.

Abstract: In a semi-conductor integrated circuit device, electric charges which relate to latch-up phenomenon generation are absorbed effectively, and thereby generation of the latch-up phenomenon is prevented. Low-concentration impurity diffusion layers of I/O transistor within I/O transistor region are electrically connected to high-concentration impurity diffusion layers with different conductive characteristics each. Furthermore, low-concentration impurity diffusion layers of internal circuit transistors within internal circuit transistor region are electrically connected to high-concentration impurity diffusion layers with different conductive characteristics each, or are brought into directly contact therewith, thus electrically connecting thereto. For this reason, it causes an observed area of the low-concentration impurity diffusion layer of the transistors to enlarge, thus absorbing the electric charges causing the latch-up phenomenon generation.

Abstract: A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well bias voltage (V.sub.BP1) is applied to the first well (N-type) and a second well bias voltage (V.sub.BN1) is applied to the second well (P-type); a second circuit (201; 202) formed in a third well (N-type) and a fourth well (P-type) of the same semiconductor substrate as above, supplied with the first supply voltage (V.sub.ss) and a third supply voltage (V.sub.cc2) higher than the first supply voltage but different from the second supply voltage (V.sub.cc), and activated when a third well bias voltage (V.sub.BP2) is applied to the third well (N-type) and a fourth well bias voltage (V.sub.BN2) is applied to the fourth well (P-type); a first bias circuit (20) supplied with the first and second supply voltages (V.

Abstract: CMOS vertically modulated wells have a structure with a buried implanted layer for lateral isolation (BILLI). This structure includes a field oxide area, a first retrograde well of a first conductivity type, a second retrograde well of a second conductivity type adjacent the first well, and a BILLI layer below the first well and connected to the second well by a vertical portion. This structure has a distribution in depth underneath the field oxide which kills lateral beta while preventing damage near the surface under the field oxide.

Abstract: A composite semiconductor device comprised of a power MOS FET and a low level signal element. The MOS FET includes an n type buried layer embedded between p type substrate and n type epitaxial layer. As conventionally formed due to the pn junctions between the p substrate and the n epitaxial layer, and between the p substrate and the n buried layer, the depletion layers had abrupt transitions therebetween, inviting field concentrations and consequent voltage drops. In order to mitigate the abrupt transitions, one or more n type additional buried regions are provided in and between the substrate and the epitaxial layer and in the adjacency of the buried layer. The additional buried regions are higher in impurity concentration than the epitaxial layer.

Abstract: An N-type well region (NW) is provided on a P-type bulk silicon substrate (PS), and a channel region (PC) is provided inside the N-type well region (NW). The channel region is formed of a semiconductor layer having a polarity opposite to that of a source region (ST) and a drain region (DT). A contact hole (CHC) is provided in a gate oxide film (GO) located below a main portion (MP) close to an end portion (EP) of a gate electrode (GT). With this construction, a semiconductor device in which a body terminal is connected to a gate terminal for fast operation can remove restriction on location for connecting the body terminal and the gate terminal to achieve size-reduction and overcome disadvantages due to restriction on supply voltage.

Abstract: A new method of forming a silicon-on-insulator device having a body node contact is described. Active areas are isolated from one another within a silicon-on-insulator layer. Adjacent active areas are doped with dopants of opposite polarities to form at least one n-channel active area and at least one p-channel active area. Gate electrodes are formed over each active area. The area directly underlying the gate electrode and extending downward to the insulator layer comprises the body node. Lightly doped areas are formed beneath the spacers on the sidewalls of the gate electrodes. First ions are implanted into the active areas not covered by a mask whereby source and drain regions are formed in the at least one n-channel active area and whereby a p-channel body contact region is formed within the at least one p-channel active area wherein the p-channel body contact region contacts the p-channel body node.

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.