Abstract: A novel method and system for fabricating integrated circuit devices is disclosed herein. In one embodiment, the method comprises determining at least one electrical performance characteristic of a plurality of semiconductor devices formed above at least one semiconducting substrate, providing the determined electrical performance characteristics to a controller that determines, based upon the determined electrical characteristics, across-substrate variations in an exposure dose of a stepper exposure process to be performed on at least one subsequently processed substrate, and performing the stepper exposure process comprised of the across-substrate variations in exposure dose on the subsequently processed substrates.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: An input/output protection device of lateral, bipolar type quickly responds to an excess voltage pulse and/or an excess current pulse of, for example, electrostatic discharge. In a region of a first conduction type (a fourth diffusion layer) of a semiconductor substrate, a first diffusion layer of a second conduction type opposite to the first conduction type is fabricated, the layer being connected to an input/output terminal. A second diffusion layer of the second conduction type is fabricated to be connected to electrode wiring at a fixed potential. A third diffusion layer of the second conduction type is manufactured at a bottom of the second diffusion layer and is connected to the second diffusion layer. The first diffusion layer is circularly enclosed with the third diffusion layer.

Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

Abstract: The semiconductor device includes: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.

Abstract: A surface-channel MOS transistor comprising; a gate electrode formed on a semiconductor substrate with a gate dielectric film therebetween and source/drain regions formed in the semiconductor substrate wherein the gate electrode is formed at least a polysilicon layer of a thickness of 100 to 200 nm uniformly doped with an impurity and the source/drain regions contains the same impurity in self-alignment with the gate electrode.

Abstract: A gate electrode of an n-channel IGFET includes a first region composed of at least a first IV group element and a second IV group element which are different from each other, and a second region composed of the first IV group element. Similarly, a gate electrode of a p-channel IGFET includes first and second regions. For example, the first region is made of SiGe while the second region is made of Si. In both of the n-channel and P-channel IGFET, silicide electrodes are formed on the gate electrodes 4N and 4P through silicidation of at least parts of the second regions.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.

Abstract: A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.

Abstract: Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circuits or other devices may include a semiconductor wafer with a substantially uniformly boron-doped bulk region and a reduced boron concentration layer near a surface of the wafer. An electrical circuit element may be provided in the reduced boron concentration layer.

Abstract: A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.

Abstract: A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.

Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

Abstract: A semiconductor device is provided having a high voltage driver IC reducing malfunction or device destruction. A high voltage IC chip includes a trench structure that surrounds each of two semiconductor regions at different electrical potentials. Specifically, a first semiconductor region forms a ground-potential-based circuit, and a high voltage junction terminating structure around a second semiconductor region forms a floating-potential-based circuit. A trench structure is formed after digging a trench by implanting a high concentration p+ region on a trench wall, or alternatively, by filling the trench with a p+ doped polysilicon or with a dielectric.

Abstract: A circuit structure integrated in a semiconductor substrate comprises at least one pair of transistors each being formed each in a respective active area region and having a source region and a drain region, as well as a channel region intervening between the source and drain regions and being overlaid by a gate region. The gate regions are connected electrically together by an overlying conductive layer and respective contacts. The contacts between the gate regions and the conductive layer are formed above the active areas.

Abstract: In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share the common gate length direction, and are arranged in the same pitch. The first gate electrodes and the second gate electrodes are all made to extend, in the gate width direction, beyond the longest active region width. With such a configuration, it is possible to provide a semiconductor device having a pattern structure that will not cause performance degradation of transistors when designing a semiconductor integrated circuit within a semiconductor device.

Abstract: An integrated CMOS semiconductor circuit comprises: an internal circuit composed of CMOS transistors including P3- and N-channel transistors each having a gate electrode and source/drain regions formed on a semiconductor substrate, the internal circuit functioning in at least two states including an active state in which data is input and output, and a standby state in which a state of the internal circuit is maintained; an external circuit composed of any electrical element and provided with a power source; and a switch portion which is enable to apply, in the standby state in the internal circuit, a reverse bias between the source and the substrate of either one of the P- and N-channel transistors of the internal circuit by the power source of the external circuit.

Abstract: The present invention creates a useful BJT by increasing the gain associated with the parasitic BJT on an SOI or bulk type MOSFET. This is done by masking those manufacturing steps that minimize the BJT's beta value, by intentionally increasing the beta value of the BJT, and by driving the base of the BJT with the circuit. Once the gain is increased sufficiently, the BJT may be used productively in the circuit. Because the physical structure of the BJT is already part of the silicon water, its productive use does not require additional space.

Abstract: An electrostatic discharge (ESD) protection device. The ESD protection device includes a first parasitic bipolar transistor, a second parasitic bipolar transistor, a third parasitic bipolar transistor and a fourth parasitic bipolar transistor formed over a substrate. A first longitudinal doped region is formed between the first parasitic bipolar transistor and the second parasitic bipolar transistor. Similarly, a second longitudinal doped region is formed between the third parasitic bipolar transistor and the fourth parasitic bipolar transistor. A guard ring circumscribes the substrate. An isolation region is formed inside the guard ring. The guard ring and the first/second longitudinal doped region are all connected to a ground terminal.

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.

Abstract: Provided is a DAD that improves resistance to latch-up and stabilizes breakdown voltage characteristic. Specifically, a first gate electrode (10) and a second drain electrode (13) are linear electrodes having a length not exceeding the length of a source electrode (9). An isolation region (20) is disposed on both end portions of these electrodes. The region surrounded by two isolation regions (20) and the source electrode (9) becomes a P channel MOS region (PR) where a P channel MOS transistor is to be formed. The isolation region (20) has a multi-trench structure that a plurality of trenches (21) are provided in a P type impurity region disposed so as to be rectangle as viewed in plan configuration. Each trench (21) is filled with a conductor such as polysilicon, and the filled conductor is disposed so that it makes no electrical contact with any specific part.

Abstract: A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate.

Abstract: An insulated gate transistor comprising a first semiconductor region, a second semiconductor region includes plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode, and a second main electrode, wherein a metallic wiring layer is provided on the first main surface plane via an insulating layer, plural regions insulated from the first main electrode are provided through said first main electrode, and the metallic wiring layer is connected electrically to the control electrode through the insulating layer via the region insulated from the main electrode.

Abstract: A P well region formed on a buried N well region and a n+ active region that are connected each other through a lead wire, serve as one terminal T1, and a gate electrode and a buried N well region that are connected each other through a leading N well region and a lead wire, serve as the other terminal T2. Thereby, the voltage dependence of capacitance C1 formed between the gate electrode and the n+ active region is canceled out with the voltage dependence of capacitance C2 formed between the P well region and the buried N well region.

Abstract: Provided is a substrate of a semiconductor integrated circuit which can easily manufacture an integrated circuit having a soft error resistance, a latch up resistance and an ESD resistance increased. A thickness of a semiconductor surface layer having a lower impurity concentration than that of each of substrate single crystals 51 and 55 is varied according to a resistance which should be possessed by each section such as a memory cell section 5, a logic section 6, an input-output section 8 or the like for a region where each section is to be formed.

Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.

Abstract: In a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and connected to the well, so as to fix a voltage at the well.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.

Abstract: A shallow P well and a deep P well are formed in the surface of a P type semiconductor substrate so as to partially overlap each other and these wells are surrounded by an N well, a deep bottom N type well and a connection N well. The impurity concentration of this overlapping region is higher than the impurity concentration of the P well or of the deep P well and a P+ type region is formed in the surface of the overlapping region. A potential (VBB) different from the ground potential is applied to the P+ type region. The P+ type region is formed in overlapping region and, thereby, the layout of the semiconductor device can be scaled down.

Abstract: A configuration for voltage buffering in dynamic memories based on CMOS technology uses the capacitance of a well structure for buffering the amplified word line voltage or the negative word line reverse voltage.

Abstract: A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

Abstract: A semiconductor memory device has a semiconductor substrate, a peripheral circuit region and a memory cell region on the principal surface of the semiconductor substrate. The semiconductor memory device has a first well formed in the peripheral circuit region, a second well of first conductivity type and a third well of second conductivity type formed in the memory cell region having substantially the same depth, and a device element isolator formed in the memory cell region for isolating a device element formed in the second well from a device element formed in the third well. The second and third wells extend to an area under the device element isolator. The second and third wells extend to a level under the device element isolator. The second and third wells may include a first layer having a depth shallower than the first well, and a second layer having substantially the same depth as the first well.

Abstract: The present invention proposes an ESD protection circuit with low input capacitance, suitable for an I/O pad. The ESD protection circuit includes a plurality of diodes and a power-rail ESD clamp circuit between power lines. The diodes are stacked and coupled between a first power line and the I/O pad. The ESD protection circuit between power lines is coupled between the first power line and a second power line. During normal operation, the diodes are reverse-biased and the ESD protection circuit between power lines is turned off. When an ESD event between the power line and the I/O pad occurs, the diodes are forward-biased, and the ESD protection circuit between power lines is turned on to conduct ESD current. The equivalent input capacitance of the ESD protection circuit of the present invention is very small, making it particularly suitable for the I/O port of high-frequency or high-speed IC.

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

Abstract: An improved semiconductor device, such as a MOSFET with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate . The device has thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The semiconductor device has very shallow source drain extensions which result in a reduced short channel effect.

Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

Abstract: An RF circuit may be formed over a triple well that creates two reverse biased junctions. By adjusting the bias across the junctions, the capacitance across the junctions can be reduced, reducing the capacitive coupling from the RF circuits to the substrate, improving the self-resonance frequency of inductors and reducing the coupling of unwanted signals and noise from the underlying substrate to the active circuits and passive components such as the capacitors and inductors. As a result, radio frequency devices, such as radios, cellular telephones and transceivers such as Bluetooth transceivers, logic devices and Flash and SRAM memory devices may all be formed in the same integrated circuit die using CMOS fabrication processes.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.

Abstract: A semiconductor device includes two latch circuits, each of which latches a corresponding one of complementary data outputs supplied from an amplifier circuit, and includes only one intervening gate from an input thereof to an output thereof, the latch circuits being reset by an activation signal that activates the amplifier circuit.

Abstract: A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N− conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12).

Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.