Abstract: A MOS transistor is formed in a first low-doped P-type retion coating a second more highly doped P-type region. The transistor comprises an N-type drain region, an N-type source region, and a region contacting the for region. The drain, cource and contacting regions are formed at the surface of the first region. The source and contacting regions are interconnected. An N-type highly doped region extends from the drain region through the first low-doped P-type region to the second more highly doped P-type region.

Abstract: A CMOS output circuit including a pMOS transistor and an nMOS transistor connected in series between a power supply voltage and a ground voltage, is formed with a resistive component for reducing occurrence of latch-up. The resistive component is arranged at least one of the sources of the pMOS and nMOS transistors so as to be connected in series with a parasitic bipolar transistor formed between the power supply voltage and the ground voltage through its emitter. The resistive component limits the collector current of the parasitic bipolar transistor at a time that a triggering voltage is applied to an output terminal of the output circuit, so that the parasitic bipolar transistor does not turn on readily, thereby resulting in reduced possibility of occurrence of latch-up.

Abstract: The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, to the source electrode, and across the drain electrode and the semiconductor substrate to expand the depletion layer from the junction face of a semiconductor substrate and a well formed thereon, the leading edge of the depletion layer does not reach a low-concentration drain diffusion region formed on the well. When a potential is applied to the drain electrode, to the semiconductor substrate, and across the source electrode and the gate electrode to expand a depletion layer from the junction face of the low-concentration drain diffusion region and the well, and a depletion layer from the junction face of semiconductor substrate and the well, the depletion layers are connected with each other.

Abstract: To improve resistance to latch-up of complementary MOS semiconductor device, a high concentration buried layer (16) of same conduction type as a semiconductor substrate (1) and of concentration higher than the silicon semiconductor substrate is formed under a well region (5) of first conduction type in which MOS transistor of second conduction type is formed and a well region (3) of second conduction type in which MOS transistor of first conduction type is formed. The high concentration buried layer (16) reduces parasitic resistance of the semiconductor substrate (1), suppresses transfer of carrier due to surge or the like applied from outside and inside, and inhibits the parasitic transistors (12)(13) from turning on.

Abstract: In a semiconductor device, a charge transfer device, a bipolar transistor, and a MOSFET are formed on a single chip, and the peripheral portion of the charge transfer device is surrounded by an N.sup.+ -type region. Since the charge transfer device block is surrounded by the N.sup.+ -type region and the N.sup.+ -type buried layer, leaked charge of clocks from the charge transfer device is absorbed by the N.sup.+ -type region and the N.sup.+ -type buried layer.

Abstract: A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.

Abstract: A semiconductor layer made of an epitaxial growing layer (16) is formed on the surface of a p.sup.- -type silicon semiconductor substrate (11), first impurity regions are formed by p.sup.+ -type buried regions (171, 172) and a p-type impurity regions (221, 222) throughout the semiconductor layer from its surface to the semiconductor substrate so as to divide said semiconductor layer into side element regions (161, 162) and a central island region (163). An anode layer obtained by alternately arranging n.sup.+ -type impurity regions (251 to 253) and p.sup.+ -type impurity regions (231, 232) is formed in surface regions of the pair of impurity regions, and cathode regions made of p-type impurity regions (231, 232) are formed in the element regions of the semiconductor layer. Gate electrodes are formed to be opposite to each other through a gate insulating film in p-n junction portions constituted by the n.sup.+ -type impurity regions (251, 252) the p-type impurity regions (221, 222), and an n.sup.