Abstract: A semiconductor device including a semiconductor substrate having thereon an element region having a surface, an element separating insulating film having an upper surface adjacent to opposing lateral sides of the element region, a silicon epitaxial layer having an upper surface formed on the surface of the element region, a polysilicon layer having an upper surface formed on the element separating film and connected to the silicon epitaxial layer, a gate insulating film and a gate electrode formed on the silicon epitaxial layer, and impurity doped source and drain regions formed in the silicon epitaxial layer. Furthermore, the upper surface of the silicon epitaxial layer is higher than or at the same level as the upper surface of the polysilicon layer. This is done by forming the polysilicon layer on a recessed portion of the element separating insulating film adjacent to the element region.

Abstract: A method if provided for forming a diamond etch stop layer across a transistor to protect the source and drain junctions and the gate conductor of the transistor from being etched. The diamond may be CVD deposited from a hydrocarbon-bearing gas across the transistor. An interlevel dielectric comprising oxide is formed across the diamond etch stop layer. Contact openings may be etched through the oxide interlevel dielectric to the source and drain junctions and the gate conductor using a fluorine-bearing plasma. Advantageously, a high etch rate selectivity of oxide to diamond may be achieved using the fluorine-bearing plasma. As such, the plasma etch may be terminated well before significant portions of the diamond can be removed. Ti atoms may be implanted into regions of the diamond exposed by the contact openings and subsequently heated to render those regions of the diamond conductive.

Abstract: A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction in a single crystal substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with all of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and more conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.

Abstract: A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.

Abstract: A method of forming a contact between a conductor and a substrate region in a MOSFET device is provided starting with forming a semiconductor substrate with a silicon oxide layer formed on the surface thereof. Then form a stack of a conductor material upon the surface of the silicon oxide layer and form a first dielectric layer upon the conductor material. Pattern the conductor stack into conductors. Form a butted contact pattern in the first dielectric layer by removal of the dielectric layer in at least one butted contact region. Form doped regions in the substrate self-aligned with the conductors. Form an etch stop layer over the device. Form a second dielectric layer over the device and pattern the second dielectric layer with contact openings therethrough down to the substrate and to the butted contact region. Employ the etch stop layer when patterning the second dielectric layer. Remove exposed portions of the etch stop layer subsequent to patterning the second dielectric layer.

Abstract: A source connection structure for a lateral RF MOS device is disclosed. The connection structure utilizes a conductive plug to connect a source area and a body area of the device with a backside. The usage of a conductive plug eliminates at least one doping area used for connectivity purposes. Therefore, the density of RF MOS devices per unit area of the chip is increased.

Abstract: A field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in place, etching the

Abstract: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source.cndot.drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source.cndot.drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.

Abstract: Thin film transistors include a silicide layer between a doped amorphous silicon layer and source/drain electrodes. The source/drain electrodes include a first non-silicidable layer and a second non-oxidizing layer. In order to form the silicide layer, a silicidable metal layer is deposited on the doped amorphous silicon layer, reacted to form a silicide, and the unsilicided portion of the metal layer is removed. High performance thin film transistors are thereby provided.

Abstract: First and second gate electrodes are formed spaced from each other on a semiconductor substrate. A pair of impurity diffusion layers are provided on both sides of the first gate electrode at the surface of the semiconductor substrate. The first gate electrode includes a first lower conductive film, a first protective conductive film provided on the first lower conductive film, and a first upper conductive film provided on the first protective conductive film. The second gate electrode includes a second lower conductive film, a second protective conductive film provided on the second lower conductive film, and a second upper conductive film provided on the second protective conductive film. The second upper conductive film extends to be in contact with one of the pair of impurity diffusion layers.

Abstract: This invention provides contact programmable ROM which shortens TAT.The manufacturing process comprises two steps of: (a) a step in which a plurality of memory cells having gate region 14 and source/drain regions 15A and 15B is formed on a semiconductor substrate, the first interlayer insulating layer 20 is formed on the whole surface, the first opening 21 is formed on the first interlayer insulating layer 20 above one source/drain region 15A of each memory cell, metal interconnect material 22 is filled in the first opening 21 to from a contact hole, and the second interlayer insulating layer 23 is formed over the metal interconnect material 22 and first interlayer insulating layer 20, and (b) a step in which the second opening 24 is formed on the second interlayer insulating layer 23 above the contact hole of specified memory cells, and interconnecting layer 25 is connected electrically to the contact hole is formed over the second interlayer insulating layer 23.

Abstract: MOSFET devices, using a local interconnect structure, and silicon nitride capped, self-aligned contact openings, have been developed. The process features the creation of self-aligned contact openings, exposing specific source and drain regions. After deposition of a composite insulator layer, a second opening is formed in the composite insulator layer, again exposing various elements including the previously opened, specific source and drain regions. The local tungsten interconnect structure fills the second opening, contacts, as well as interconnects, the specific source and drain regions.

Abstract: A CMOS integrated circuit structure with planarized self-aligned transistors and local planarization in the vicinity of the transistors so as to allow an interconnect, with a planar upper surface, which is free of bridging, has good continuity over the planarized topography and is compatible with self-alignment schemes, hence conserving chip real estate. The structure is compatible with planarization using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, a "landing pad" is formed on the substrate at the buried contact and polyiso contact locations so as to allow more effective etching at the exact location of the buried contact and polyiso contact. Then the integrated circuit structure is locally planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface.

Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in the form of a substitutional solid solution.

Abstract: A semiconductor device in which mutual diffusion of doped impurities occurring through an upper silicide electrode layer is prevented. A silicide electrode layer is doped with both the same degree of p-type impurities as the concentration of p-type impurities of the lower gate electrode layer and the same degree of n-type impurities as the concentration of n-type impurities. As a result, the concentration of doped impurities of the gate electrode layer is balanced at the two sides of the interface of the pMOS side and nMOS side. Therefore, heat diffusion caused by subsequent heat treatment is prevented and the problem of mutual diffusion can be solved. The present invention is also suitable for the SALICIDE process.

Abstract: A lateral diffused MOS transistor formed in a doped epitaxial semiconductor layer on a doped semiconductor substrate includes a source contact to the substrate which comprises a trench in the epitaxial layer filled with conductive material such as doped polysilicon, a refractory metal, or a refractory silicide. By providing a plug as part of the source contact, lateral diffusion of the source contact is reduced, thereby reducing overall pitch of the transistor cell. Further, source contact resistance is reduced by the presence of the conductive plug, and the reduced thermal budget requirements in forming the source contact reduces up diffusion from the doped substrate, thereby reducing parasitic capacitance.

Abstract: A field effect transistor includes, a silicon substrate having impurity doping of a first conductivity type; source and drain diffusion regions of a second conductivity type within the silicon substrate, the source region and the drain region being spaced from one another to define a channel region therebetween within the silicon substrate; a gate relative to the silicon substrate operatively adjacent the channel region; and respective ohmic electrical contacts to the source region and the drain region, the electrical contact to the source region comprising a substrate leaking junction, the electrical connection to the drain region not comprising a substrate leaking junction.

Abstract: According to this invention, a metal interconnection for the common source diffusion layer of memory cell transistors can be easily formed. An insulating interlayer which covers memory cell transistors is formed on a substrate. A contact hole connected to each drain diffusion layer and a slit-like opening for forming the metal interconnection for the common source diffusion layer are formed on the insulating interlayer. Each contact hole and the slit-like opening are embedded with a refractory metal. The refractory metal in each contact hole is connected to a bit line on the insulating interlayer. In order to connect the refractory metal film in the slit-like opening to only an upper source line, the refractory metal in the slit-like opening crosses under the bit line so as to have an intermediate level of the insulating interlayer in the direction of thickness except for a contact portion with the source line.

Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.

Abstract: A method for creating manufacturable polycide contacts, for use in advanced semiconductor designs using images as small as 0.35 uM, has been developed. An amorphous silicon film, is used as an underlay, to assist in the growth of an overlying tungsten silicide layer. The tungsten silicide deposition is performed using tungsten hexafluoride and silane, and in conjunction with the amorphous silicon underlay, results excellent step coverage in the narrow contact hole. A nitrogen anneal, using high flow rates, optimizes the adhesion characteristics of the tungsten polycide structure.

Abstract: A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor.

Abstract: A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

Abstract: A semiconductor device includes a connection pad layer for securing a contact margin which is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. A device fabricated according to this structure yields improved punch-through and junction depth characteristics.

Abstract: A process of production of a semiconductor device comprising the steps of forming a first interlayer insulating film for covering a transistor formed on a substrate; forming a contact hole which will be connected to the transistor and a contact hole for local connection which will connect locations near each other simultaneously; and filling the contact holes with a conductor to form conductive plugs.

Abstract: A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a silicon substrate, and a contact hole is formed in an inter-level insulating layer of silicon oxide exposing a part of the upper silicon nitride layer and a part of the titanium silicide layer into the contact hole; while the inter-level insulating layer is being selectively etched so as to form the contact hole, the upper silicon nitride layer serves as an etching stopper, and the contact hole never reaches the silicon substrate beneath the buried isolating structure.

Abstract: A gate electrode is made up of a polycrystalline silicon film containing phosphorous as a dopant for determining its conductivity type, a titanium silicide film of the C54 structure, and a tungsten silicide film all of which films are laid one on another in said order.

Abstract: An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface region improves silicidation characteristics.

Abstract: Through exposure of the top surface of a tungsten film to plasma of a gas including nitrogen at a temperature of 550.degree. C. or less, a tungsten nitride layer having a structure in which nitrogen atoms and tungsten atoms are bonded is formed in an area in the vicinity of the surface of the tungsten film. Then, an aluminum alloy film is deposited on the tungsten film, thereby forming a metallic interconnection. Since the nitrogen atoms and the tungsten atoms are bonded in the tungsten nitride layer formed by such plasma nitridation, the tungsten nitric layer not only has a good barrier function to prevent the diffusion of other metal atoms but also can be formed in a small thickness. Accordingly, formation of an alloy layer with a high resistance otherwise caused due to counter diffusion during an annealing process and a junction leakage can be avoided.

Abstract: Deep submicran mosfets with defect enhanced CoSi2 formation and improved silicided junctions. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.

Abstract: A novel compound PVD target material, suitable for use in the fabrication of cobalt silicide layers on semiconductor devices is disclosed. The compound material is formed by blending an amount of SiO.sub.z with an amount of CoSi.sub.x to form a blended compound material CoSi.sub.x O.sub.y and then compressing and shaping said blended compound material in a hot powder press into an appropriate shape for use in a PVD sputtering chamber. A polysilicon MOSFET gate stack structure and a source/drain salicide structure incorporating the CoSi.sub.X O.sub.y, compound material are described. The addition of a small amount of oxide to the cobalt silicide, when sputter deposited, results in an as-deposited film of CoSi.sub.x O.sub.y having smaller grain size and significantly enhanced thermal stability over conventional CoSi.sub.x, and other characteristics desirable in the fabrication of salicide MOSFET structures.

Abstract: Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion.

Abstract: A contact for a semiconductor device is provided by depositing a layer of palladium on a silicon substrate, causing the palladium to react with the substrate for forming palladium silicide, removing unreacted palladium from the substrate, forming doped silicon on the palladium silicide and substrate, causing the silicon to be transported through the palladium silicide for recrystallizing on the substrate for forming epitaxially recrystallized silicon regions on the substrate and lifting the palladium silicide above the epitaxially recrystallized silicon regions for forming a silicided contact therefor, and removing the doped silicon from the substrate.

Abstract: In a semiconductor device in which a source/drain and a wiring layer are connected to each other through an associated buried conductive layer on an upper portion of a gate electrode is made small to manufacture a highly reliable and fine MOS transistor. After a silicon oxide film has been formed on a first polycrystalline film to be aligned with a width of a gate electrode, a second polycrystalline silicon film formed on the whole surface of a substrate is selectively etched away so as to be left only on both side faces of a pattern of the silicon oxide film. Thereafter, the first polycrystalline silicon film is selectively etched away with both the silicon oxide film and the second polycrystalline silicon film as an etching mask so that the first polycrystalline film is separated with a width which is smaller than that of the gate electrode by a width of a pattern of the second polycrystalline silicon film.

Abstract: A semiconductor device includes a gate insulating film on a semiconductor region of a first conductive type. There is provided on the gate insulating film a gate electrode having a channel length under a design rule of 350 nm or below. The gate electrode includes a first conductive film and a first silicide film formed on the first conductive film and a contact length between the first conductive film and the first silicide film in a channel length direction is longer than the channel length. Source and drain regions each including an impurity layer of a second conductive type formed on the surface of the semiconductor region and a second silicide film formed on the impurity layer. An insulating film spacer structure is provided to contact with side surfaces of the first conductive film of the gate electrode and to have a top surface thereof higher than a top surface of the gate electrode.

Abstract: A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors.

Abstract: A polysilicon electrode is formed in an active area surrounded by an isolation on a silicon substrate with a gate oxide film sandwiched therebetween, a polysilicon wire is formed on the isolation, and a source/drain region is formed on both sides of the polysilicon electrode. On the both sides of a polysilicon film constituting the electrode and the wire are formed side walls having a height that is 4/5 or less of the height of the polysilicon film. Furthermore, the polysilicon film is provided with a silicide layer in contact with the top surface and portions of the side surfaces of the polysilicon film projecting from the side walls, and another silicide layer is formed in contact with the source/drain region. Since the sectional area of the silicide layer is increased, the resistance value can be suppressed even when the dimension of the polysilicon film is minimized. Thus, the invention provides a semiconductor device including an FET having a low resistance value applicable to a refined pattern.

Abstract: An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

Abstract: The present invention relates to a semiconductor device having complementary field effect transistors and a method for manufacturing the same. The object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which is decreased the silicide formation area for connecting a p-type impurity region and an n-type impurity region in the dual gate structure. It comprises steps of covering the silicide formation area of a semiconductor layer with an oxidation resisting sidewall formed in a self-aligned fashion, ion-implanting p-type and n-type impurities with the oxidation resisting sidewall as a mask, patterning the semiconductor layer to form a dual gate pattern, oxidizing a surface of the dual gate pattern with the oxidation resisting sidewall as a mask, selectively removing the oxidation resisting sidewall, and followed by making silicide at its surface exposed by the removal of the oxidation resisting sidewall.

Abstract: A first contact hole and a second contact hole are formed in an insulating film on the surface of a substrate, and thereafter a blanket tungsten (W) layer is deposited on the substrate surface, with or without a barrier metal layer being interposed therebetween. The first contact hole has a small size a so that the W layer can fully bury the first contact hole, whereas the second contact hole has a large size b over a size c where a<c<b so that a desired wiring layer coverage ratio is attained. The deposited W layer is etched back while leaving the W layer in the first contact hole and a tapered W layer in the second contact hole. A wiring layer such as Al alloy is deposited on the substrate surface. The unnecessary wiring layer and barrier metal layer are patterned to form a wiring pattern. Wiring layers having a good burying state and a good coverage state can be obtained. A yield of manufacturing wiring layers can be improved.

Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate at which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.

Abstract: Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described. Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.

Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.

Abstract: A transistor element is formed on the surface of a silicon substrate. A tunnel is formed in the silicon substrate at a position right under the transistor element. A contact hole is formed to extend from the surface of the silicon substrate to the contact hole. Silicon oxide films are respectively formed on the inner surfaces of the tunnel and the contact hole. A wiring layer is buried in the tunnel and the contact hole. The wiring layer is connected to a diffusion layer of the transistor element.

Abstract: (MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught.

Abstract: After formation a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate, and then the Ti layer is silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.