Abstract: In a trench capacitor type semiconductor memory device including a semiconductor substrate having a trench and first and second impurity diffusion source/drain regions, a capacitor electrode buried in the trench, and a substrate-side capacitor electrode and a capacitor insulating layer within the semiconductor substrate and adjacent to a lower portion of the capacitor electrode, a buried insulating layer is formed between the semiconductor substrate and an upper portion of the capacitor electrode. The buried insulating layer is thicker than the capacitor insulating layer. However the buried insulating layer on a surface of the second impurity diffusion source/drain region is thin, or in direct contact with the capacitor electrode. A silicide layer is formed on the second impurity diffusion source/drain region and the capacitor electrode.

Abstract: This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate conductor layer and a hard silicon oxide mask layer and define gate conductors. Form lightly doped source/drain regions, form spacers and source/drain regions in the well. Form a first inter-conductor dielectric layer on the cell. Define a self-aligned contact region in the cell above source/drain regions. Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region. Form a second inter-conductor dielectric layer on the cell, a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.

Abstract: A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased hardness in comparison to conventional etch stop layers, such as plasma enhanced chemical vapor deposition (PECVD) SiON etch stop layers. A PECVD process is used to deposit silicon carbide (SiC). The increased hardness of the SiC etch stop layer is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

Abstract: A manufacturing process OF a thin film transistor is provided, in which occurrence of a dry spot and occurrence of an etch residue of an ohmic contact layer (n+ a-Si:H film) due to the dry spot are prevented in photoengraving process for patterning a semiconductor layer and the ohmic contact layer into an island, without any further treatment by any other apparatus. After forming the a-Si:H film 4a which forms the semiconductor layer of the TFT and the n+ a-Si:H film 5a which forms the ohmic contact layer, a N2 gas plasma discharge is continuously performed using the same plasma CVD apparatus, thereby forming a very thin silicon nitride film 6 having a hydrophilic property on a surface layer of the n+ a-Si:H film 5a.

Abstract: A main electrode (14) is connected to an n-type semiconductor layer (7) selectively formed on a major surface of a silicon substrate. A silicide layer (15) is interposed between the main electrode (14) and the semiconductor layer (7). The silicide layer (15) is heat-treated at 600° C. to 850° C. for at least 30 minutes, to have an epitaxial layer selectively epitaxially growing in a specific direction such as the <110> direction toward the semiconductor layer (7). Therefore, irregularities are formed on the interface between the silicide layer (15) and the semiconductor layer (7). The interface resistivity between the silicide layer (15) and the semiconductor layer (7) is low due to the presence of the epitaxial layer, and besides the contact area of the interface is large due to the irregularities of the interface. Consequently, the contact resistance between the main electrode (14) and the semiconductor layer (7) is effectively reduced.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film on a semiconductor layer, forming a gate electrode on the insulating film, pattering the first insulating film into a second insulating film so that a portion of the semiconductor layer is exposed while the second insulating film has extensions which extend beyond the side edges of the gate electrode, and performing ion introduction for forming impurity regions using the gate electrode and extensions of the gate insulating film as a mask. The condition of the ion introduction is varied in order to control the regions of the semiconductor layer to be added with the impurity and the concentration of the impurity therein.

Abstract: A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.

Abstract: A MOSFET device fabricated by a method that reduces, the risk of gate to source and drain bridging, has been developed. The process features fabricating a polysilicon structure, which is wider at the top than at the bottom, with a source and drain region, self-aligned to the narrower, underlying polysilicon layer. Subsequent metallization results in metal coverage, only on the surfaces of the wider polysilicon layer. An anneal cycle then converts only the wider polysilicon feature to a metal silicide, resulting in a polycide gate structure, comprised of a wider, overhanging metal silicide layer, on a narrower, underlying polysiliocn layer.

Abstract: A semiconductor device includes a pair of second semiconductor regions (5) selectively formed in predetermined spaced apart relation in a first semiconductor region (3), and a silicide film (8) formed in an upper main surface of the first semiconductor region (3) between the pair of second semiconductor regions (5). The silicide film (8) is formed to establish an electric connection between side surfaces of the second semiconductor regions (5) at their respective edges opposed to each other. A source electrode (11) is formed on an upper surface of the silicide film (8). The semiconductor device has an increased safe operating area without the increase in manufacturing costs. A method of manufacturing the semiconductor device is also provided.

Abstract: A semiconductor device having a trench type gate and a fabrication method therefor is provided. The semiconductor device includes a trench formed in a semiconductor substrate and a gate insulating layer formed on the inner walls of the trench. A gate fills the trench and is insulated from the semiconductor substrate by the gate insulating layer. A barrier layer is formed between the gate insulating layer and the gate for preventing migration of impurities from the gate to the gate insulating layer.

Abstract: A MOSFET device with buried contact structure on a semiconductor substrate has the following major elements with their relative locations. A gate insulator is on a portion of the substrate and a gate electrode is on the gate insulator. A gate sidewall structure is located on sidewalls of the gate electrode. Inside the substrate, a lightly doped source/drain region is under the gate sidewall structure, and a doped source/drain region is abutting the lightly doped source/drain region and located aside from a region under the gate sidewall structure. In addition, a doped buried contact region is also in the substrate next to the doped source/drain region. On the substrate, a silicon connection is located on a portion of the doped buried contact region, and a shielding block is on the doped buried contact region covering only a region uncovered by the silicon connection.

Abstract: A TFT structure includes a variably doped contact layer system in order to reduce leakage current characteristics and increase mobility of the TFT. Such TFTs may be utilized in, for example, X-ray imagers or liquid crystal displays. In certain embodiments, the contact layer system is lightly doped adjacent a semiconductor or channel layer, and is more heavily doped adjacent the source/drain electrodes. The variation in doping density of the contact layer system may be performed in a step-like manner, gradually, continuously, or in any other suitable manner. In certain embodiments, the contact layer system may include a single layer which is deposited over an intrinsic semiconductor layer, with the amount of dopant gas being used during the deposition process being adjusted through the deposition of the single layer so as to cause the doping density to vary (increase or decrease) throughout the thickness of the system/layer.

Abstract: In a MISFET incorporating a silicide compound made of metal having a high melting point and formed on an impurity diffusion layer for the drain and source, a MISFET disclosed herein comprises an impurity diffusion layer for the drain and source, a gate insulating film, a gate electrode, a side-wall insulating film formed on the side wall of the gate electrode, an interlayer insulating film having an opened portion including a side-portion removed region obtained by removing a portion of the side portion of the side-wall insulating film on an impurity diffusion layer for the drain and source, a silicide compound layer formed on the impurity diffusion layer for the drain and source, the silicide compound layer being formed on the bottom surface of the opening of the interlayer insulating film corresponding to the side-portion removed region, and a conductor formed in the opening and made contact with the silicide compound layer.

Abstract: An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

Abstract: An ohmic electrode structure includes an n-InxGa1−xAs layer where 0<x≦1; a Pt or Pd layer provided on the n-InxGa1−xAs layer; and at least one metal layer provided on the Pt or Pd layer. A semiconductor device includes a substrate; a first semiconductor layer having a p-type conductivity provided on the substrate; a second semiconductor layer having an n-type conductivity provided on the substrate; an ohmic contact layer provided on the first semiconductor layer; a barrier layer provided on the second semiconductor layer; a first electrode provided on the ohmic contact layer; and a second electrode provided on the barrier layer. The ohmic contact layer and the barrier layer are each formed of a material selected from the group consisting of Pt and Pd.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: Electromigration in the source and drain conductors of a semiconductor device is reduced by increasing the cross-sectional areas of these conductors in accordance with an increase in a magnitude of current, thereby enabling the semiconductor device to operate at high temperatures.

Abstract: A semiconductor thin film structure includes source/drain regions and a channel region positioned between the source/drain regions. The semiconductor thin film structure extends directly on and in contact with a surface of an insulation region. At least one of the source/drain regions includes a semiconductor material region extending directly over and in contact with the surface of the insulation region and a refractory metal silicide layer extending directly on and in contact with the semiconductor material region. The refractory metal silicide layer has a first thickness which is equal to or thicker than a half of a second thickness of the channel region, thereby suppressing any substantive kink effect.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expense of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in

Abstract: A semiconductor device is formed in a self-light-emitting apparatus having a substrate and a plurality of self-light-emitting elements formed on the substrate. The semiconductor device is used to drive one of the self-light-emitting elements. The semiconductor device includes an active layer of semiconductor material, in which a source region and a drain region are formed. A source electrode has a multi-layered structure including an upper side layer of titanium nitride and a lower side layer of a high melting point metal having low resistance. The source electrode is electrically coupled to the source region. A drain electrode has a multi-layered structure including an upper side layer of titanium nitride and a lower side layer of a high melting point metal having low resistance. The drain electrode is electrically coupled to the drain region. An insulation layer is formed on the active layer. A gate electrode is formed on the insulation layer.

Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.

Abstract: A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer surrounds the film. A grid structure with insulated flanks is formed above the channel. Source and drain contacts are formed on the portion of the silicon film between the field insulation layer and the grid structure. The source and drain contacts are self-aligned on the grid structure and the field insulation layer is placed directly adjacent to the grid structure.

Abstract: An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400.degree. C. and above. Heat treatment at a high temperature (400-700.degree. C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 .mu.m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.

Abstract: A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.

Abstract: A buried contact structure on a semiconductor substrate in the present invention is as follows. A gate insulator is on a portion of the substrate and a gate electrode is located over the gate insulator. A gate sidewall structure is on the sidewall of the gate electrode. A lightly doped junction region in the substrate is under the gate sidewall structure. A doped junction region is in the substrate abutting the lightly doped junction region and is located aside from the gate insulator. A doped buried contact region is in the substrate next to the doped junction region. An interconnect is located over a first portion of the doped buried contact region.The buried contact structure can further include a shielding layer over a second portion of the doped buried contact region. For forming more connections, the buried contact structure can further have a dielectric layer over the interconnect, the substrate, the gate sidewall structure, and the gate electrode.

Abstract: At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

Abstract: Integrated circuitry and a method of forming a contact landing pad are described. The method includes, in one embodiment, providing a substrate having a plurality of components which are disposed in spaced relation to one another; forming a silicon plug spanning between two adjacent components; forming a refractory metal layer over the silicon plug and at least one of the components; reacting the silicon plug and the refractory metal layer to form a silicide layer on the silicon plug; and after forming the silicide layer removing unreacted refractory metal layer material from the substrate.

Abstract: A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.

Abstract: An integrated circuit fabrication process is provided for implanting silicon into select areas of a refractory metal to reduce the consumption of silicon-based junctions underlying those select areas during salicide formation. The refractory metal is subjected to a heat cycle to form salicide upon the junctions and polycide upon the upper surface of a gate conductor positioned between the junctions. In response to being heated, the metal atoms readily react with implanted silicon atoms positioned proximate the metal atoms to form salicide. Once a metal atom has reacted with implanted silicon atoms, it is no longer available to react with silicon atoms of the junctions. However, not all of the metal atoms react with implanted silicon atoms, so some of the metal atoms are free to react with the silicon atoms of the junctions. Interdiffusion and reaction between those available metal atoms and those silicon atoms of the junctions occurs as a result of heating the semiconductor topography.

Abstract: A semiconductor MOSFET device having a decreased length of the channel region is disclosed. In one embodiment of the device, each gate includes three gate subregions. An enhancement drift drain region underlies the first gate subregion, a channel region underlies the third gate subregion, and each enhancement drift drain region and each channel region are separated by an epitaxial region underlying the second gate subregion. The device of the present invention if used as an amplifier, has a more linear transfer characteristic, less cross talk and less channel interference than a conventional semiconductor MOSFET device having a conventional gate region without gate subregions.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: A very thin (less than 350 angstrom) layer of silicon dioxide (SiO.sub.2) is produced using plasma-enhanced chemical vapor deposition (PECVD) by substantially increasing the time duration of pre-coat and soak time steps of the PECVD process and substantially reducing the flow of silane (SiH.sub.4), the applied high frequency power and the applied pressure in the PECVD process.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: In a semiconductor device such as a thin film transistor a semiconductor region is formed and an insulating film is formed on the semiconductor region to have a contact hole extending to the semiconductor region. An electrically conductive metal layer is formed of aluminum to fill the contact hole. An electrically conductive protection layer is formed on the metal layer to prevent oxidation of the metal layer during manufacturing of the semiconductor device. Material of the protection layer is more difficult to be oxidized than aluminum. A transparent electrode is formed on the protection layer such that the electrode is electrically connected to the semiconductor region. The protection layer may be formed of titanium or a laminate layer of a titanium layer and a titanium nitride layer.

Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an loff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

Abstract: A semiconductor device array having silicon device islands isolated from the substrate by an insulator. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and programming such arrays.

Abstract: In order to prevent an epitaxial layer from contamination by metal when the epitaxial layer is formed on a substrate on which a conductor film comprising a metallic film is formed, a bipolar transistor (semiconductor device) 1 has the first conductor pattern 8 comprising a high-melting metallic film or a high-melting metallic compound film formed on the substrate 4, and the second conductor pattern 9 comprising a non-metallic film formed so as to cover the first conductor pattern 8. On the substrate 4 is formed the first conductivity type base layer 10 on the semiconductor layer comprising an epitaxial layer so as to come in contact with the second conductor pattern 9. Furthermore, when manufacturing the bipolar transistor 1, the semiconductor layer as the base layer 10 is formed with the epitaxial process after the first conductor pattern 8 is covered by the second conductor pattern 9.

Abstract: In the manufacture of a planar channel-type MOS transistor, an n-well is formed in a predetermined region of a p-type semiconductor substrate to define a p-channel transistor region in which element forming regions are located as a p-type active region and a p-type gate electrode. A p-type substrate region adjacent to the p-channel transistor region defines an n-channel transistor region in which element forming regions are located as an n-type active region and an n-type gate electrode. Titanium silicide is formed in self-alignment as an upper layer of each of the p- and n-type active regions and p- and n-type gate electrodes. A boundary of the p- and n-type gate electrodes is a nondoped region where the titanium silicide is formed in an increased thickness as compared to that of the titanium silicide formed on the remaining portion of the gate electrodes.

Abstract: There is disclosed an active matrix liquid crystal display comprising pixels having an improved aperture ratio. A metallization layer makes contact with an active layer through openings. Inside the openings, the active layer is patterned into the same geometry as the metallization layer. That is, the active layer is patterned in a self-aligned manner according to the pattern of the metallization layer. This can enlarge the contact area. Also, the metallization layer does not required to be specially patterned for making contacts. A high aperture ratio can be obtained.

Abstract: A method of fabricating a self-aligned contact window is described. A gate oxide layer, a conductive layer, a first oxide layer and an undoped polysilicon layer are successively formed on a substrate. These layers above are patterned to form a gate structure. A water clean step is performed, producing a recess in the first oxide layer. A second oxide layer is thermally formed on the surface of the gate structure. An undoped polysilicon spacer is formed on the sidewall of the gate structure and a portion of the undoped polysilicon spacer extends into the recess of the first oxide layer. A dielectric layer is formed over the substrate and using the undoped polysilicon spacer as an etching stop, a self-aligned contact window is formed to expose the source/drain region.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: A unit cell of a static random-access memory includes a laminated gate electrode structure adjacent to a diffusion layer. A top surface of the gate electrode structure is coated with a first silicide layer and the diffusion layer includes a second silicide layer. The second silicide layer is separated from the gate electrode structure by a distance that is the same as a width of a sidewall spacer on an opposite side of the gate electrode structure. The portion of the diffusion layer that is exposed between the second silicide layer and the gate electrode structure has a higher impurity concentration than the remainder of the diffusion layer to reduce or eliminate undesired leakage voltage.

Abstract: A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer.

Abstract: An integrated circuit having formed therein a low contact leakage and low contact resistance integrated circuit device electrode. The integrated circuit comprises a semiconductor substrate having an isolation region formed upon the semiconductor substrate. The isolation region bounds an active region of the semiconductor substrate adjoining the isolation region. There is formed at least in part within the active region of the semiconductor substrate an integrated circuit device. The integrated circuit device has an integrated circuit device electrode formed within a portion of the active region of the semiconductor substrate bounded by the isolation region. The integrated circuit also comprises a patterned metal silicide layer aligned upon the integrated circuit device electrode.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A static RAM which is a CMOS static RAM having first and second load transistors, first and second driver transistors, and first and second switching transistors in one memory cell includes: a laminated structure of a first polysilicon layer, a silicide layer and a second polysilicon layer, forming the gate regions of the second load and driver transistors in a body; an interconnection layer comprising a laminated structure of the silicide layer and the second polysilicon layer to form a p-n junction between the drain regions of the first load and driver transistors; and one contact for making the gate regions and the interconnection layer in a body by the second polysilicon layer.

Abstract: In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.