Abstract: For manufacturing an insulated-gate field-effect transistor in a semiconductor device, a refractory metal film is formed on a semiconductor substrate with an insulating film being interposed therebetween. An insulated gate electrode is formed by patterning the refractory metal film and insulating film. After formation of source/drain regions in a surface of the substrate, using the insulated gate electrode as a mask, a poly-silicon film is formed to cover the surface portion of the substrate and the patterned refractory metal film of the gate electrode. The resulting structure is heated to convert at least that portion of the poly-silicon film which lies on the patterned refractory metal film to a silicide film portion. The thus formed silicide film portion is removed so that portions of the doped poly-silicon film are left on the source/drain regions in the surface of semiconductor substrate. These portions of the doped poly-silicon film serve as source/drain electrodes.

Abstract: A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.

Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.

Abstract: A thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi.sub.2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists.

Abstract: A contact and interconnect structure for a semiconductor integrated circuit includes a thin layer of refractory metal on a contact surface of the substrate through an opening in an overlying insulation layer with boron ions implanted into the substrate through the layer of refractory metal and the contact surface to ensure a uniform ohmic contact. An interconnect structure is then formed on the insulation layer and on the thin layer of refractory metal including a first layer of a refractory metal nitride on the insulation layer, a second layer of refractory metal on the first layer of refractory metal nitride, and a second layer of refractory metal nitride on the second layer of refractory metal.

Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Abstract: A poly-crystal silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the poly-crystal silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polyside gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten siliside layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten siliside layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten siliside layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer.

Abstract: A junction suitable for incorporation in diamond electronic devices, such as field effect transistors, U-V photodetectors, capacitors, charge-coupled devices, etc., comprising a double layer structure deposited on the semiconducting diamond film of the electronic device, wherein the double layer structure consists of a layer of intrinsic diamond and a layer of a carrier blocking material. The carrier blocking materials is characterized by a band structure discontinuous with that of diamond resulting in the formation of a depletion layer at the interface. A contact is then formed on this double layer structure.

Abstract: A semiconductor apparatus with MOS transistors for transmitting electrons from an n type source layer to an n type drain layer through a first channel region in an n-channel MOS transistor and transmitting holes from a p type source layer to a p type drain layer through a second channel region in a p-channel MOS transistor consists of a field oxide layer for separating the n-channel MOS transistor from the p-channel MOS transistor, an n type gate electrode mounted on a first gate oxide film arranged on the first channel region, a p type gate electrode mounted on a second gate oxide film arranged on the second channel region and positioned far away from the n type gate electrode to prevent impurities implanted into one of tile gate electrodes from diffusing into the other gate electrode, and a gate metal wiring connecting the gate electrodes through a gate contact hole to miniaturize the transistors.

Abstract: A semiconductor device or a semiconductor integrated circuit includes a field effect transistor having a source region, a drain region and a channel regions formed within a semiconductor substrate. A lower wiring is formed on the semiconductor substrate to form a gate electrode and its extension and oxidized to form an oxide film covering the lower wiring. An upper wiring is formed over the lower wiring on the semiconductor substrate to make contact with the drain or source region. The lower wiring is electrically insulated from the upper wiring by the oxide film.

Abstract: A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.

Abstract: In an integrated circuit arrangement having at least one power component and low-voltage components, the at least one power component is realized in a semiconductor substrate. At least one contact of the power component is arranged on a principal surface of the substrate. The contact is covered with an insulation layer at a surface of which at least one thin-film component, particularly a thin-film transistor, is provided above the contact.

Abstract: A semiconductor device comprises a silicon substrate, a gate electrode including a conductive layer formed on the silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering the conductive layer, a conductive region formed in the surface of the silicon substrate at its portion adjacent to the gate electrode, a second insulating layer formed so as to cover the gate electrode and the silicon substrate, a third insulating layer formed so as to cover the second insulating layer, a contact hole formed by etching to penetrate the third and second insulating layers and to reach the conductive region, and a wiring layer formed to cover the third insulating layer and having a contact part extending inside the contact hole, and electrically connect to the conductive region, the second insulating layer being made of a material having a selected ratio of an etching rate relative to an etching rate of a material of the first insulating

Abstract: In a semiconductor integrated circuit having a block of static memory cells using CMOS transistors and peripheral components using bipolar transistors, metal interconnections in a layer over the CMOS transistors on the substrate are simplified by using buried layers in the substrate as supply and ground lines for the CMOS transistors. This is accomplished by making buried contacts of a metal such as tungsten in each memory cell to make ohmic connection of the diffused layer of n-MOS transistors and the diffused layer of p-MOS transistors respectively to underlying buried layers of opposite conductivities and applying supply voltage or ground potential to each buried layer from the substrate surface by using additional buried contacts which are made at convenient locations outside the memory block. In the case of n-MOS memory cells using resistors or TFTs as load elements, ground potential is applied to the n-MOS transistors by the same method.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: The adhesion between a metallic silicide film and a dielectric layer of a semiconductor device is improved. Formed on a silicon substrate is a gate dielectric layer formed on which is a metallic silicide film. A silicon dielectric layer of a rich-in-silicon-content type, which have a silicon content higher than a silicon content according to the stoichiometric composition formula, is deposited on the metallic silicide film. Because of this arrangement, a semiconductor device which is free from film peeling and which has an electrode wire with a low electrical resistance is achievable without decreasing the concentration of impurity at an electrode. If a passivation silicon oxide layer whose composition is close to a composition according to the stoichiometric composition formula is formed on the silicon oxide layer of a rich-in-silicon-content type, the degradation of the inside of an electrode, and the degradation of a gate oxide layer both caused by unwanted impurities from the outside can be prevented.

Abstract: Epitaxial growth of films on single crystal substrates having a lattice mismatch of at least 10% through domain matching is achieved by maintaining na.sub.1 within 5% of ma.sub.2, wherein a.sub.1 is the lattice constant of the substrate, a.sub.2 is the lattice constant of the epitaxial layer and n and m are integers. The epitaxial layer can be TiN and the substrate can be Si or GaAs. For instance, epitaxial TiN films having low resistivity can be provided on (100) silicon and (100) GaAs substrates using a pulsed laser deposition method. The TiN films were characterized using X-ray diffraction (XRD), Rutherford back scattering (RBS), four-point-probe ac resistivity, high resolution transmission electron microscopy (TEM) and scanning electron microscopy (SEM) techniques. Epitaxial relationship was found to be <100> TiN aligned with <100> Si. TiN films showed 10-20% channeling yield. In the plane, four unit cells of TiN match with three unit cells of silicon with less than 4.0% misfit.

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Abstract: A method of producing a ROM device wherein parallel spaced bit line regions are formed in a semiconductor substrate, blanket layers of (1) polysilicon, (2) etch stop material, and (3) polysilicon, are deposited, the layers etched to form orthogonal parallel word lines on the surface of the substrate, a thick insulating layer deposited over the word lines, a resist layer deposited, exposed and developed to define a desired code implant pattern, the exposed areas of the thick layer removed, and the underlie upper polysilicon layer of the bit line removed, and ion implanted into the substrate to form a code implant.

Abstract: A semiconductor device with a small gate-source capacitance is fabricated by growing a semiconductor epitaxial layer of a first conductivity type on a substrate. Two metal layers that are etched at different rates are successively deposited on the epitaxial layer. The metal layers are dry-etched to form a gate electrode including a wider (larger gate length) upper gate electrode section and a narrower (smaller gate length) lower gate electrode section. The upper gate electrode section is used as a mask for implanting a dopant impurity into the semiconductor epitaxial layer to form a source region having an edge close to but not extending beneath the lower gate electrode section.

Abstract: A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al.sub.2 O.sub.3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof.

Abstract: A semiconductor memory device comprising a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having source and drain diffused layers and a gate, an interlayer insulating film covering the MOS transistor, a contact hole formed in the interlayer insulating film so as to reach one of the source and the drain diffused layers, a metallic layer filling up the contact hole and a capacitor formed on the interlayer insulating film and connected electrically to the one diffused layer through the metallic layer.

Abstract: A semiconductor device having a bonding pad region, and a method of its fabrication. A conductive layer is formed on an isolation layer separating transistors of the device, to anchor the interconnection layer on the bonding region. The conductive layer may be formed from the same layer of material that gate electrodes of the transistors are formed. An oxide insulation layer covers the conductive layer and has at least one opening exposing the conductive layer in the bonding pad region. A barrier metal layer, formed on the diffusion regions and the insulation layer, extends into the opening where it makes a firm direct connection with the exposed conductive layer. A bonding pad is formed on the barrier metal layer by providing the interconnection layer on the barrier metal layer. Since the conductive layer and the barrier metal layer are firmly connected, and secures the interconnection layer in the bonding pad structure.

Abstract: Local interconnect is defined in a polycrystalline silicon layer. Openings to underlying conducting regions are made through an insulating layer after the local interconnect conductor definition. A thin extra polycrystalline silicon layer is then deposited over the device and etched back to form polycrystalline silicon sidewall elements. These sidewalls connect the polycrystalline silicon local interconnect conductors to the underlying conductive regions. Standard silicidation techniques are then used to form a refractory metal silicide on the exposed underlying conductive regions, the polycrystalline silicon sidewall elements, and the polycrystalline silicon local interconnect conductors. This results in a complete silicided connection between features connected by the local interconnect conductors.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate, a p-type impurity diffused region formed in the semiconductor substrate, and a polycide interconnection electrically connected to the p-type impurity diffused region. In the semiconductor device, the polycide interconnection includes a first polysilicon film, a refractory metal silicide film formed on the first polysilicon film, and a second polysilicon film formed on the refractory metal silicide film.

Abstract: Increases in the contact resistance at the aluminum-silicon interface in contact points is inhibited by employing a molybdenum boride conductive barrier layer between the aluminum conductor and the silicon substrate.

Abstract: A semiconductor device applicable to/an SRAM and the like provided with a flip-flop having a pair of transistors and a pair of high resistance loads and a Vcc line connected to the pair of high resistance loads of the flip-flop and holding a power supply voltage is described. The high resistance loads and the Vcc line have a common semiconductor layer which has an concentration of impurities at a portion forming the Vcc line higher than an concentration of impurities of a portion forming the high resistance loads. Furthermore, by forming a conductive layer such as tungsten on the portion of the semiconductor layer where the impurity concentration is high, the Vcc line is formed by the conductive layer or a cooperation of the conductive layer and the semiconductor layer disposed under the conductive layer. By means of such a structure, the Vcc line is surely made low in resistance, and the data access speed is made faster.

Abstract: There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Abstract: A device structure is described wherein metal silicide contacts are made to polycrystalline silicon regions and nonmetal silicide contacts to monocrystalline silicon regions of an integrated circuit device. Polycrystalline silicon regions are formed and patterned. A dielectric masking layer is formed over the polycrystalline and monocrystalline silicon regions. The surfaces of the masking layer are covered and the irregularities of the surfaces filled with an organic material to thereby planarize the surfaces. The organic material is blanket etched until the masking layer which covers the polycrystalline silicon regions is exposed and allowing the masking layer which covers the monocrystalline silicon regions to remain covered with organic material. The exposed masking layer is removed from the polycrystalline regions. The remaining organic material is removed. A layer of metal film is blanket deposited over the wafer. The metal silicide contacts to polycrystalline regions are formed.

Abstract: The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer doped with an impurity and a refractory metal silicide layer has an impurity concentration that is reduced close to a boundary between the polysilicon layer and the refractory metal silicide layer. With this structure, the difference in oxidation speed between the polysilicon layer and the silicide layer is smaller in comparison with a conventional structure, and thus peeling due to bird's beaks can be prevented. The semiconductor device of this structure can be realized by a two-layer polysilicon structure in which the upper layer in contact with the refractory metal silicide layer has a lower impurity concentration, or by a structure in which the peak of the impurity concentration profile is set to be deep within the polysilicon layer during ion implantation.

Abstract: Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.

Abstract: A silicon carbide field-effect transistor is disclosed which includes an MOS structure composed successively of a silicon carbide layer, a gate insulator film, and a gate electrode. The field-effect transistor has source and drain regions formed in the silicon carbide layer, between which the MOS structure is disposed, wherein at least one of the source and drain regions is formed by the use of a Schottky contact on the silicon carbide layer.

Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.