Abstract: The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure.

Abstract: A gate electrode (GE1) includes a polysilicon layer (4C), silicon oxide films (reoxidation films) 14, a metal layer (50C), and silicide films (15). The polysilicon layer (4C) is formed on a main surface (3BS) of a gate insulating film (3B), and the silicon oxide films (14) are formed on the side walls (4CW) of the polysilicon layer (4C). The metal layer (50C) is formed in contact with the main surface (4CS1) of the polysilicon layer (4C) on the opposite side to the gate insulating film (3B). The silicide films (15) are formed on the side walls (50CW) of the metal layer (50C) (which are composed of side walls (51CW and 52CW) of first and second metal layers (51 and 52)). After the silicide films (15) are formed, the metal layer (50C) is protected by the silicide films (15). This structure provides an MOS transistor having a polymetal gate in which oxidation of the metal layer is prevented to realize lower resistivity.

Abstract: A method of making embedded DRAM devices having integrated therein a gate electrode of low sheet resistance satisfying the requirement of high performance logic circuitry is provided. The gate electrode on a semiconductor substrate comprises a gate oxide film, a polysilicon film, a metal, a lightly doped diffusion layer, silicon dioxide spacers, and a source/drain diffusion layer. The metal is planted in an opening, where a capped silicon nitride used to occupy, on top the polysilicon film.

Abstract: A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.

Abstract: A semiconductor device comprises a first insulating layer formed on a substrate; a resistor layer formed on the first insulating layer and having a prescribed electrical resistance; a second insulating layer formed on the resistor layer; a plurality of wirings electrically connected, at positions spaced apart from each other on the resistor layer, to the resistor layer through holes formed in the second insulating layer. Further the semiconductor device comprises a heat storage layer formed in the vicinity of the resistor layer for storing heat generated when a current flows in the resistor layer Hence, even if a large current such as a surge current flows in the resistor layer, heat generated in the resistor layer can be stored in the heat storage layer provided in the vicinity of the resistor layer. Therefore, a stable and reliable semiconductor device free of the breakdown of the resistor layer can be provided.

Abstract: A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.

Abstract: The present invention relates to a semiconductor device formed in a self-light-emitting apparatus having a substrate and a plurality of self-light-emitting elements formed on the substrate, the semiconductor device being used to drive one of the self-light-emitting elements. The semiconductor device includes an active layer of semiconductor material, in which a source region and a drain region are formed, a source electrode having a multi-layered structure including an upper side layer of titanium nitride and a lower side layer of a high melting point metal having low resistance, the source electrode electrically being coupled to the source region, a drain electrode having a multi-layered structure including an upper side layer of titan nitride and a lower side layer of a high melting point metal having low resistance, the source electrode electrically being coupled to said drain region, an insulation layer formed on the active layer, and a gate electrode formed on the insulation layer.

Abstract: A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions and diffusing the impurity ions in the source/drain extensions The temperature of the heat treatment for diffusing step is lower than the maximum of the temperatures of the heat treatment for forming the silicide layer, whereby a MOSFET having excellent short-channel characteristics and a higher reliability can be obtained.

Abstract: A semiconductor device and a method of producing the semiconductor device, fabricated by forming a memory device and a logic device on a single semiconductor substrate, are provided. A side wall (9) and a silicide protection film (10) of a gate electrode (7e) are used instead of forming a silicide protection film in a logic device region (101), whereby the number of steps in forming a logic process consolidating device can be reduced. Further, high concentration impurity regions are formed using the silicide protection film (10) as a mask, whereby a degree of freedom of a condition of implanting ions becomes high.

Abstract: A method to improve LDD corner control during a local interconnect trench oxide etch on a semiconductor device by providing a first etch stop layer over the gate and active regions in the substrate and further providing thereon a second etch stop layer made of polysilicon and having of a different composition than that of the first etch stop layer. By forming a second etch stop layer of polysilicon the present invention improves the selectivity of the local interconnect trench oxide etch, thereby improving the ability of the first and second etch stop layers to stop the etch process at the critical interfaces.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen oxide plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: A semiconductor device more reduced in size and a manufacturing method thereof are provided. A gate electrode is covered with a silicon nitride film having a selecting ratio greater than an NSG film under a prescribed etching condition. A cobalt suicide film is formed on an upper surface of source/drain regions. Furthermore, a refractory metal silicide film forming the gate electrode is formed by a cobalt silicide film.

Abstract: A semiconductor device for ESD protection is provided. The semiconductor device includes a plurality of transistors having a multi-fingered structure, a plurality of multilayer interconnections separated from one another, formed in proportion to the number of common drain regions of the transistors, and connected to the common drain regions of each of the transistors; a pad conductive layer formed on the multilayer interconnections; and a plurality of contact plugs for connecting interconnections of the multilayer interconnections to one another and for connecting the multilayer interconnections to the pad conductive layer so that a current flowing in the common drain regions of the transistors may pass only through the multilayer interconnections connected to the common drain regions and may flow into the pad conductive layer. Parasitic bipolar transistors of all MOSFETs having the multi-fingered structure are turned on, thereby flowing a high current during an ESD event.

Abstract: The present invention relates to a semiconductor device formed in a self-light-emitting apparatus having a substrate and a plurality of self-light-emitting elements formed on the substrate, the semiconductor device being used to drive one of the self-light-emitting elements. The semiconductor device includes an active layer of semiconductor material, in which a source region and a drain region are formed, a source electrode having a multi-layered structure including an upper side layer of titanium nitride and a lower side layer of a high melting point metal having low resistance, the source electrode electrically being coupled to the source region, a drain electrode having a multi-layered structure including an upper side layer of titan nitride and a lower side layer of a high melting point metal having low resistance, the source electrode electrically being coupled to said drain region, an insulation layer formed on the active layer, and a gate electrode formed on the insulation layer.

Abstract: A semiconductor device includes: a first-surface-channel-type MOSFET having a first threshold voltage; and a second-surface-channel-type MOSFET with a second threshold voltage having an absolute value greater than an absolute value of said first threshold voltage. The first-surface-channel-type MOSFET includes: a first gate insulating film formed on a semiconductor substrate; and a first gate electrode, which has been formed out of a poly-silicon film over the first gate insulating film. The second-surface-channel-type MOSFET includes: a second gate insulating film formed on the semiconductor substrate; and a second gate electrode, which has been formed out of a refractory metal film over the second gate insulating film. The refractory metal film is made of a refractory metal or a compound thereof.

Abstract: A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlayer dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

Abstract: Formation of a structure of a conductive layer of an integrated circuit includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide region is formed on the titanium nitride layer. A photoresist layer is formed oh the oxide region for use in patterning the conductive layer. The oxide region may be formed by oxidation of the titanium nitride layer or by depositing an oxide layer on the titanium nitride layer.

Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.

Abstract: A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched onto the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.

Abstract: A method of forming a gate electrode of a multi-layer structure includes a step of supplying a processing gas for poly-crystal film formation and impurities of a P-type into a film formation device, to form a poly-crystal silicon layer doped with P-type impurities, on a surface of a gate film target, a step of maintaining the processing target in the film formation device to prevent formation of an oxide film might not be formed on the poly-crystal silicon layer, and a step of supplying a processing gas for tungsten silicide film formation and impurities of a P-type into the film formation device, to form a tungsten silicide layer doped with impurities of P-type impurities, on the poly-crystal silicon layer on which no oxide film is formed.

Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.

Abstract: An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

Abstract: In a semiconductor memory device, such as a flash memory device, a conductor layer of metal or metal compound having high refractoriness, such as titanium nitride, is formed on a conductor or wiring formed by a buried diffusion layer to reduce resistance thereof. In the present invention, such conductor layer is formed by using small number of process steps and without using photolithography process. For example, after forming the buried diffusion layer for source and drain regions by ion implantation using each floating gate and dummy gate as a mask, titanium nitride is deposited throughout a substrate. Thereafter, by using oxide film growth and etching back process, an oxide film layer remaining on the titanium nitride layer between the floating gate and the dummy gate is fabricated. Then, the titanium nitride layer on the floating gate and on the dummy gate is removed by using this remained oxide film layer as a mask, without using any photolithography process.

Abstract: A CMOS image sensor containing a plurality of unit pixels, each unit pixel having a light sensing region and a peripheral circuit region, includes: a semiconductor substrate of a first conductive type; a transistor formed on the peripheral circuit region of the semiconductor substrate, wherein the transistor has a gate oxide layer and a gate electrode formed on the gate oxide layer; spacers formed on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer are formed on the light sensing region; a first doping region of a second conductive type formed on the light sensing region, wherein the first doping region is extended to an edge of the gate electrode; and a second doping region of the first conductive type formed on the first doping region, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.

Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.

Abstract: Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.

Abstract: The invention is about a method for forming a MOS device. A substrate is provided first. A field oxide layer is formed on the substrate to define an active region. A gate structure is formed on the active region, where the gate structure has a gate oxide layer, a first gate layer, and a cap layer on the gate layer. The field oxide layer has a height substantially equal to the cap layer. The cap layer is thicker than the first gate layer, such as about three times of the first gate layer. A lightly doped region is formed in the substrate. A spacer is formed on a sidewall of the gate structure. A source/drain region is formed at each side of the gate. An epitaxial silicon layer is selectively formed on the source/drain region with a height substantially equal to the height of the first gate layer. The cap layer is removed to form a trench that exposes the first gate layer. A conductive layer is deposited on the first gate layer and the epitaxial silicon layer within the source/drain region.

Abstract: The present invention provides a semiconductor device, comprising a gate electrode of a stacked structure consisting of a polysilicon layer and a metal layer, a cap insulating film formed on the gate electrode, and a gate side wall film formed on the side wall of the gate electrode. The cap insulating film consists of an insulating film containing a silicon oxide-based layer and a silicon nitride layer and serves to protect the upper surface of the gate electrode. Further, the gate side wall film consists of an insulating film containing a silicon nitride film and a silicon oxide film and serves to protect the side surface of the gate electrode.

Abstract: The present invention provide a method for reducing the sheet resistance of the buried layer serving as the bit line or an interconnect of a semiconductor device. The method includes steps of providing the silicon substrate, doping the silicon substrate for forming an extrinsic silicon region, and forming a silicide layer on the extrinsic silicon region for obtaining a low-resistance buried layer.

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: The present invention provides a source/drain structure formed in a semiconductor layer which has source and drain regions of a first conductivity type and a body portion of a second conductivity type disposed between said source and drain regions. The body portion is positioned under a gate insulation film over which a gate electrode is provided. The source region has a first low resistive region which is lower in electrical resistivity than said source region and said drain region having a second low resistive region which is lower in electrical resistively than said source region. For the first present invention, it is important that a distance of an inside edge portion of the first low resistive region from a first interface between the source region and the body portion is shorter than a distance of an inside portion of the second low resistive region from a second interface between the drain region and the body portion.

Abstract: A monollithic CMOS integrated device formed in silicon carbide and method of fabricating same. The CMOS integrated device includes a layer of silicon carbide of a first conductivity type with a well region of a second conductivity type formed in the layer of silicon carbide. A MOS field effect transistor is formed in the well region and a complementary MOS field effect transistor is formed in the silicon carbide layer. The method of fabrication of CMOS silicon carbide includes formation of an opposite conductivity well region in a silicon carbide layer by ion implantation. Source and drain contacts are also formed by selective ion implantation in the silicon carbide layer and the well region. A gate dielectric layer is formed by deposition and reoxidation. A gate electrode is formed on the gate dielectric such that a channel region is formed between the source and the drain when a bias is applied to the gate electrode.

Abstract: A method of forming a silicate dielectric having superior electrical properties comprising forming a metal oxide layer on a Si-containing semiconductor material and reacting the metal oxide with the underlying Si-containing material in the presence of an oxidizing gas is provided. Semiconductor structures comprising the metal silicate formed over a SiO2 layer are also disclosed herein.

Abstract: To provide a conducting path between the metal—0 layer and a metal—1 interconnect layer, two layers with conducting plugs were necessary in the prior art. In the present invention, the conducting regions electrically coupling two regions of the integrated circuit are formed at the same time as the formation of the conducting plugs coupling selected portions of the integrated circuit with the metal—1 interconnect layer. The conducting regions, as with the conducting plugs, extend to surface of the insulating layer upon which the metal—1 interconnect paths are patterned. Using this technique, process steps required in the prior art can be eliminated. This process has the limitation that the metal—1 interconnect layer can not be formed over the conducting regions.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: In a method for manufacturing a conductive pattern layer, a conductive layer is deposited on a substrate, and an etching mask layer is coated onto the conductive layer. First, the conductive layer is etched by a first etching solution using the etching mask layer to expose the substrate a sidewall of the conductive layer. Then, the conductive layer is etched by a second etching solution using the etching mask to retard the sidewall of the conductive layer.

Abstract: A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.

Abstract: A local interconnect for an integrated circuit structure is described capable of bridging over a conductive element to electrically connect together, at the local interconnect level, non-adjacent conductive portions of the integrated circuit structure. After formation of active devices and a conductive element of an integrated circuit structure in a semiconductor substrate, a silicon oxide mask is formed over the structure, with the conductive element covered by the silicon oxide mask. Metal silicide is then formed in exposed silicon regions beneath openings in the mask. The portion of the silicon oxide mask covering the conductive element is then retained as insulation. A silicon nitride etch stop layer and a planarizable dielectric layer are then formed over the structure. An opening is then formed through such silicon nitride and dielectric layers over the conductive element and exposed metal silicide regions adjacent the conductive element.

Abstract: The present invention relates to a semiconductor structure including metal nitride and metal silicide, where a metal silicide layer is formed upon an active area that is part of a junction in order to facilitate further miniaturization that is demanded and dictated by the need for smaller devices. A single PECVD process makes three distinct depositions. First, a metal silicide forms by the reaction: MHal+Si+H2→MSix+HHal, where M represents a metal and Hal represents a preferred halogen or the like. Second, a metal nitride forms upon areas not containing Si by the reaction: MHal+N2+H2→MN+HHal. Third, a metal nitride forms upon areas of evolving metal silicide due to a diffusion barrier effect that makes formation of the metal silicide self limiting. Ultimately, a metal nitride layer will be uniformly disposed in a substantially uniform composition covering all underlying structures upon a semiconductor substrate.

Abstract: The presence and absence of sidewall spacers are used to provide discontinuous and continuous contacts respectively, between a gate electrode and a source/drain region. In particular, first and second spaced apart gate electrodes are formed on an integrated circuit substrate. A source/drain region is formed in the integrated circuit substrate therebetween. The first electrode includes a first sidewall spacer on a first sidewall thereof facing the second gate electrode. The second gate electrode is free of (i.e. does not include a sidewall spacer on a second sidewall thereof facing the first electrode. A metal silicide layer is formed on the first gate electrode, on the second gate electrode and extending from the second gate electrode onto the second sidewall and onto the source/drain region. The first sidewall spacer is free of the metal silicide layer thereon.

Abstract: A method of manufacturing a semiconductor device which has the steps of: forming an insulated gate field effect transistor of a first conductivity type on a semiconductor substrate; forming a first insulating film over the semiconductor substrate, the first insulating film covering the insulated gate electrode; forming a contact window through the first insulating film to at least one of the source/drain regions; embedding a metal plug in the contact window; forming a second insulating film having an oxygen blocking function on the first insulating film, the second insulating film covering the metal plug; forming a capacitor lower electrode on the second insulating film; forming a dielectric oxide film having a perovskite crystal structure on the lower electrode; annealing the semiconductor substrate in an oxygen-containing atmosphere; and forming a capacitor upper electrode on the dielectric oxide film.

Abstract: A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conductivity type. The structure further includes a source layer and a drain layer, each layer being of a second conductivity type, and a channel layer disposed between the source layer and the drain layer. The channel layer has an oxide layer and a gate disposed thereon. At least one of a wet anisotropic and a reactive ion etching step is performed to define a trench having a maximum width of about from 4-6 microns and a depth that extends well into the substrate. An electrically conductive via is then formed by deposition of metal into the trench to thereby establish a low resistance path between the source and the substrate ground.

Abstract: A semiconductor device has a thin semi-insulating polycrystalline silicon (SIPOS) film on the surface of a silicon substrate having a diffused region therein. The SIOPS film is thermally treated at the bottom of a via-plug of an overlying metallic film to form a metallic silicide for electrically connecting the via-plug with the diffused region, whereas the SIPOS film is maintained as it is for insulation on a dielectric film. The SIPOS film protects the diffused regions against over-etching to thereby improve the junction characteristics and provide a larger process margin for contacts between the metallic interconnects and the diffused regions.

Abstract: A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered and a method for making a semiconductor device which has the steps of: forming selectively a given conductive type semiconductor region on a substrate; forming a Co—Si alloy layer on the entire surface of the semiconductor region; introducing Si into the entire surface or part of the Co—Si alloy layer; forming a Ti-included layer in part of the Co—Si alloy layer; and conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.

Abstract: A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory-metal silicide layer disposed on the nitrogen-rich Ti layer.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact.

Abstract: Method and arrangements are provided for removing plasma etch damage to pre-silicidize the surfaces by a wet silicon etch. Following the formation of lightly doped drain (LDD) spacers in conjunction with a refractory metal silicide process, the damage created by the plasma etching to form these sidewall spacers is removed. The silicide that is formed on the pre-silicidized surfaces are substantially free of the etch damage and/or elemental contaminants and exhibits improved quality.

Abstract: A semiconductor structure comprising a plurality of gates located on a semiconductor substrate; wherein insulating spacer is provided on sidewalls of the gates; and metallic silicide located between the gates is provided along with a method for its fabrication. A partially disposable spacer permits increased area for silicide formation without degrading the device short channel behavior.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film on a semiconductor layer, forming a gate electrode on the insulating film, pattering the first insulating film into a second insulating film so that a portion of the semiconductor layer is exposed while the second insulating film has extensions which extend beyond the side edges of the gate electrode, and performing ion introduction for forming impurity regions using the gate electrode and extensions of the gate insulating film as a mask. The condition of the ion introduction is varied in order to control the regions of the semiconductor layer to be added with the impurity and the concentration of the impurity therein.