Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

Abstract: A trench isolation region separating active regions in which MISFETs are formed includes: side insulating films covering the sides of a trench; polycrystalline semiconductor layers of a first conductivity type covering the respective sides of the side insulating films; and a polycrystalline semiconductor layer of a second conductivity type filling a gap between the polycrystalline semiconductor layers of the first conductivity type. Two pn junctions extending along the depth direction of the trench are formed between each of the polycrystalline semiconductor layers of the first conductivity type and the polycrystalline semiconductor layer of the second conductivity type. Upon application of a voltage between the active regions, a depletion layer expands in one of the pn junctions, so that the voltage is also partly applied to the depletion layer. As a result, the concentration of electric field in the side insulating films is relaxed.

Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a channel region located in a semiconductor substrate and a trench located adjacent a side of the channel region. The semiconductor device further includes an isolation structure located in the trench, and a source/drain region located over the isolation structure.

Abstract: A semiconductor device has: a gate insulator film of a transistor formed in a predetermined region on a region of a first conductivity type; a gate electrode of the transistor formed on the gate insulator film; a diffusion layer of a second conductivity type formed on both sides of the gate insulator film on the region of the first conductivity type; and a diffusion layer of the first conductivity type formed on the region of the first conductivity type so as to surround the gate insulator film and the diffusion layer of the second conductivity type. The diffusion layer of the first conductivity type has a higher impurity concentration than the region of the first conductivity type. In such a semiconductor device, the diffusion layer of the first conductivity type is formed so as to be separated from the gate insulator film.

Abstract: In cellular MOSFET transistor arrays using a geometric gate construction, deleterious inherent capacitance induced by the construction is substantially reduced by the use of plugs in between adjacent source regions of transistor source rows and adjacent drain regions of transistor drain rows of the array. Embodiments using field oxide, thicker step gate oxide, dielectric materials in a floating gate construction, and shallow trench isolation region plugs are described.

Abstract: An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturing the device in which the vertically oriented portion of each L-shaped diffused region is formed by directing dopants at an angle toward a sidewall of a trench to form the vertically oriented portion using the edge of the opposing sidewall of the trench as a mask.

Abstract: The present invention relates to a gas insulated gate field effect transistor and a fabricating method thereof which provides an improved insulator between the gate and the source-drain channel of a field effect transistor. The insulator is a vacuum or a gas filled trench. As compared to a conventional MOSFET, the gas insulated gate device provides reduced capacitance between the gate and the source/drain region, improved device reliability and durability, and improved isolation from interference caused by nearby electric fields. The present invention includes the steps of forming a doped source region and drain region on a substrate, forming a gate, forming a gaseous gate insulating trench and forming terminals upon the gate, the source region and the drain region. A plurality of the devices on a single substrate may be combined to form an integrated circuit.

Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

Abstract: Systems for electrically isolating portions of wafers are provided. A representative system includes a first wafer and a first conductor formed at least partially through the first wafer. A first conductor insulating layer is formed at least partially through the first wafer. The first conductor insulating layer engages the first conductor and is disposed between the first conductor and material of the first wafer. A first outer insulating layer also is provided that is formed at least partially through the first wafer. The first outer insulating layer is spaced from the first conductor insulating layer. Both the first conductor insulating layer and the first outer insulating layer are formed of dielectric material. Methods also are provided.

Abstract: In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).

Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.

Abstract: P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

Abstract: Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive elements may be metal, such as tungsten or a tungsten alloy. The invention described in the disclosure provides for advantages including formation of three-dimensional structures without resort to external wiring.

Abstract: An electrolytic capacitor of the invention includes one type of electrode selected from a group consisting of an electrode of at least one type of alloy selected from a group consisting of niobium alloy, titanium alloy, and tungsten alloy, an electrode of mixed sinter of niobium and aluminum, or a fluorine-doped electrode of niobium or niobium alloy and on a surface of the each electrodes a dielectric layer is formed by anodizing the electrode.

Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: A first semiconductor element is a transistor for use in a memory cell region, and a second semiconductor element is a transistor for use in a peripheral circuit region. A first total impurity concentration of a first impurity diffusion region and a second impurity diffusion region of the first semiconductor element is higher than a second total impurity concentration of a fifth impurity diffusion region of the second semiconductor element. Thus, a semiconductor device with semiconductor elements having different threshold voltages is obtained.

Abstract: Photosensitive insulating films are laminated on lower-layer interconnection layers and a connection hole is formed in the photosensitive insulating film, and a interconnection groove is formed in the photosensitive insulating film. The upper-layer interconnection layers fill the connection hole and the groove. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method producing a multi-layer interconnection structure, in which the connection hole and the groove are formed in a simple process, yield is improved, and the number of process steps and cost are reduced.

Abstract: Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

Abstract: A semiconductor device has first and second active regions defined on the principal surface of a silicon substrate, a first n-channel MOS transistor formed in the first active region and having first extension regions and first pocket regions being deeper than the first extension regions and being doped with indium at a first concentration, and a second n-channel MOS transistor formed in the second active region and having second extension regions and second pocket regions being deeper than the second extension regions and being doped with indium at a second concentration lower than the first concentration. Boron ions may be implanted into the second pocket regions. The pocket regions can be formed by implanting indium ions and an increase in leak current to be caused by indium implantation can be reduced.

Abstract: A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer. In addition, an integrated circuit structure is provided. The structure comprises a substrate having a gate dielectric layer on the substrate and a gate conductor on the substrate above the gate dielectric layer. The gate conductor further comprises an edge and a solid state source of fluorine in close proximity to the gate dielectric layer.

Abstract: A trench gate semiconductor device, which can improve the difficulty of channel inversion to thereby improve the switching characteristics as maintaining the effect of suppression of short-channel effects and the high dielectric voltage characteristic between the gate and the drain. The trench gate semiconductor device includes a gate electrode (18) buried in a trench (14) formed in an Si substrate (12) through a gate insulating film (16), and a source/drain diffusion layer (20) formed in a surface region of the Si substrate (12) on the opposite sides of the trench (14). In this trench gate semiconductor device, the corner portions (14a) and (14b) formed by the side walls and the bottom wall of the trench (14) are rounded so as to form concave surfaces concaved inward of the trench (14).

Abstract: A solid electrolytic capacitor comprising a foil coated with a dielectric oxide film, wherein the coated foil has slit or cut edges, and the slit or cut edges have been reformed by anodizing the foil in an aqueous oxalic acid electrolyte, then forming the foil in an aqueous citrate electrolyte, then depolarizing the foil, and then forming the foil in an aqueous phosphate electrolyte.

Abstract: The invention comprises a granulate comprising a) a micronized silicic acid gel (A) with an average particle size from 2 to 15 microns, a specific pore volume from 0.3 to 2.0 ml/g, a specific surface (BET) from 200 to 1000 m2/g, in a concentration from 5 to 60% by weight or b) a hydrated or dehydrated aluminosilicate (B) which contains sodium and/or potassium and/or calcium cations, with a particle size between 1 and 25 microns in a concentration from 5 to 75% by weight and c) an organic additive composition (C) in a concentration from 25 to 95% by weight, but at least 5% more (measured by the oil adsorption process) than that which is necessary to fill all pores of the silicic acid and the spaces between the silicic acid particles and the aluminosilicate and the aluminosilicate particles.

Abstract: A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

Abstract: A method for improving the gate coupling in a flash memory core includes forming floating gates of memory element stacks by depositing a first polysilicon layer having relatively small grain size on a tunnel oxide layer and then depositing a second polysilicon layer on the first, the second polysilicon layer being made of relatively large hemispherical-grained (HSG) polysilicon crystals, which improves gate coupling. In contrast, owing to the relatively small size of its grains, the first layer of polysilicon advantageously establishes a relatively flat surface interface with the tunnel oxide layer that is between the memory stacks and the underlying silicon substrate. Conventional control gates are then established above the HSG layer.

Abstract: A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate structure in which the insulated gate is coupled to the gate electrode through contacts at a plurality of locations. The source electrode includes first and second segments. The first segment is interposed between the drain electrode and the gate electrode and acts as a field plate.

Abstract: A method of manufacturing an integrated circuit utilizes a thin film substrate and a high-k gate dielectric. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.

Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

Abstract: A semiconductor device has first and second active regions defined on the principal surface of a silicon substrate, a first n-channel MOS transistor formed in the first active region and having first extension regions and first pocket regions being deeper than the first extension regions and being doped with indium at a first concentration, and a second n-channel MOS transistor formed in the second active region and having second extension regions and second pocket regions being deeper than the second extension regions and being doped with indium at a second concentration lower than the first concentration. Boron ions may be implanted into the second pocket regions. The pocket regions can be formed by implanting indium ions and an increase in leak current to be caused by indium implantation can be reduced.

Abstract: A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.

Abstract: An object of the invention is to provide a technique for improving the characteristics of a TFT and realizing an optimum structure of the TFT for the driving conditions of a pixel section and a driving circuit by a small number of photo masks. Therefore, a light emitting device has a semiconductor film, a first electrode and a first insulating film nipped between the semiconductor film and the first electrode. Further, the light emitting device has a second electrode and a second insulating film nipped between the semiconductor film and the second electrode. The first and second electrodes are overlapped with each other through a channel forming area arranged in the semiconductor film. In the case of a TFT in which a reduction in off-electric current is considered important in comparison with an increase in on-electric current, a constant voltage (common voltage) is applied to the first electrode at any time.

Abstract: A MOS trench structure integrated with a semiconductor device, for enhancing the breakdown characteristics of the semiconductor device, comprises a semiconductor substrate; a plurality of in-line trenches formed in the semiconductor substrate, a peripheral trench separated from and at least partially surrounding the in-line trenches, a dielectric material lining the trenches; and a conductive material substantially filling the dielectric-lined trenches.

Abstract: Thin film transistor, and organic EL display of the same and method for fabricating the same, including a high temperature substrate of metal or ceramic, a semiconductor layer formed in a region of the substrate having a source region and a drain region, a source electrode in contact with the source region in the semiconductor layer for use as a data line, a pixel electrode formed in each of the pixel region in contact with the drain region in the semiconductor layer, an organic EL layer formed on the pixel electrode, a common electrode formed on the organic EL layer, and a transparent protection film on the common electrode.

Abstract: A semiconductor device has first and second active regions defined on the principal surface of a silicon substrate, a first n-channel MOS transistor formed in the first active region and having first extension regions and first pocket regions being deeper than the first extension regions and being doped with indium at a first concentration, and a second n-channel MOS transistor formed in the second active region and having second extension regions and second pocket regions being deeper than the second extension regions and being doped with indium at a second concentration lower than the first concentration. Boron ions may be implanted into the second pocket regions. The pocket regions can be formed by implanting indium ions and an increase in leak current to be caused by indium implantation can be reduced.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: A silicon substrate comprises a silicon-on-insulator (SOI) portion which includes an insulating silicon dioxide layer beneath a device layer. SOI circuit structures, including SOI field effect transistors, are formed in the device layer. The substrate also comprises a bulk portion. Bulk semiconductor circuit structures are formed in wells in the bulk portion. The bulk circuit structures may be coupled to the SOI circuit structures.

Abstract: A novel shallow-trench isolation (STI) structure and process for forming it is described. More particularly, a recess is formed in a semiconductor substrate. An oxide layer is formed in the recess using thermal oxidation or high-pressure oxidation. If the oxide layer is formed by high-pressure oxidation, then a nitrogen containing gas may be flowed into a high-pressure oxidation chamber to add nitrogen to the oxide layer. The recess may then be filled with a dielectric layer by a deposition process. Alternately, the dielectric layer may be formed using high-pressure oxidation.

Abstract: A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

Abstract: A semiconductor device capable of controlling an electric potential of an electric conductor to reduce both a leakage caused by a punch-through and a junction leakage in a trench isolating structure having the electric conductor in a trench portion. In a trench isolating structure, an insulating film is disposed on an inner surface of a trench provided in a silicon substrate and doped polysilicon doped with phosphorus in a concentration of approximately 1×1020/cm3, for example, is buried as an electric conductor in a lower side of a trench space defined by the insulating film. In addition, a silicon oxide is buried as an insulator in an upper side of the trench space. For the silicon oxide to be used, a TEOS oxide film, a HDP oxide film or a SiOF film having a small dielectric constant may be buried.

Abstract: A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or “offset” towards a shallower part.