With Permanent Threshold Adjustment (e.g., Depletion Mode) Patents (Class 257/402)
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Publication number: 20140077311Abstract: A lateral semiconductor device and/or design including a space-charge generating layer and electrode located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.Type: ApplicationFiled: September 16, 2013Publication date: March 20, 2014Applicant: Sensor Electronic Technology, Inc.Inventors: Grigory Simin, Mikhail Gaevski, Michael Shur, Remigijus Gaska
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Publication number: 20140077312Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: ApplicationFiled: November 18, 2013Publication date: March 20, 2014Applicant: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 8674455Abstract: A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 ?m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.Type: GrantFiled: December 22, 2011Date of Patent: March 18, 2014Inventors: Kensuke Okonogi, Kazuhiro Nojima, Kiyonori Oyu
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Patent number: 8674419Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: GrantFiled: July 19, 2010Date of Patent: March 18, 2014Assignee: Renesas Electronics CorporationInventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Patent number: 8664060Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.Type: GrantFiled: February 7, 2012Date of Patent: March 4, 2014Assignee: United Microelectronics Corp.Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
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Patent number: 8664067Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.Type: GrantFiled: November 18, 2010Date of Patent: March 4, 2014Assignee: Monolithic Power Systems, Inc.Inventor: Donald R. Disney
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Patent number: 8664054Abstract: The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.Type: GrantFiled: April 18, 2011Date of Patent: March 4, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
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Patent number: 8653565Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.Type: GrantFiled: November 26, 2012Date of Patent: February 18, 2014Assignee: Sarda Technologies, Inc.Inventor: James L. Vorhaus
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Patent number: 8643117Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.Type: GrantFiled: January 18, 2010Date of Patent: February 4, 2014Assignee: Hitachi, Ltd.Inventors: Ryuta Tsuchiya, Nobuyuki Sugii, Yusuke Morita, Hiroyuki Yoshimoto, Takashi Ishigaki, Shinichiro Kimura
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Patent number: 8643106Abstract: A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.Type: GrantFiled: June 21, 2007Date of Patent: February 4, 2014Assignees: National University Corporation Tohoku University, Foundation for Advancement of International ScienceInventors: Tadahiro Ohmi, Akinobu Teramoto, Cheng Weitao
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Patent number: 8637385Abstract: According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.Type: GrantFiled: August 24, 2007Date of Patent: January 28, 2014Assignee: Broadcom CorporationInventors: Akira Ito, Henry KuoShun Chen
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Patent number: 8637938Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.Type: GrantFiled: December 2, 2010Date of Patent: January 28, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Akihiro Usujima
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Publication number: 20140021545Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.Type: ApplicationFiled: February 14, 2013Publication date: January 23, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: MAHALINGAM NANDAKUMAR, BRIAN HORNUNG, TERRY JAMES BORDELON, JR., AMITAVA CHATTERJEE
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Patent number: 8598595Abstract: The present application discloses a semiconductor device and a method for manufacturing the same.Type: GrantFiled: September 26, 2010Date of Patent: December 3, 2013Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
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Publication number: 20130313655Abstract: A semiconductor device comprises a substrate; a shallow trench isolation embedded in the substrate and forms at least one opening region; a channel region located in the opening region; a gate stack including a gate dielectric layer and a gate electrode layer, located above said channel region; a source/drain region located on both sides of the channel region, including a stress layer which provides strain for the channel region. A liner layer is provided between the shallow trench isolation and the stress layer, which serves as a crystal seed layer of the stress layer. A liner layer and a pad oxide layer are provided between the substrate and the shallow trench isolation. The liner layer is inserted between the STI and the stress layer of the source/drain region as a crystal seed layer or nucleating layer for epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering.Type: ApplicationFiled: July 18, 2012Publication date: November 28, 2013Applicant: Institute of Microelectronics, Chinese Academy Of SciencesInventors: Guilei Wang, Hushan Cui, Chao Zhao
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Patent number: 8592921Abstract: A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain.Type: GrantFiled: December 7, 2011Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Ulmann, Kelly L. Williams
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Publication number: 20130307090Abstract: The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage.Type: ApplicationFiled: July 23, 2013Publication date: November 21, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Thorsten Kammler, Gunda Beernink, Carsten Reichel
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Patent number: 8587075Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.Type: GrantFiled: November 18, 2008Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Krishna Kumar Bhuwalka, Yi-Ming Sheu, Carlos H. Diaz
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Publication number: 20130299771Abstract: A semiconductor device has a semiconductor body including a source region, a channel region, and a drain region, which are sequentially arranged in a longitudinal direction and are doped with the same type of impurity, a gate electrode including metal, and a gate dielectric layer interposed between the semiconductor body and the gate electrode.Type: ApplicationFiled: January 24, 2013Publication date: November 14, 2013Inventors: Sun-pil Youn, Dong-won Kim, Taek-sung Kim
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Publication number: 20130299918Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.Type: ApplicationFiled: March 15, 2013Publication date: November 14, 2013Inventors: Ju-Youn Kim, Kwang-You Seo
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Patent number: 8581349Abstract: A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.Type: GrantFiled: May 2, 2011Date of Patent: November 12, 2013Assignee: Monolithic 3D Inc.Inventors: Deepak C. Sekar, Zvi Or-Bach, Brian Cronquist
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Patent number: 8575012Abstract: A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow.Type: GrantFiled: April 28, 2011Date of Patent: November 5, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Masaki Haneda
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Patent number: 8575708Abstract: A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.Type: GrantFiled: October 26, 2011Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventor: Chien-Ting Lin
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Patent number: 8563384Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3?, or alternatively, less than one-quarter the dopant concentration of the source and the drain.Type: GrantFiled: February 19, 2013Date of Patent: October 22, 2013Assignee: SuVolta, Inc.Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
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Publication number: 20130264656Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.Type: ApplicationFiled: January 22, 2013Publication date: October 10, 2013Inventors: Yuniarto Widjaja, Jin-Woo Han, Benjamin S. Louie
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Publication number: 20130264657Abstract: A semiconductor device includes a gate electrode formed on a nitride semiconductor layer, and a source electrode and a drain electrode provided on the nitride semiconductor layer so as to interpose the gate electrode therebetween, a first silicon nitride film that covers the gate electrode and the silicon nitride film and has a composition ratio of silicon to nitrogen equal to or larger than 0.75, the first silicon nitride film having compressive stress solely, and a second. silicon nitride film that is formed on the first silicon nitride film and has a composition ratio of silicon to nitrogen equal to or larger than 0.75 solely, a whole stacked layer structure of the first and second silicon nitride films having tensile stress.Type: ApplicationFiled: April 5, 2013Publication date: October 10, 2013Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
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Publication number: 20130249019Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
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Publication number: 20130241006Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.Type: ApplicationFiled: May 7, 2013Publication date: September 19, 2013Applicant: Forschungsverbund Berlin E.V.Inventors: Oliver HILT, Rimma ZHYTNYTSKA, Hans-Joachim WÜRFL
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Patent number: 8530286Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.Type: GrantFiled: December 17, 2010Date of Patent: September 10, 2013Assignee: SuVolta, Inc.Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
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Publication number: 20130221449Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a monolayer that includes organic compounds that contain conductive type dopants on a semiconductor layer, applying a bias voltage to the semiconductor layer, and injecting plasma inactive gas ions against the monolayer, so that conductive type dopants included in the monolayer are impacted by the ions to form the dopant layer injected with the conductive type dopants in a semiconductor layer. This manufacturing method controls the density of the conductive type dopants in the dopant layer by changing a size of functional group.Type: ApplicationFiled: September 8, 2012Publication date: August 29, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tomonori AOYAMA
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Patent number: 8518784Abstract: The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage.Type: GrantFiled: December 29, 2009Date of Patent: August 27, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Thorsten Kammler, Gunda Beernink, Carsten Reichel
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Patent number: 8508001Abstract: Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.Type: GrantFiled: August 25, 2011Date of Patent: August 13, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Steven Langdon, Stefan Flachowsky, Thilo Scheiper
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Publication number: 20130181298Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: ApplicationFiled: March 6, 2013Publication date: July 18, 2013Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Publication number: 20130175640Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the transistor includes a channel region at a surface of a semiconductor substrate. The method includes etching first recesses into the semiconductor substrate adjacent the channel region to define adjacent regions in the semiconductor substrate between the first recesses and the channel region. A first layer of SiGe is epitaxially grown in the first recesses. The method includes etching second recesses through the first layer of SiGe and into the adjacent regions of the semiconductor substrate. Further, a second layer of SiGe is epitaxially grown in the second recesses.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Ralf Illgen, Stefan Flachowsky
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Publication number: 20130168779Abstract: A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.Type: ApplicationFiled: December 26, 2012Publication date: July 4, 2013Applicant: PFC DEVICE CORP.Inventor: PFC DEVICE CORP.
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Publication number: 20130161745Abstract: In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described.Type: ApplicationFiled: September 27, 2012Publication date: June 27, 2013Applicant: International Business Machines CorporationInventor: International Business Machines Corporation
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Publication number: 20130154029Abstract: Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.Type: ApplicationFiled: September 12, 2012Publication date: June 20, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ming Cai, Dechao Guo, Pranita Kulkarni, Chun-Chen Yeh
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Publication number: 20130146992Abstract: A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets II, Gregory J. Uhlmann, Kelly L. Williams
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Publication number: 20130134523Abstract: CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.Type: ApplicationFiled: January 29, 2013Publication date: May 30, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machines Corporation
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Publication number: 20130126983Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.Type: ApplicationFiled: November 16, 2011Publication date: May 23, 2013Inventor: Constantin Bulucea
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Publication number: 20130113052Abstract: A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel.Type: ApplicationFiled: November 18, 2011Publication date: May 9, 2013Inventor: Le Wang
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Publication number: 20130113050Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.Type: ApplicationFiled: November 4, 2011Publication date: May 9, 2013Applicant: International Business Machines CorporationInventors: James W. Adkisson, Brent A. Anderson, Andres Bryant, Edward J. Nowak
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Publication number: 20130113051Abstract: A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.Type: ApplicationFiled: January 2, 2013Publication date: May 9, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machenes Corporation
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Publication number: 20130105914Abstract: A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Inventor: Chien-Ting Lin
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Publication number: 20130105915Abstract: A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Chi WU, Ryan Chia-Jen CHEN
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Patent number: 8426927Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: GrantFiled: May 13, 2011Date of Patent: April 23, 2013Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20130093018Abstract: A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
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Publication number: 20130093021Abstract: A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor.Type: ApplicationFiled: September 20, 2012Publication date: April 18, 2013Applicant: International Business Machines CorporationInventor: International Business Machines Corporation
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Patent number: 8421162Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: GrantFiled: September 30, 2010Date of Patent: April 16, 2013Assignee: Suvolta, Inc.Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Patent number: 8420456Abstract: An object is to provide a semiconductor device with improved reliability in which a defect stemming from an end portion of a semiconductor layer provided in an island shape is prevented, and a manufacturing method thereof. Over a substrate having an insulating surface, an island-shaped semiconductor layer is formed, a first alteration treatment is performed, a first insulating film is formed on a surface of the island-shaped semiconductor layer, the first insulating film is removed, a second alteration treatment is performed on the island-shaped semiconductor from which the first insulating film is removed, a second insulating film is formed on a surface of the island-shaped semiconductor layer, and a conductive layer is formed over the second insulating film. An upper end portion of the island-shaped semiconductor layer has curvature by the first alteration treatment and the second alteration treatment.Type: GrantFiled: May 23, 2008Date of Patent: April 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoru Okamoto