Abstract: A FET comprising an LDD region having a high overlap extension beneath the gate thereof and a pit region on the surface of the substrate immediately below the gate and entirely surrounded by said LDD region. The surface dopant concentration is in the vicinity of the gate corner so as to reduce the local field strength, and thereby decrease the GIDL, whilst keeping high overlap extension so a to maintain a high Ion current. More particularly a region under the gate corner but enclosed by the conventional LDD is counterdoped. Counter-doping of the LDD is performed with a sufficiently low energy, a specific dose and a low angle that the counter-doped region is enclosed into the LDD (at the substrate/gate-oxide interface and keeping high overlap extension between the gate oxide and the non-counter-doped LDD). As an optimum, the counter-doped region is under the gate corner. In that way, high Ion current is ensure with a overlap length is not altered.

Abstract: The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.

Abstract: A semiconductor device manufacturing method includes forming a channel dope layer having a first electric conductive-type inside of a semiconductor substrate, the channel dope layer being formed in a region except for a drain impurity region where dopant impurities for forming a low-concentration drain region are introduced, and the channel dope layer being separated from the drain impurity region; forming a gate electrode on the semiconductor substrate via a gate insulating film; and forming a low-concentration source region inside of the semiconductor substrate on a first side of the gate electrode, and forming a low-concentration drain region in the drain impurity region of the semiconductor substrate on a second side of the gate electrode, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode as a mask.

Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.

Abstract: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

Abstract: A semiconductor device includes a semiconductor substrate, and a p-channel MOS transistor provided on the semiconductor substrate, the p-channel MOS transistor comprising a first gate dielectric film including Hf, a second gate dielectric film provided on the first gate dielectric film and including aluminum oxide, and a first metal silicide gate electrode provided on the second gate dielectric film.

Abstract: A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

Abstract: An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not disposed under substantially all of a heavily doped portion of the drain region, and has a higher dopant concentration compared to the channel region. A process of forming an electronic device can include forming a drain region, a channel region, and a doped region, wherein the drain region has a conductivity type opposite that of the channel and doped region. After forming the drain, channel, and doped regions, the doped region is disposed under substantially all of the channel region, the doped region is not disposed under substantially all of a heavily doped portion of the drain region, and the drain region is laterally closer to the doped region than to the channel region.

Abstract: Improvements in Complementary Metal Oxide Semiconductor (CMOS) devices; in particular, field effect transistors (FETs) and devices using said transistors which are able to take advantage of the higher carrier mobility of electrons compared to holes by replacing the conventional p-channel transistor with an n-channel transistor having a double gate (or vice versa): Such a Unipolar CMOS (U-CMOS) transistor can be realised by adapting the source and/or the drain such that when the body region undergoes inversion at a first surface current, is able to flow between the drain and the source and when the body region undergoes inversion at a second surface current is not able to flow between the drain and the source. Various logic gates may be constructed using U-CMOS transistors.

Abstract: A self-aligned well implantation process may be performed so as to adjust threshold voltage and/or body resistance of transistors. To this end, after removing a placeholder material of gate electrode structures, the implantation process may be performed on the basis of appropriate process parameters to obtain the desired transistor characteristics. Thereafter, any appropriate electrode metal may be filled in, thereby providing gate electrode structures having superior performance. For example, high-k metal gate electrode structures may be formed on the basis of a replacement gate approach, while the additional late well implantation may provide a high degree of flexibility in providing different transistor versions of the same basic configuration.

Abstract: A transistor, an inverter including the transistor, and methods of manufacturing the inverter and the transistor. A gate insulating layer of the transistor has a charge trap region. A threshold voltage may be moved in a positive (+) direction by trapping charges in the charge trap region. The transistor may be an enhancement mode oxide thin-film transistor (TFT) and may be used as an element of the inverter.

Abstract: A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract: A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.

Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.

Abstract: A semiconductor device includes a channel layer formed over a substrate, a gate formed over the channel layer, junction regions formed on both sides of the channel layer to protrude from the substrate, and a buried barrier layer formed between the channel layer and the junction regions.

Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

Abstract: Devices comprising, and a method for fabricating, a remote doped high performance transistor having improved subthreshold characteristics are disclosed. In one embodiment a field-effect transistor includes a channel layer configured to convey between from a source portion and a drain portion of the transistor when the transistor is in an active state. Further, the field-effect transistor includes a barrier layer adjacent to the channel layer. The barrier layer comprises a delta doped layer configured to provide carriers to the channel layer of the transistor, while preferably substantially retaining dopants in said delta-doped layer.

Abstract: To provide a MOSFET which is increased in substrate bias effect ? without increasing parasitic capacitance and junction leak current, the MOSFET includes: a gate electrode (104) formed on a semiconductor substrate (101) and an insulating film (103); a sidewall insulating film (106) covering the side surface of the gate electrode (104); and source/drain regions surrounded by the sidewall insulating film (106) and a shallow trench isolation (102) in a self-alignment manner, in which an impurity concentration of a first conductivity type which is the same type as a well-forming impurity has a profile becoming, in a lower direction of the gate electrode (104), lower in a channel formation region, then higher and again lower, and a high-concentration first conductivity type impurity region (110) is provided, in which the impurity concentration of the first conductivity type is formed to be low in the source/drain regions and to be high below the gate electrode (104) sandwiched between the source/drain regions.

Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.

Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.

Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

Abstract: In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

Abstract: In sophisticated transistor elements, integrity of sensitive gate materials may be enhanced while, at the same time, the lateral offset of extension regions may be reduced. To this end, at least a portion of the extension regions may be implanted at an early manufacturing stage, i.e., in the presence of a protective liner material, which may, after forming the extension regions, be patterned into a protective spacer structure used for preserving integrity of the sensitive gate electrode structure.

Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Abstract: A semiconductor device according to the embodiments comprises a gate insulator formed on a substrate, the gate insulator including a high-dielectric film in whole or part, a reaction film including a first metal on the gate insulator; a metal film including a second metal on the reaction film; and a film including Si formed on the metal film.

Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

Abstract: Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

Abstract: The present invention discloses an integrated junction field effect transistor (JFET) and Schottky diode, comprising a depletion mode JFET which includes a source, a drain and a gate, wherein the drain is not provided with an ohmic contact such that it forms a Schottky diode.

Abstract: The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being in contact with the drain region, the channel region having a longitudinal direction, a highly doped source region in contact with the channel region, the contact between the source region and the channel region forming a source-channel interface, a gate dielectric and a gate electrode covering along the longitudinal direction at least part of the source and channel regions, the gate electrode being situated onto the gate dielectric, not extending beyond the gate dielectric, wherein the effective gate dielectric thickness tgd,eff of the gate dielectric is smaller at the source-channel interface than above the channel at a distance from the source-channel interface, the increase in effective gate dielectric thickness tgd,eff being obtained by means of at least changing the physical thickness tgd of the gate dielectri

Abstract: An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×1018 dopant atoms per cm3. A threshold voltage set region is formed by placement of a threshold voltage offset plane positioned above the screening region. The threshold voltage set region may be formed by delta doping and have a thickness between Lg/5 and Lg/1. The structure uses minimal or no halo implants to maintain channel dopant concentration at less than 5×1017 dopant atoms per cm3.

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.

Abstract: The present disclosure relates to methods of treating a silicon substrate with an ultra-fast laser to create a getter material for example in a substantially enclosed MEMS package. In an embodiment, the laser treating comprises irradiating the silicon surface with a plurality of laser pulses adding gettering microstructure to the treated surface. Semiconductor based packaged devices, e.g. MEMS, are given as examples hereof.

Abstract: The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.

Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

Abstract: A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction.

Abstract: A semiconductor device includes a semiconductor substrate; a first impurity diffusion suppression layer and a thicker second impurity diffusion suppression layer formed on the semiconductor substrate in first and second isolated transistor regions; first and second crystal layers formed on the first and second impurity diffusion suppression layers; first and second gate electrodes formed on the first and second crystal layers; first and second p-type channel regions formed in the semiconductor substrate, the first impurity diffusion suppression layer and respective of the first and second crystal layers below the first and second gate electrodes; and first and second source/drain regions formed on both sides of the first and second channel region; wherein the first and second p-type channels have lower impurity concentrations in respective of the first and second crystal layers than in the semiconductor substrate.

Abstract: A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

Abstract: The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.

Abstract: An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode. At least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted. The implantation region has the first conductivity type impurity and the second conductivity type impurity. Further, the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.

Abstract: A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

Abstract: A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.

Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.

Abstract: A junctionless metal-oxide-semiconductor transistor is described. In one aspect, a transistor device comprises a semiconductor material. The semiconductor material comprises first, second, and third portions. The second portion is located between the first and third portions. The first, second, and third portions are doped with dopants of the same polarity and the same concentration. The transistor device further comprises an electrode connected to the second portion. A current flows between the first and third portions when a voltage is applied to the electrode.

Abstract: A power transistor chip with built-in enhancement mode metal oxide semiconductor field effect transistor and application circuit thereof provides an enhancement mode metal oxide semiconductor field effect transistor in association with two series connected resistors to act as a start-up circuit for the AC/DC voltage converter. The start-up circuit can be shut off after the pulse width modulation circuit of the AC/DC voltage converter circuit works normally and still capable of offering a function of brown out detection for the pulse width modulation circuit as well. Besides, the enhancement mode metal oxide semiconductor field effect transistor is built in the power transistor chip without additional masks and processes during the power transistor chip being fabricated such that the entire manufacturing process is simplified substantively with the economical production cost.

Abstract: A semiconductor device includes a circuit comprising a first transistor in a first Fin; a power supply circuit in a second Fin, the power supply circuit comprising a second transistor connected between the circuit and a power supply line; and a substrate contact electrically connected to the semiconductor substrate and configured to apply a substrate voltage to a substrate, wherein a width of the first Fin in a cross-section of the first Fin perpendicular to a channel length direction of the first transistor is equal to or smaller than a twofold of a largest depletion layer width of a depletion layer formed in a channel part of the first transistor, and a width of the second Fin in a cross-section of the second Fin perpendicular to a channel length direction of the second transistor is larger than a twofold of a largest depletion layer width of a depletion layer in a channel of the second transistor.