Physical Deformation Patents (Class 257/415)
-
Patent number: 11955480Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.Type: GrantFiled: May 11, 2022Date of Patent: April 9, 2024Assignee: STMICROELECTRONICS (TOURS) SASInventor: Mohamed Boufnichel
-
Patent number: 11945712Abstract: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.Type: GrantFiled: May 14, 2021Date of Patent: April 2, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Giorgio Allegato, Lorenzo Corso, Ilaria Gelmi, Carlo Valzasina
-
Patent number: 11938708Abstract: An economical, efficient, and effective formation of a high resolution pattern of conductive material on a variety of films by polymer casting. This allows, for example, quite small-scale patterns with sufficient resolution for such things as effective microelectronics without complex systems or steps and with substantial control over the characteristics of the film. A final end product that includes that high resolution functional pattern on any of a variety of substrates, including flexible, stretchable, porous, biodegradable, and/or biocompatible. This allows, for example, highly beneficial options in design of high resolution conductive patterns for a wide variety of applications.Type: GrantFiled: August 30, 2022Date of Patent: March 26, 2024Assignee: lowa State University Research Foundation, Inc.Inventors: Metin Uz, Surya Mallapragada
-
Patent number: 11919769Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: GrantFiled: November 29, 2022Date of Patent: March 5, 2024Assignee: InvenSense, Inc.Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
-
Patent number: 11897763Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.Type: GrantFiled: November 24, 2020Date of Patent: February 13, 2024Assignee: STMicroelectronics, Inc.Inventor: Jefferson Sismundo Talledo
-
Patent number: 11901192Abstract: To provide an etching processing method and an etching processing apparatus which allow an aluminum oxide film to be etched with high accuracy and with a high selectivity to each of a silicon oxide film and a silicon nitride film, the etching processing method includes the step of placing, in a processing chamber, a wafer having the aluminum oxide film disposed on an upper surface thereof, maintaining the wafer at a temperature of ?20° C. or less, and supplying vapor of hydrogen fluoride from a plurality of through holes in a plate-like member disposed above the upper surface of the wafer with a predetermined gap being provided therebetween only for a predetermined period to etch the aluminum oxide film.Type: GrantFiled: June 30, 2020Date of Patent: February 13, 2024Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Hiroto Otake, Takashi Hattori
-
Patent number: 11897758Abstract: An electrical contacting between a surrounding wiring and a conductor region. The conductor region is situated in a conductor layer above an SOI wafer or SOI chip. A cover layer is situated above the conductor layer and below the surrounding wiring. The cover layer has a contacting region. The contacting region is insulated from the rest of the cover layer by a first configuration of recesses. An opening is formed at least in the contacting region. A metallic material is situated in the opening. The metallic material connects the surrounding wiring and the conductor region.Type: GrantFiled: June 25, 2019Date of Patent: February 13, 2024Assignee: ROBERT BOSCH GMBHInventors: Jochen Reinmuth, Markus Kuhnke, Stefan Majoni, Timo Schary
-
Patent number: 11829565Abstract: A biometric sensor may comprise a plurality of a first type of signal traces formed on a first surface of a first layer of a multi-layer laminate package; at least one trace of a second type, formed on a second surface of the first layer or on a first surface of a second layer of the multi-layer laminate package; and connection vias in at least the first layer electrically connecting the signal traces of the first type or the signal traces of the second type to respective circuitry of the respective first or second type contained in an integrated circuit physically and electrically connected to one of the first layer, the second layer or a third layer of the multi-layer laminate package.Type: GrantFiled: August 12, 2021Date of Patent: November 28, 2023Assignee: Synaptics IncorporatedInventors: Brett Dunlap, Paul Wickboldt
-
Patent number: 11827511Abstract: A MEMS transducer for a microphone includes a closed chamber, an array of conductive pins, a dielectric grid, and a diaphragm. The closed chamber is at a pressure lower than atmospheric pressure. The array of conductive pins is in a fixed position in the closed chamber, distributed in two dimensions, and have gaps formed therebetween. The dielectric grid is positioned within the closed chamber, includes a grid of dielectric material positioned between the gaps of the array of conductive pins, and is configured to move parallel to the conductive pins. The diaphragm is configured to form a portion of the closed chamber and deflect in response to changes in a differential pressure between the pressure within the closed chamber and a pressure outside the transducer. The diaphragm is configured to move the dielectric grid relative to the array of conductive pins in response to a change in the differential pressure.Type: GrantFiled: November 18, 2019Date of Patent: November 28, 2023Assignee: KNOWLES ELECTRONICS, LLCInventors: Peter V. Loeppert, Michael Pedersen
-
Patent number: 11800602Abstract: A multilayered metal nanowire array including a plurality of stacked and separated nanowire array layers each including a plurality of vertically aligned metal nanowires, and a lateral interposer positioned in a gap between each pair of adjacent nanowire array layers and being thermally coupled to the nanowires in the adjacent layers so that the lateral interposers provide thermal conduction between the nanowire array layers and laterally across each nanowire array layer. The nanowire array layers between the interposers can have the same or different thicknesses, the diameter and density of the nanowires can be the same or different, and the nanowire metal can be the same or different.Type: GrantFiled: November 30, 2021Date of Patent: October 24, 2023Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Michael T. Barako, Jesse B. Tice, Max H. Kuciej
-
Patent number: 11800782Abstract: The present application discloses a display panel, a method of manufacturing the same, and a display device, wherein the display panel includes a first substrate, a second substrate, and a light-transmitting planarization layer, a light transmittance of the first substrate is lower than that of the second substrate; at least one first through hole is provided on the substrate, at least one blind hole is provided on the second substrate, and the blind hole is provided corresponding to the first through hole; the light-transmitting planarization layer is provided in the blind hole to flatten the bottom of the blind hole, thus obtaining a relatively flat film surface.Type: GrantFiled: February 26, 2021Date of Patent: October 24, 2023Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Yunti Zhang
-
Patent number: 11787685Abstract: For manufacturing an optical microelectromechanical device, a first wafer of semiconductor material having a first surface and a second surface is machined to form a suspended mirror structure, a fixed structure surrounding the suspended mirror structure, elastic supporting elements which extend between the fixed structure and the suspended mirror structure, and an actuation structure coupled to the suspended mirror structure. A second wafer is machined separately to form a chamber delimited by a bottom wall having a through opening. The second wafer is bonded to the first surface of the first wafer in such a way that the chamber overlies the actuation structure and the through opening is aligned to the suspended mirror structure. Furthermore, a third wafer is bonded to the second surface of the first wafer to form a composite wafer device. The composite wafer device is then diced to form an optical microelectromechanical device.Type: GrantFiled: December 18, 2020Date of Patent: October 17, 2023Assignee: STMicroelectronics S.r.l.Inventors: Luca Seghizzi, Nicolo′ Boni, Laura Oggioni, Roberto Carminati, Marta Carminati
-
Patent number: 11753296Abstract: A MEMS device includes a lower substrate having a resonator, an upper substrate disposed to oppose an upper electrode of the resonator, a bonding layer sealing an internal space between the lower substrate and the upper substrate, and wiring layers that contain the same metal material as the bonding layer. Moreover, a rare gas content of each of the wiring layers is less than 1×1020 (atoms/cm3).Type: GrantFiled: September 1, 2020Date of Patent: September 12, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Masakazu Fukumitsu
-
Patent number: 11742816Abstract: An acoustic wave device includes: a substrate; a lower electrode, an air gap being interposed between the lower electrode and the substrate; a piezoelectric film located on the lower electrode; and an upper electrode located on the piezoelectric film such that a resonance region where at least a part of the piezoelectric film is interposed between the upper electrode and the lower electrode is formed and the resonance region overlaps with the air gap in plan view, wherein a surface facing the substrate across the air gap of the lower electrode in a center region of the resonance region is positioned lower than a surface closer to the piezoelectric film of the substrate in an outside of the air gap in plan view.Type: GrantFiled: December 10, 2019Date of Patent: August 29, 2023Assignee: TAIYO YUDEN CO., LTD.Inventors: Taisei Irieda, Tatsuya Aoki, Mitsuhiro Habuta, Satoshi Orito, Shinji Taniguchi
-
Patent number: 11736845Abstract: A microphone component and a method for fabricating a microphone component are disclosed. In an embodiment, a microphone component includes a membrane and a backplate, wherein the membrane includes a plurality of holes, and wherein the holes have diameters smaller than 5 ?m.Type: GrantFiled: March 19, 2021Date of Patent: August 22, 2023Assignee: TDK CorporationInventors: Pirmin Hermann Otto Rombach, Dennis Mortensen
-
Patent number: 11728073Abstract: A method for manufacturing an electronic component includes providing a substrate and a functional layer supported by the substrate; forming a structured protection layer on a side of the substrate to which the functional layer is attached, wherein the structured protection layer has a recess so that a portion of the functional layer is exposed; applying a dispersion comprising a solvent and electrically conductive components to the exposed portion of the functional layer so that the recess is at least partially filled with the dispersion; drying the dispersion in order to create an electrically conductive layer; and removing the structured protection layer.Type: GrantFiled: November 11, 2021Date of Patent: August 15, 2023Assignee: Infineon Technologies AGInventors: Markus Meyer, Jorge Eduardo Adatti Estevez, Alexandra Marina Roth
-
Patent number: 11697889Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.Type: GrantFiled: December 18, 2019Date of Patent: July 11, 2023Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Keith E. Fogel
-
Patent number: 11658169Abstract: A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.Type: GrantFiled: August 28, 2020Date of Patent: May 23, 2023Assignee: Kioxia CorporationInventor: Junichi Shibata
-
Patent number: 11656243Abstract: A physical quantity sensor includes, when three directions orthogonal to one another are defined as a first direction, a second direction, and a third direction, a substrate; and a moving member facing the substrate in the third direction via a gap and becoming displaced in the third direction in relation to the substrate. The moving member has a first region that has a plurality of penetration holes penetrating the moving member in the third direction and having a square opening shape as viewed from the third direction, and a second region having no penetration hole. At least one of a length in the first direction and a length in the second direction of the second region is equal to or greater than S0+2×S1, where S0 is a length of one side of the penetration hole, and S1 is a space between the penetration holes next to each other.Type: GrantFiled: February 26, 2021Date of Patent: May 23, 2023Inventor: Satoru Tanaka
-
Patent number: 11634317Abstract: A micro-electromechanical system (MEMS) device comprises a fixed portion and a proofmass suspended by at least one composite beam. The composite beam is cantilevered relative to the fixed portion and extends between a first end that is integrally formed with the fixed portion and a second distal end. The composite beam comprises an insulator having a top surface and at least two side surfaces; a conductor extending away from the fixed portion and surrounding at least a portion of the insulator; and a second conductor positioned adjacent to the top surface of the conductor and extending parallel with the insulator away from the fixed portion. The second conductor is separated from the first conductor to provide a low parasitic conductance of the composite beam.Type: GrantFiled: April 23, 2019Date of Patent: April 25, 2023Assignee: Kionix, Inc.Inventors: Andrew Hocking, Martin Heller, Wenting Gu
-
Patent number: 11630012Abstract: A pressure sensor includes a micromechanical sensor element including a pressure-sensitive diaphragm, which spans a cavity in a base material and includes a diaphragm electrode. A fixed counter electrode is situated inside the cavity and, with the diaphragm electrode, forms a first measuring capacitor for detecting a first measuring pressure. A reference capacitor is situated inside the cavity and includes a first and a second fixed reference electrode. The pressure sensor is operable in a first operating mode, in which the first measuring capacitor and the first reference capacitor are interconnected in a first bridge circuit. The pressure sensor is operable in a second operating mode, in which the diaphragm electrode, the counter electrode and the reference electrodes are interconnected in such a way that the diaphragm electrode, together with the at least one first reference electrode, forms a second measuring capacitor for detecting a second measuring pressure.Type: GrantFiled: February 3, 2022Date of Patent: April 18, 2023Assignee: ROBERT BOSCH GMBHInventors: David Slogsnat, Joachim Kreutzer
-
Patent number: 11591211Abstract: A method of manufacturing a semiconductive structure includes receiving a first substrate; disposing an interconnection layer on the first substrate; forming a plurality of conductors over the interconnection layer; filing gaps between the plurality of conductors with a film; forming a barrier layer over the film; removing the barrier layer; and partially removing the film to expose a portion of the interconnection and leave a portion of the interconnection layer covered by the film.Type: GrantFiled: October 7, 2019Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Cheng Liu, Cheng-Yu Hsieh, Shang-Ying Tsai, Kuei-Sung Chang
-
Patent number: 11585711Abstract: A capacitive sensor is disclosed. In an embodiment a semiconductor device includes a die including a capacitive pressure sensor integrated on a CMOS circuit, wherein the capacitive pressure sensor includes a first electrode and a second electrode separated from one another by a cavity, the second electrode including a suspended tensile membrane, and wherein the first electrode is composed of one or more aluminum-free layers containing Ti.Type: GrantFiled: January 10, 2019Date of Patent: February 21, 2023Assignee: SCIOSENSE B.V.Inventors: Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg, Kailash Vijayakumar, Jörg Siegert, Alessandro Faes
-
Patent number: 11580767Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.Type: GrantFiled: September 10, 2020Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
-
Patent number: 11575081Abstract: A MEMS structure may include a substrate, a first metal layer arranged over the substrate, an aluminum nitride layer at least partially arranged over the first metal layer and a second metal layer including one or more patterns arranged over the aluminum nitride layer. The first metal layer may include an electrode area configured for external electrical connection and one or more isolated areas configured to be electrically isolated from the electrode area and further configured to be electrically isolated from external electrical connection. Each pattern of the second metal layer may be arranged to at least partially overlap with one of the isolated area(s) of the first metal layer.Type: GrantFiled: November 26, 2019Date of Patent: February 7, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.Inventors: Bevita Kallupalathinkal Chandran, Jia Jie Xia, Tze Sheong Neoh
-
Patent number: 11554952Abstract: A method for closing openings in a flexible diaphragm of a MEMS element. The method includes: providing at least one opening in the flexible diaphragm, situating sealing material in the area of the at least one opening, melting-on at least the applied sealing material in the area of the at least one opening, and subsequently cooling the melted-on material to close the at least one opening.Type: GrantFiled: December 20, 2018Date of Patent: January 17, 2023Assignee: Robert Bosch GmbHInventors: Bernhard Gehl, Christoph Hermes, Juergen Butz
-
Patent number: 11542151Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) apparatus. The MEMS apparatus includes a base substrate and a conductive routing layer disposed over the base substrate. A bump feature is disposed directly over the conductive routing layer. Opposing outermost sidewalls of the bump feature are laterally between outermost sidewalls of the conductive routing layer. A MEMS substrate is bonded to the base substrate and includes a MEMS device directly over the bump feature. An anti-stiction layer is arranged on one or more of the bump feature and the MEMS device.Type: GrantFiled: July 21, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Sung Chang, Fei-Lung Lai, Shang-Ying Tsai, Cheng Yu Hsieh
-
Patent number: 11542154Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: GrantFiled: March 18, 2021Date of Patent: January 3, 2023Assignee: InvenSense, Inc.Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
-
Patent number: 11531415Abstract: A module (1) for a display and/or operating device (10), the module (1) comprising a first transparent electrode (3) having a first matrix of a plurality of electrode islands (3a, 3b, 3c); a transparent piezoelectric layer (2) having a first and a second area; a second transparent electrode (4); a transparent substrate (12); and a conductive path arrangement (25) having at least a first conductive path (24a) on the transparent piezoelectric layer (2), wherein the transparent substrate (12) is coated with the second transparent electrode (4) and the second transparent electrode (4) is disposed between the transparent substrate and the transparent piezoelectric layer (2), and the first area is coated with the first transparent electrode and the second area is coated with the second transparent electrode (4); and the electrode islands (3a, 3b, 3c) are arranged electrically insulated from one another on the first area of the transparent piezoelectric material (2), wherein the at least first conductive path (24a)Type: GrantFiled: January 17, 2020Date of Patent: December 20, 2022Assignee: Bayerische Motoren Werke AktiengesellschaftInventors: Thomas Tille, Florian Miedl
-
Patent number: 11493471Abstract: According to one embodiment, a sensor includes a first sensor part. The first sensor part includes a first counter electrode, a first movable electrode, a first layer, and a first intermediate layer. The first movable electrode is between the first counter electrode and the first layer. The first intermediate layer is between the first movable electrode and a portion of the first layer. A first gap is located between the first counter electrode and the first movable electrode. A distance between the first counter electrode and the first movable electrode changes according to a concentration of a gas around the first sensor part. The first layer includes a crystal. The first intermediate layer is amorphous, or a crystallinity of the first intermediate layer is less than a crystallinity of the first layer. A width of the first layer is greater than a width of the first intermediate layer.Type: GrantFiled: August 19, 2021Date of Patent: November 8, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yumi Hayashi
-
Patent number: 11459228Abstract: A physical quantity sensor includes a substrate, a movable body that is provided displaceably in a state of being opposed to the substrate and is provided with a first through-hole and a second through-hole as through-holes, and a protrusion configured integrally with the substrate at a side of the movable body of the substrate, and in which the protrusion is provided at a position where the protrusion overlaps the through-hole and the movable body in plan view.Type: GrantFiled: August 5, 2019Date of Patent: October 4, 2022Assignee: Seiko Epson CorporationInventor: Satoru Tanaka
-
Patent number: 11442294Abstract: A transmissive polarization control device includes: a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including: a first conductivity type region having a conductivity type, a second conductivity type region having a conductivity type, and a pn junction located between the first and second conductivity type regions; a loop electrode disposed on the first surface and configured such that an electric current flowing through the loop produces a magnetic field in a direction penetrating the pn junction; and a near-field light formation region in which an impurity of the first conductivity type introduced as a dopant into the first conductivity type region for formation of near-field light is distributed. A polarization direction of linearly polarized light traveling through a region surrounded by the loop electrode and the near-field light formation region is rotated according to the electric current.Type: GrantFiled: June 23, 2020Date of Patent: September 13, 2022Assignee: NICHIA CORPORATIONInventors: Takuya Kadowaki, Motoichi Ohtsu, Tadashi Kawazoe
-
Patent number: 11444048Abstract: In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.Type: GrantFiled: August 14, 2018Date of Patent: September 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Sreenivasan K. Koduri
-
Patent number: 11422075Abstract: The invention relates to a device (10) for determining the mechanical properties of nanomaterials comprising a substrate (30) onto which a nanomaterial specimen (40) can be anchored, wherein said substrate (30) is mechanically connected to an actuator (20) on one side and to a sensor (50) on the opposite side, and wherein the substrate (30) is configured to generate a fracture line (32?) in a predetermined position which divides the substrate (30) into two parts (31,31?), wherein a first part (31) is connected to the actuator (20) and a second part (31?) is connected to a sensor (50), in order to allow a relative movement between the actuator (20) and the sensor (50).Type: GrantFiled: September 28, 2018Date of Patent: August 23, 2022Assignee: UNIVERSITA' DEGLI STUDI DI TRENTOInventors: Maria Pantano, Nicola Pugno, Giorgio Speranza
-
Patent number: 11408912Abstract: An optomechanical device for producing and detecting optical signals comprising a proof mass assembly, one or more laser devices, and a circuit. The one or more laser devices are configured to generate a first optical signal and a second optical signal. The circuit is configured to modulate, with an electro-optic modulator (EOM), the second optical signal, output the first optical signal and the second optical signal to the proof mass assembly, generate a filtered optical signal corresponding to a response by the proof mass assembly to the first optical signal without the second optical signal, and generate an electrical signal based on the filtered optical signal, wherein the EOM modulates the second optical signal based on the electrical signal.Type: GrantFiled: August 13, 2019Date of Patent: August 9, 2022Assignee: Honeywell International Inc.Inventors: Joshua Dorr, Chad Fertig, Arthur Savchenko, Steven Tin, Neil Krueger
-
Patent number: 11339050Abstract: An actuator device includes a support portion, a movable portion, a connection portion which connects the movable portion to the support portion on a second axis, a first wiring which is provided on the connection portion, a second wiring which is provided on the support portion, and an insulation layer which includes a first opening exposing a surface opposite to the support portion in a first connection part located on the support portion in one of the first wiring and the second wiring and covers a corner of the first connection part. The rigidity of a first metal material forming the first wiring is higher than the rigidity of a second metal material forming the second wiring. The other wiring of the first wiring and the second wiring is connected to the surface of the first connection part in the first opening.Type: GrantFiled: February 13, 2020Date of Patent: May 24, 2022Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Sadaharu Takimoto, Yuki Morinaga, Daiki Suzuki, Yoshihisa Warashina
-
Patent number: 11342266Abstract: An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.Type: GrantFiled: July 21, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Cheng, Chia-Hua Chu
-
Patent number: 11343904Abstract: The present invention relates to a multi-functional platform, including: a printed circuit board (PCB) having a single chip integrated thereon; wherein the single chip includes a substrate having an environmental system disposed thereon, the environmental system including a plurality of three-dimensional (3D) printed, patterned and multi-layered nanostructures disposed on the substrate. The nanostructures include an on-chip heater, a power source, a wireless communication module, and a plurality of sensors, the sensors including at least one of a gas sensor, a pressure sensor, or a temperature sensor, each of which is directly deposited on the substrate and printed with a plurality of nanomaterials. The 3D patterned nanostructures use functionalized nanomaterials, which are patterned by a template using one of directed assembly or nano-offset printing, to deposit the nanostructures directly on the substrate of the single chip.Type: GrantFiled: February 22, 2021Date of Patent: May 24, 2022Assignee: United States of America as represented by the Administrator of NASAInventor: Mahmooda Sultana
-
Patent number: 11335678Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.Type: GrantFiled: February 25, 2020Date of Patent: May 17, 2022Assignee: STMICROELECTRONICS (TOURS) SASInventor: Mohamed Boufnichel
-
Patent number: 11312623Abstract: The present disclosure relates to a method of forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a dielectric structure over a substrate. A dielectric layer arranged along a top of the dielectric structure is patterned to define a via hole exposing an uppermost one of the plurality of interconnect layers. An extension via is formed within the via hole and one or more conductive materials are formed over the dielectric layer and the extension via. The one or more conductive materials are patterned to define a sensing electrode over and electrically coupled to the extension via. A microelectromechanical systems (MEMS) substrate is bonded to the substrate. The MEMs substrate is vertically separated from the sensing electrode.Type: GrantFiled: July 31, 2020Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
-
Patent number: 11312617Abstract: A MEMS device formed using the materials of the BEOL of a CMOS process where a post-processing of vHF and post backing was applied to form the MEMS device and where a total size of the MEMS device is between 50 um and 150 um. The MEMS device may be implemented as an inertial sensor among other applications.Type: GrantFiled: January 8, 2021Date of Patent: April 26, 2022Assignee: Nanusens SLInventor: Josep Montanyà Silvestre
-
Patent number: 11293821Abstract: In an embodiment, a pressure sensor module includes a base electrode surrounding at least a part of a bottom electrode, an anchor arrangement on top of the base electrode including at least two electrically conductive walls that both surround at least the part of the bottom electrode and an electrically conductive layer that covers at least the bottom electrode and the anchor arrangement such that a cavity is formed between the bottom electrode, the anchor arrangement and the electrically conductive layer, wherein, on at least one side of the cavity, a proportionate area of the electrically conductive walls in a cross section extending from a surface of an inner wall of the anchor arrangement facing the cavity to a surface of an outermost wall of the anchor arrangement facing away from the cavity in a plane parallel to a plane of the bottom electrode is equal to or less than 10%.Type: GrantFiled: July 19, 2017Date of Patent: April 5, 2022Assignee: SCIOSENSE B.V.Inventors: Roel Daamen, Kailash Vijayakumar, Hendrik Bouman, Remco Henricus Wilhelmus Pijnenburg, Twan Van Lippen
-
Patent number: 11267692Abstract: A MEMS device formed using the materials of the BEOL of a CMOS process where a post-processing of vHF and post backing was applied to form the MEMS device and where a total size of the MEMS device is between 50 um and 150 um. The MEMS device may be implemented as an inertial sensor among other applications.Type: GrantFiled: January 8, 2021Date of Patent: March 8, 2022Assignee: Nanusens SLInventor: Josep Montanyà Silvestre
-
Patent number: 11269464Abstract: An electronic pen includes a tubular casing, and a first coupling member and a second coupling member that are coupled to each other in a hollow portion of the casing in an axial direction of the casing. In the axial direction, the first coupling member and the second coupling member are coupled to each other, and in a coupling portion between the first coupling member and the second coupling member, a welded portion that attaches the first coupling member and the second coupling member to each other is formed. The first coupling member is coupled to a core. The second coupling member holds a printed circuit board. The core of the core-side component is made of a conductive material. The second coupling member includes a conductor that supplies, to the core, a signal from a signal transmitting circuit on the printed circuit board with a battery.Type: GrantFiled: April 14, 2021Date of Patent: March 8, 2022Assignee: Wacom Co., Ltd.Inventors: Kohei Tanaka, Hiroyuki Fujitsuka, Kenichi Ninomiya, Takenori Kaneda, Gunji Ishihara, Takashi Yamaguchi, Taketoshi Ito, Shuanglei Li
-
Patent number: 11269377Abstract: The present disclosure relates to the field of flexible display technology and provides a flexible display panel, a method for manufacturing the same, and a display device, which can reduce the stress in the direction perpendicular to the bending surface applied on a portion of the signal lead wire located in the bending area when the flexible display panel is bent. The flexible display panel includes a flexible basal substrate including a first surface, the first surface including a bending area provided with a plurality of protrusions, and a signal lead wire located on a side of the first surface facing away from the flexible basal substrate. The signal lead wire extends across the bending area and has a shape substantially matching the plurality of protrusions.Type: GrantFiled: October 29, 2018Date of Patent: March 8, 2022Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng Huang, Zhifeng Zhan, Hai Zheng, Fushi Jin
-
Patent number: 11262294Abstract: An illumination unit is described that includes a first light source positioned on a first axis and a second light source on a second axis that intersects and is angularly offset with respect to the first axis. The illumination unit includes a reflector having an aperture through which the first axis extends and a reflective surface angled with respect to the first axis and second axis.Type: GrantFiled: May 3, 2019Date of Patent: March 1, 2022Assignee: Siemens Healthcare Diagnostics Inc.Inventor: Jeffrey R. Jasperse
-
Patent number: 11251081Abstract: The method of manufacturing a plurality of semiconductor chips (100) comprises a step A) of providing a semiconductor substrate (1) having a plurality of integrated electronic circuits (2) on a top side (10) thereof. In a step B), a sacrificial layer (3) is applied on one side of the semiconductor substrate. In a step C), holes (30) are introduced in the sacrificial layer so that at least one hole is formed above each electronic circuit. In a step D), the semiconductor substrate is adhered to a carrier (5) with the sacrificial layer at the front, an adhesive layer (4) being used between the sacrificial layer and the carrier, and the adhesive layer filling the holes so that holding elements (40) from the adhesive layer are formed in the holes. In a step E) the semiconductor substrate is thinned.Type: GrantFiled: October 25, 2018Date of Patent: February 15, 2022Assignee: OSRAM OLED GMBHInventors: Thomas Schwarz, Lutz Höppel, Thorsten Frank Baumheinrich, Jens Richter
-
Patent number: 11242243Abstract: Embodiments of the application provide a MEMS chip and an electrical packaging method for a MEMS chip. The MEMS chip includes a MEMS device layer, a first isolating layer located under the MEMS device layer, and a first conducting layer located under the first isolating layer. At the first isolating layer, there are a corresponding quantity of first conductive through holes in locations corresponding to conductive structures in a first region and in locations corresponding to electrodes in a second region. At the first conducting layer, there are M electrodes spaced apart from one another, and the M electrodes are respectively connected to M of the first conductive through holes. At the first conducting layer, electrodes in locations corresponding to at least some of the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to at least some of the electrodes in the second region.Type: GrantFiled: October 18, 2019Date of Patent: February 8, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventor: Yuming Wei
-
Patent number: 11229090Abstract: A method for fabricating a multilayered metal nanowire array including providing a metal seed layer, stacking a plurality of porous templates on the seed layer so that a gap forms between each adjacent pair of templates, depositing by electroplating a metal in the pores so that the metal produces nanowires in the templates and lateral interposers in the gaps between the templates, and dissolving the templates so as to produce the multilayered nanowire array including the lateral interposers. The layers between the interposers can have the same or different thicknesses, the diameter and density of the pores in each layer can be the same or different and the metal deposited in the pores of the layers can be the same or different.Type: GrantFiled: May 10, 2019Date of Patent: January 18, 2022Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Michael T. Barako, Jesse B. Tice, Max H. Kuciej
-
Patent number: 11192776Abstract: A device having both an electronic assembly having an electronic component assembled on a first substrate, and also a body defining a cavity having a first end in fluid flow communication with a fluid, the electronic component extending inside the cavity and the first substrate including a portion in contact with a wall of the cavity. The coefficient of thermal expansion of the material of the first substrate is less than that of the electronic component, and the electronic component is assembled on the first substrate by a brazing type assembly method involving the application of heat. A method of making an electronic assembly. An assembly obtained by the method.Type: GrantFiled: October 9, 2019Date of Patent: December 7, 2021Assignee: SAFRAN ELECTRONICS & DEFENSEInventors: Jean-Christophe Riou, Nawres Sridi-Convers, Eric Bailly