Physical Deformation Patents (Class 257/415)
  • Patent number: 10266395
    Abstract: A semiconductive structure includes a first substrate including a first surface and a second surface opposite to the first surface, a second substrate disposed over the first surface and including a first device and a second device, a first capping structure disposed over the second substrate, and including a via extending through the first capping structure to the second device, a first cavity surrounding the first device and defined by the first capping structure and the first substrate, a second cavity surrounding the second device and defined by the first capping structure and the first substrate, and a second capping structure disposed over the first capping structure and covering the via, wherein the second cavity and the via are sealed by the second capping structure.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Cheng Liu, Hsin-Ting Huang, Shang-Ying Tsai, Kuei-Sung Chang
  • Patent number: 10266396
    Abstract: The present disclosure provides a semiconductor device, which includes a first substrate comprising an upper surface and a second substrate disposed over the first substrate. The semiconductor device also includes a first electrode disposed in the second substrate and configured to move in a direction substantially parallel to the upper surface in response to a pressure difference, and a second electrode disposed in the second substrate. The second electrode is configured to provide a capacitance in conjunction with the first electrode.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Wen-Chuan Tai, Chia-Ming Hung, Hsiang-Fu Chen, Jung-Huei Peng, Chun-Wen Cheng
  • Patent number: 10250998
    Abstract: A Micro-Electro-Mechanical Systems (MEMS) device includes a substrate, a dielectric supporting layer, a diaphragm, a backplate. The substrate has a substrate opening corresponding to a diaphragm region. The dielectric supporting layer is disposed on the substrate, having a dielectric opening corresponding to the substrate opening to form the diaphragm region. The diaphragm within the dielectric opening is held by the dielectric supporting layer at a periphery. The backplate is disposed on the dielectric supporting layer, having a plurality of venting holes, connecting to the dielectric opening. The backplate includes a conductive layer and a passivation layer covering over the conductive layer at a first side opposite to the diaphragm, wherein a second side of the conductive layer is facing to the diaphragm and not covered by the passivation layer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: April 2, 2019
    Assignee: Solid State Systems Co., Ltd.
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Cheng-Wei Tsai
  • Patent number: 10240957
    Abstract: A thermal airflow sensor includes a semiconductor device, a protective film a bonding wire, and a resin. The resin covers over a part of the semiconductor device so that the bonding wire is covered with the resin and the region including a thin-wall portion is exposed. The protective film is not covered with the resin and has an outer peripheral edge located outside the thin-wall portion.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 26, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ryosuke Doi, Hiroshi Nakano, Keiji Hanzawa
  • Patent number: 10227231
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: March 12, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Merrill Albert Hatcher, Jr., Jonathan Hale Hammond, Jon Chadwick, Julio C. Costa, Jan Edward Vandemeer
  • Patent number: 10217699
    Abstract: A preformed lead frame includes a plurality of lead frame units and intersecting cutting paths extending between two adjacent rows of said lead frame units, and a molding layer. Each of the lead frame units includes a die pad, and a plurality of spaced-apart leads. Each of the cutting paths has a plurality of metallic connecting portions and etched grooves. The molding layer embeds the lead frame units and the connecting portions. Each of the etched grooves is indented from the top surface of the molding layer. A top open end of each of the etched grooves includes two opposite curved edges respectively meeting an adjacent one of the leads of one of the lead frame units and an adjacent one of the leads of the other one of the lead frame units.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 26, 2019
    Assignee: Chang Wah Technology Co., Ltd.
    Inventor: Chia-Neng Huang
  • Patent number: 10215988
    Abstract: An optical system for displaying light from a scene includes an active optical component that includes a first plurality of light directing apertures, an optical detector, a processor, a display, and a second plurality of light directing apertures. The first plurality of light directing apertures is positioned to provide an optical input to the optical detector. The optical detector is positioned to receive the optical input and convert the optical input to an electrical signal corresponding to intensity and location data. The processor is connected to receive the data from the optical detector and process the data for the display. The second plurality of light directing apertures is positioned to provide an optical output from the display.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 26, 2019
    Assignee: Marsupial Holdings, Inc.
    Inventors: William P. Parker, Michael A. Strauss, Ian M. Rousseau, Eric M. Gallo
  • Patent number: 10210978
    Abstract: A haptic actuator having a base structure, a beam rotatably attached to the base structure by an axial member, a first coil portion, and a second coil portion is presented. The beam has a first end that includes a first magnet with magnetic poles having a first polarity, and a second end that includes a second magnet with magnetic poles having a second, opposite polarity. The first coil portion and the second coil portion are configured to generate magnetic field lines. The magnetic poles of the first magnet and the magnetic poles of the second magnet are aligned to be parallel with a central axis of the first coil portion or the second coil portion when the beam is in an equilibrium position. The beam is configured to rotate via the axial member in response to electrical current being passed through the first coil portion or the second coil portion.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: February 19, 2019
    Assignee: IMMERSION CORPORATION
    Inventors: Vahid Khoshkava, Mansoor Alghooneh, Mohammadreza Motamedi
  • Patent number: 10211128
    Abstract: An electronic device structure includes a leadframe with a die pad and a lead. A semiconductor die is mounted adjacent to the die pad. A clip having a clip tail section is attached to the lead. The clip further has a clip top section attached to the clip tail section, and the clip top section is attached to a die top side of the semiconductor die with a conductive material. The clip further has an opening disposed to extend through the clip top section. In one embodiment, after a reflow step the conductive material forms a conductive fillet at least partially covering sidewall surfaces of the opening, and has a height within the opening with respect to a bottom surface of the clip top section. The opening and the conductive fillet provide an improved approach to monitoring coverage of the conductive material between the clip top section and the die top side of the semiconductor die.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: February 19, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventor: Marc Alan Mangrum
  • Patent number: 10202275
    Abstract: A process for manufacturing an integrated semiconductor device, envisages: forming a MEMS structure; forming an ASIC electronic circuit; and electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: February 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Tocchio, Lorenzo Corso
  • Patent number: 10204855
    Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Alejandro Levander, Tatyana Andryushchenko, David Staines, Mauro Kobrinsky, Aleksandar Aleksov, Dilan Seneviratne, Javier Soto Gonzalez, Srinivas Pietambaram, Rafiqul Islam
  • Patent number: 10196260
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 5, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Merrill Albert Hatcher, Jr., Jonathan Hale Hammond, Jon Chadwick, Julio C. Costa, Jan Edward Vandemeer
  • Patent number: 10192850
    Abstract: First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: January 29, 2019
    Assignee: SiTime Corporation
    Inventors: Paul M. Hagelin, Charles I. Grosjean
  • Patent number: 10187059
    Abstract: A light-emitting touch-switch device includes a first circuit board, a cap unit and a light-emitting element. The first circuit board is electrically coupled to a sensing chip. The cap unit is disposed on the first circuit board and that is at least partially made of an electrically conductive plastic material having a resistance of equal to or smaller than 1×105?. The cap unit and the first circuit board cooperate to define a receiving space. The light-emitting element is disposed in the receiving space and is electrically coupled to the first circuit board. A light-emitting touch-switch module including the light-emitting touch-switch device is also disclosed.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: January 22, 2019
    Assignees: Lite-On Opto Technology (Changzhou) Co., Ltd., Lite-On Technology Corp.
    Inventors: Shuo-Hung Chen, Chin-Kuan Lin
  • Patent number: 10177064
    Abstract: The present disclosure relates to an air-cavity package, which includes a substrate, a base, and a semiconductor die. The substrate includes a substrate body, thermal vias extending through the substrate body, and a metal trace on a bottom side of the substrate body and separate from the thermal vias. The base includes a base body, a perimeter wall extending about a perimeter of the base body, and a signal via structure. Herein, the bottom side of the substrate body resides on the perimeter wall to form a cavity, and the signal via structure extends through the perimeter wall and is electrically coupled to the metal trace. The semiconductor die is mounted on the bottom side of the substrate body, exposed to the cavity, and electrically coupled to the metal trace. The thermal vias conduct heat generated from the semiconductor die toward a top side of the substrate body.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 8, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Kevin J. Anderson, Anthony Chiu, Tarak A. Railkar
  • Patent number: 10173887
    Abstract: A device with an out-of-plane electrode includes a device layer positioned above a handle layer, a first electrode defined within the device layer, a cap layer having a first cap layer portion spaced apart from an upper surface of the device layer by a gap, and having an etch stop perimeter defining portion defining a lateral edge of the gap, and an out-of-plane electrode defined within the first cap layer portion by a spacer.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: January 8, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Andrew Graham, Gary Yama, Gary O'Brien
  • Patent number: 10171917
    Abstract: The present invention provides a capacitive microphone including a MEMS microphone. In the microphone, the movable or deflectable membrane/diaphragm moves in a lateral manner relative to the fixed backplate, instead of moving toward/from the fixed backplate. The squeeze film damping is substantially avoided, and the performances of the microphone is significantly improved.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 1, 2019
    Assignee: GMEMS Technologies International Limited
    Inventors: Guanghua Wu, Xingshuo Lan
  • Patent number: 10160634
    Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
    Type: Grant
    Filed: July 16, 2017
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Bucknell C. Webb
  • Patent number: 10160632
    Abstract: A system and method for forming a sensor device with a buried first electrode includes providing a first silicon portion with an electrode layer and a second silicon portion with a device layer. The first silicon portion and the second silicon portion are adjoined along a common oxide layer formed on the electrode layer of the first silicon portion and the device layer of the second silicon portion. The resulting multi-silicon stack includes a buried lower electrode that is further defined by a buried oxide layer, a highly-doped ion implanted region, or a combination thereof. The multi-silicon stack has a plurality of silicon layers and silicon dioxide layers with electrically isolated regions in each layer allowing for both the lower electrode and an upper electrode. The multi-silicon stack further includes a spacer that enables the lower electrode to be accessible from a topside of the sensor device.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: December 25, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Andrew Graham, Ando Feyh, Gary O'Brien
  • Patent number: 10163945
    Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 25, 2018
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Etienne Menard, Matthew Meitl, Joseph Carr
  • Patent number: 10155658
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 18, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Merrill Albert Hatcher, Jr., Jonathan Hale Hammond, Jon Chadwick, Julio C. Costa, Jan Edward Vandemeer
  • Patent number: 10150666
    Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: December 11, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Lorenzo Baldo, Enri Duqi, Flavio Francesco Villa
  • Patent number: 10146257
    Abstract: In an embodiment, a foldable device having a sensor is described. In an embodiment, the device comprises: A folding area, wherein the folding area is configured to rotate according to an axis of rotation caused by folding the device, causing deformation of the folding area. The folding area comprises: a layer of strain sensitive material having particles, wherein conductivity of the strain sensitive material is configured to change when the layer experiences the deformation. The folding area comprises a layer of conductor lines configured to detect the change of the conductivity of the strain sensitive material, wherein the layer of the conductor lines includes a plurality of contacting points with the strain sensitive material.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 4, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vicente Calvo Alonso, Jouko Lång
  • Patent number: 10147906
    Abstract: A high efficacy multi-layer seal structure formed on an organic light emitting diode device and the process for depositing the same. A thin film seal is formed over the substrate having OLED layers, and includes a first metallic layer formed over the substrate, an inorganic layer formed over the first metallic layer, and a second metallic layer formed of the inorganic layer. The metallic layers comprise one or more oxide or nitride layers, each oxide or nitride comprising a metal. The inorganic layer comprises a metal oxide, a metal nitride or a metal oxynitride. The process for forming the multi-layer seal structure includes depositing the first metallic layer over the substrate using atomic layer deposition, depositing the inorganic layer over the first metallic layer using sputtering, and then depositing the second metallic layer over the inorganic layer using atomic layer deposition.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: December 4, 2018
    Assignee: eMagin Corporation
    Inventors: Amalkumar Ghosh, Fridrich Vazan
  • Patent number: 10138542
    Abstract: Strain-gated logic devices are important for the development of advanced flexible electronics. Using a dual-monolayer-promoted film-transfer technique, a flexible multilayer structure capable of undergoing large compressive deformation was prepared. Formation of a crease in the gap between electrodes at a geometrically tunable strain leads to formation of an electrical connection in a reversible and reproducible fashion. A strain-gated electrical switch includes at least two conductive electrodes disposed on a surface of an elastomer substrate, the at least two conductive electrodes forming a gap between the at least two electrodes in an off-state of the strain-gated electrical switch, the gap diminishing under compressive strain to form a crease, the compressive strain pressing the at least two electrodes into contact with each other in an on-state of the strain-gated electrical switch.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: November 27, 2018
    Assignee: University of Massachusetts
    Inventors: Ryan C. Hayward, Dayong Chen, Bin Xu
  • Patent number: 10121623
    Abstract: A microelectromechanical system switch includes a signal input line, a signal output line, a deformable conducting membrane electrically connected to the signal output line and including a contact dimple facing the signal input line, and an actuation electrode. The membrane has a planar round shape, with a radial opening in the direction of the signal input line, narrowing from the periphery towards the center of the membrane, the contact dimple being formed in the central region of the membrane, the actuation electrode has the same shape as the membrane, and the gap between the membrane, facing the actuation electrode, and the actuation electrode is an airgap only.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 6, 2018
    Assignee: AIRMEMS
    Inventors: Pierre Blondy, Romain Stefanini, Ling Yan Zhang, Abedel Halim Zahr
  • Patent number: 10109536
    Abstract: According to an embodiment, a micro-fabricated test structure includes a structure mechanically coupled between two rigid anchors and disposed above a substrate. The structure is released from the substrate and includes a test layer mechanically coupled between the two rigid anchors. The test layer includes a first region having a first cross-sectional area and a constricted region having a second cross-sectional area smaller than the first cross-sectional area. The structure also includes a first tensile stressed layer disposed on a surface of the test layer adjacent the first region.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 23, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christoph Glacer, Alfons Dehe, John Brueckner
  • Patent number: 10074294
    Abstract: A conductive trace design is described that minimizes the possibility of crack initiation and propagation in conductive traces during bending. The conductive trace design has a winding trace pattern that is more resistant to the formation of cracks at high stress points in the conductive traces. The conductive trace design includes a cap that helps ensure electrical connection of the conductive trace even though one or more cracks may begin to form in the conductive portion of the conductive trace.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: September 11, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Zhen Zhang, Paul Stephen Drzaic, Seyeoul Kwon, Sangcheon Youn, Heeseok Yang, Chanwoo Lee, Soyoung Jo, Anna Ha, Dongyoon Kim, Saemleenuri Lee, Yoondong Cho
  • Patent number: 10061965
    Abstract: A fingerprint sensing unit includes a carrier substrate, a fingerprint sensing chip on an upper surface of the carrier substrate, a molding layer, a light-pervious cover layer on the molding layer, and an adhesive layer between the light-pervious cover layer and the molding layer. The fingerprint sensing chip is electrically connected to the carrier substrate. The molding layer covers the fingerprint sensing chip.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 28, 2018
    Assignee: J-METRICS TECHNOLOGY CO., LTD.
    Inventors: Wei-Ting Lin, Shih-Chun Kuo
  • Patent number: 10061962
    Abstract: A fingerprint identification module includes a substrate, a fingerprint sensor die, a covering adhesive layer, a cover plate and a mold compound layer. The fingerprint sensor die is attached on the substrate for sensing a fingerprint image. The covering adhesive layer is formed on a top surface of the fingerprint sensor die. The cover plate is attached on the covering adhesive layer. The mold compound layer is formed over the substrate. The fingerprint sensor die, the covering adhesive layer and the cover plate over the substrate are molded together through the mold compound layer, and the cover plate is exposed. The fingerprint identification module has small thickness and enhanced sensing accuracy.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: August 28, 2018
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Ching-Hui Chang, Tung-Ying Wu
  • Patent number: 10060817
    Abstract: Disclosed is an integrated circuit, comprising a semiconductor substrate carrying a plurality of circuit elements; and a pressure sensor including a cavity on said semiconductor substrate, said cavity comprising a pair of electrodes laterally separated from each other; and a flexible membrane over and spatially separated from said electrodes such that said membrane interferes with a fringe field between said electrodes, said membrane comprising at least one aperture. A method of manufacturing such an IC is also disclosed.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: August 28, 2018
    Assignee: ams International AG
    Inventors: Axel Nackaerts, Willem Frederik Adrianus Besling, Klaus Reimann
  • Patent number: 10061961
    Abstract: A sensor-compatible overlay is disclosed which uses anisotropic conductive material to increase capacitive coupling of a conductive object through the overlay material to a capacitive sensor. The anisotropic conductive material has increased conductivity in a direction orthogonal to the capacitive sensor. In one embodiment, the overlay is configured to enclose a device which includes a capacitive sensor. In another embodiment, the overlay is configured as a glove.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: August 28, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Roman Ogirko, Hans Klein, David G. Wright, Igor Kolych, Andriy Maharyta, Hassane El-Khoury
  • Patent number: 10057976
    Abstract: An interface layout for a vertical interface of a first semiconductor component is disclosed. A first one or more conductors configured to carry power signals extends vertically from the first semiconductor component. A second one or more conductors configured to carry data signals extends vertically from the first semiconductor component. A third one or more conductors configured to carry ground signals extending vertically from the first semiconductor component. The first one or more conductors are further configured to shield and separate the second one or more conductors. A fourth one or more conductors extends horizontally from the first one or more conductors adjacent to and terminating proximal to the third one or more conductors. A fifth one or more conductors extending horizontally from the third one or more conductors adjacent to and terminating proximal to the first one or more conductors and the fourth one or more conductors.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 21, 2018
    Assignee: XILINX, INC.
    Inventors: Hong Shi, Siow Chek Tan, Sarajuddin Niazi
  • Patent number: 10053358
    Abstract: A microelectromechanical systems (MEMS) structure includes a substrate, an epitaxial polysilicon cap located above the substrate, a first cavity portion defined between the substrate and the epitaxial polysilicon cap, and a first graphene component having at least one graphene surface immediately adjacent to the first cavity portion.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 21, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Gary Yama, Seow Yeun Yee, Franz Laermer, Ashwin Samarao
  • Patent number: 10046964
    Abstract: A method for fabricating an integrated MEMS-CMOS device. The method can include providing a substrate member having a surface region and forming a CMOS IC layer having at least one CMOS device overlying the surface region. A bottom isolation layer can be formed overlying the CMOS IC layer and a shielding layer and a top isolation layer can be formed overlying a portion of bottom isolation layer. The bottom isolation layer can include an isolation region between the top isolation layer and the shielding layer. A MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer, and can be etched to form at least one MEMS structure having at least one movable structure and at least one anchored structure.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: August 14, 2018
    Assignee: mCube Inc.
    Inventors: Te-Hsi “Terrence” Lee, Sudheer S. Sridharamurthy, Shingo Yoneoka, Wenhua Zhang
  • Patent number: 10035701
    Abstract: There is provided a method for forming a composite cavity and a composite cavity formed using the method.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: July 31, 2018
    Assignee: Advanced Semiconductor Manufacturing Co. Ltd.
    Inventors: Yuanjun Xu, Yilin Yan, Weijia Xue
  • Patent number: 10032592
    Abstract: A force sensing switch for use in an electronic device can include one or more dome switches disposed over a top surface of a deflectable beam. One or more strain gauges can be disposed over at least one surface of the deflectable beam. An electronic device that includes at least one force sensing switch can further include a processing device operatively connected to the one or more strain gauges. Alternatively or additionally, an electrode can be disposed under a bottom surface of the deflectable beam and a capacitance measured between the bottom surface and the electrode.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: July 24, 2018
    Assignee: APPLE INC.
    Inventors: Ryan P. Brooks, John M. Brock, Storrs T. Hoen
  • Patent number: 10031157
    Abstract: A functional device includes a fixed electrode portion including a first fixed electrode portion and a second fixed electrode portion, a first wiring portion connected to the first fixed electrode portion, and a second wiring portion connected to the second fixed electrode portion. At least one of the first wiring portion and the second wiring portion is provided with a branch portion. One wiring line extending from the branch portion is connected to the fixed electrode portion, and another wiring line extending from the branch portion is provided along the first wiring portion or the second wiring portion.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 24, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Satoru Tanaka
  • Patent number: 10017376
    Abstract: Measures are described which contribute simply and reliably to the mechanical decoupling of a MEMS functional element from the structure of a MEMS element. The MEMS element includes at least one deflectable functional element, which is implemented in a layered structure on a MEMS substrate, so that a space exists between the layered structure and the MEMS substrate, at least in the area of the functional element. According to the invention, a stress decoupling structure is formed in the MEMS substrate in the form of a blind hole-like trench structure, which is open to the space between the layered structure and the MEMS substrate and extends into the MEMS substrate to only a predefined depth, so that the rear side of the MEMS substrate is closed, at least in the area of the trench structure.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 10, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Johannes Classen, Jochen Reinmuth, Mirko Hattass, Ralf Reichenbach, Antoine Puygranier
  • Patent number: 10014462
    Abstract: An apparatus comprises: a body terminal comprising a first body electrode and a second body electrode; a gate terminal comprising a first gate electrode and a second gate electrode; a first actuator between the first body electrode and the first gate electrode, the first actuator comprising a first piezoelectric material; a second actuator between the second body electrode and the second gate electrode, the second actuator comprising a second piezoelectric material; a beam comprising a first end attached to the first actuator, a second end attached to the second actuator, and a suspended section between the first end and the second end; a metal channel attached to the suspended section of the beam; a source terminal extending over the beam; and a drain terminal extending over the beam.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 3, 2018
    Assignee: Carnegie Mellon University
    Inventors: Usama Zaghloul Heiba, Gianluca Piazza
  • Patent number: 10008427
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 9997595
    Abstract: A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies Dresden GmbH
    Inventor: Thoralf Kautzsch
  • Patent number: 9981841
    Abstract: A micro-electromechanical systems (MEMS) device includes a MEMS substrate having a first opening, a second opening, and a membrane layer comprising a first membrane disposed over the first opening and a second membrane disposed over the second opening. The MEMS device also includes a carrier substrate bonded to a first side of the MEMS substrate, the carrier substrate having a first cavity exposing the first membrane and a second cavity exposing the second membrane, and a cap substrate bonded to a second side of the MEMS substrate. The cap substrate has a third cavity connected to the first opening and a fourth cavity connected to the second opening. The first membrane, the first cavity, and the third cavity are part of a pressure sensor. The fourth cavity extends completely through the cap substrate. The second membrane, the second cavity, and the fourth cavity are part of a microphone.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9984945
    Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Rae Cho, Sun-Dae Kim, Nam-Gyu Baek, Hyung-Gil Baek
  • Patent number: 9978720
    Abstract: An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Gottfried Beer, Juergen Hoegerl
  • Patent number: 9976913
    Abstract: Embodiments of the present disclosure include nanowire field-effect transistors, systems for temperature history detection, methods for thermal history detection, a matrix of field effect transistors, and the like.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: May 22, 2018
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jesus Alfonso Caraveo Frescas, Husam Alshareef
  • Patent number: 9976918
    Abstract: A pressure sensing device having a Dirac material and a method of operating the same are provided. The pressure sensing device includes a Dirac material pattern disposed on a substrate and having a band structure in which Dirac cones meet at a Dirac point. A source electrode and a drain electrode are respectively connected to the Dirac material pattern. A spacer layer including a cavity on the Dirac material pattern is disposed on the substrate. A gate electrode overlapping the Dirac material pattern is disposed on the cavity.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 22, 2018
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Seung-Beck Lee, Onejae Sul
  • Patent number: 9969607
    Abstract: A device and method utilizes interconnecting layers separated by an insulating layer. A layered structure comprises a first and a second layer of electrically conductive material, and a third layer of electrically insulating material between them. A via trench is fabricated that extends from the second layer through the third layer into the first layer, a surface on the first layer of electrically conductive material forming a bottom surface of the via trench. An ink-jetting set-up for a mixture of liquid carrier and nanoparticles of conductive material is formed, and a specific process period is determined. Capillary flow of nanoparticles to peripheral edges of an ink-jetted blob of said mixture is induced. The mixture is ink-jetted into a blob on the via trench; the layered structure is heated to evaporate the liquid carrier. The interconnection element is higher at a certain point than between opposing side walls.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: May 15, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Heikki Kuisma, Matti Mäntysalo
  • Patent number: 9969608
    Abstract: Systems and methods for packaging a MEMS device to measure the in-stream pressure within a pipe are provided. Embodiments herein avoid the use of a metal housing enclosing the MEMS device or die pad of the MEMS device. Instead, the MEMS device is mounted directly to the pipe using a ceramic carrier. In preferred embodiments, the ceramic carrier is soldered, brazed, welded or eutectic bonded to the metal pipe.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: May 15, 2018
    Assignee: DUNAN SENSING, LLC
    Inventors: Tom Kwa, Danny Do, Gary Winzeler, Emir Vukotic
  • Patent number: 9960091
    Abstract: A package includes: a semiconductor element; a case having an opening and housing the semiconductor element; and a lid having a rectangular parallelepiped shape and occluding the opening of the case. In the package, the lid is joined to an end portion of the opening of the case, and includes a bent portion surrounded by a portion joining the lid to the case and extending along a longitudinal side of the lid.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 1, 2018
    Assignees: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Tomohiro Mitani, Takashi Uchida, Georg Refcio