Abstract: A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.

Abstract: A physical quantity sensor includes: a sensor substrate including a first support substrate, a first insulation film and a first semiconductor layer, which are stacked in this order; a cap substrate including a second support substrate disposed on the first semiconductor layer, and has a P conductive type; and multiple electrodes, which are separated from each other. The first support substrate, the first insulation film and the first semiconductor layer have the P conductive type. The physical quantity is detected based on a capacitance between the plurality of electrodes, and the electrodes are disposed in the first semiconductor layer.

Abstract: A method for fabricating a micro-electro-mechanical system (MEMS) device. The method comprises placing a guiding mask on an application platform, the guiding mask including an opening that defines the position of a MEMS part to be placed on the application platform. The method further comprises placing the MEMS part into the opening of the guiding mask on the application platform, and removing the guiding mask from the application platform after the MEMS part is bonded to the application platform.

Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.

Abstract: An electronic apparatus includes a first die, a second die, a third die, and a fourth die, wherein a portion of the second die and a portion of the third die are movably connected between the first die and the fourth die.

Abstract: A semiconductor sensor has a first semiconductor layer as a base, an insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the insulating layer. A recess is formed from a bottom surface of the first semiconductor layer up to a top surface of the insulating layer. The second semiconductor layer is covered with the insulating layer in an outer circumference of a top surface of the recess. A sensitive region of the second semiconductor layer is exposed in a region except the outer circumference of the top surface of the recess.

Abstract: A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially overlying a cantilever beam top surface, at least partially overlying a cantilever beam bottom surface, or embedded within the cantilever beam. In one example, forming thin-films on the substrate includes: selectively forming a first layer with a first stress level; selectively forming a first active Si region overlying the first layer; and selectively forming a second layer overlying the first layer with a second stress level. The thin-film cantilever beam is formed from the first and second layers, while the TFT source/drain (S/D) and channel regions are formed from the first active Si region.

Abstract: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.

Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.

Abstract: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.

Abstract: In various embodiments, a dosimeter is employed to passively record a peak pressure (e.g., a peak blast pressure) and/or a maximum acceleration experienced by the dosimeter.

Abstract: A premold housing for accommodating a chip structure in which a part of the housing that is connected to the chip structure is connected in a manner that permits elastic deflection to another part of the housing which is attached to the supporting structure bearing the entire housing, the two housing parts not contacting one another.

Abstract: Provided are a contact-force sensor package and a method of fabricating the same. The contact-force sensor package includes an elastic layer comprising a side that contacts a source of a contact-force; and a substrate layer adhered to the opposing side of the elastic layer from the side that contacts the source of the contact-force and comprising a cantilever beam separated from the elastic layer and deformed due to the contact-force, a pillar extending from a free end portion of the cantilever beam to the elastic layer and transferring the contact-force from the elastic layer to the cantilever beam, and a deformation sensing element for generating an electrical signal that is proportional to a degree of deformation of the cantilever beam.

Abstract: A micro-electro-mechanical system (MEMS) pressure sensor includes a silicon spacer defining an opening, a silicon membrane layer mounted above the spacer, and a silicon sensor layer mounted above the silicon membrane layer. The silicon membrane layer forms a diaphragm opposite of the spacer opening, and a stationary perimeter around the diaphragm and opposite the spacer. The silicon sensor layer includes a movable electrode and a stationary electrode separated by a substantially constant gap and respectively located above the diaphragm and the stationary perimeter of the silicon membrane layer. The movable electrode and the diaphragm move in response to a pressure applied to the diaphragm where an overlap area between sidewall surfaces of the movable and the stationary electrodes create a capacitance proportion to the pressure.

Abstract: A small structure which uses bonding wires to prevent disturbance and provide support and a method of fabricating the same are provided. The small structure includes a floating body having a plurality of first contact pads, a base having a plurality of second contact pads, and a plurality of bonding wires electrically connecting the first and second contact pads and elastically supporting the floating body. The method of fabricating the small structure includes preparing a base, forming a sacrificial layer on the base, disposing a floating body on the sacrificial layer, connecting the base and the floating body with bonding wires, and removing the sacrificial layer. Thereby, fabrication costs of the small structure are reduced.

Abstract: The invention provides a MEMS package including: a MEMS chip including a first surface, a second surface, a first cavity, and a sensing device, the sensing device defining a first end of the first cavity; a leadframe including a second cavity and being electrically connected to the first surface of the MEMS chip, the second cavity being adjacent to the sensing device of the MEMS chip; a conductive layer disposed on the second surface of the MEMS chip to define a second end of the first cavity and grounded via the leadframe that is electrically connected to the conductive layer so as to provide electromagnetic shielding to the MEMS chip; and an encapsulant covering the MEMS chip, the leadframe, and the conductive layer to define an shape of the MEMS package and allowing outer surfaces of the leadframe to emerge from the MEMS package.

Abstract: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.

Abstract: According to the present invention, a SOI substrate includes a first silicon substrate having first and second surfaces; a second silicon substrate having first and second surfaces; and a first insulating layer formed between first surface of the first silicon substrate and the first surface of the second silicon substrates. The first surface of the first silicon substrate is partly depressed to form a thin-layer region thereat. The first insulating layer is formed at least in the thin-layer region.

Abstract: A micromechanical component, in particular a micromechanical sensor, having a first wafer and a second wafer is provided, the first wafer having at least one structural element, and the second wafer having at least one mating structural element, and, in addition, the structural element and the mating structural element are designed in such a way that a relative displacement of the first wafer relative to the second wafer parallel to a main extension plane of the first wafer essentially leads to compressive loading or tensile loading between the structural element and the mating structural element.

Abstract: A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a p-type well. The p-type well applies a positive voltage to the fixed electrode while the n-type well applies a negative voltage to the fixed electrode.

Abstract: A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the MEMS structure over the active circuitry, wherein at least a portion of the MEMS structure spatially overlaps the active circuitry.

Abstract: In a method for manufacturing a micromechanical device having a region for forming an integrated circuit, at first a first layer is produced on a deeper-lying part in the substrate. Subsequently, a membrane layer is produced on the first layer and at least one channel completely penetrating the membrane layer is introduced in the membrane layer. After that, a region of the first layer below the membrane layer is removed to form a cavity. Finally, the channel is sealed and a planar surface is formed.

Abstract: A sensor system includes a sensor device (10) and an integrated circuit (20) for driving the device (10). The device (10) includes a sensor body (1) of a silicon-based material, an upper sealing member (2) of a silicon-based material, and a lower sealing member (3) of a silicon-based material. The upper sealing member (2) and the lower sealing member (3) are joined together to cooperatively house the body (1) therewithin in an airtight manner. The device (10) and the circuit (20) are formed as a stacked body. The body (1) is electrically connected to a wiring pattern (12) of the circuit (20) through a conductive through-path (4) penetrating the upper sealing member (4) and a mounting electrode (5) provided on an outer surface of the upper sealing member (2). The device (10) is connected to an MID substrate (30) through the circuit (20).

Abstract: A rotational micro-electromechanical system (MEMS) having a piezo-resistor sensor is provided. The rotational MEMS device includes a pair of torsion springs that support a stage, four resistors, at least one of the resistors being formed along a center axis of the torsion springs, and electrical signal cables connected to the four resistors, wherein at least one of the torsion springs is formed in a <100> direction on an n-type silicon substrate having a (100) plane, and the resistors formed on the at least one of the torsion springs are formed in a <110> group direction.

Abstract: A method of manufacturing a pressure sensor is provided whereby the pressure sensor includes a joint, a diaphragm, and an adapter disposed between the joint and the diaphragm. The adapter includes an axis portion and a flange projecting in a radial direction from the axis portion. The axis portion is disposed such that one end does not interfere with the joint and the other end is welded to the diaphragm. The diaphragm is welded to the adapter and the welded portion the welded portion is positioned on an inner side of an end face of the joint. The joint is caulked to a peripheral edge of the flange of the adapter.

Abstract: A memory cell for storing a bit having one of two logic states. The memory cell includes a structure comprises a pair of electrically conductive shape memory alloy members separated by a dielectric. An electrical circuit applies a current pulse at a first time to the first electrically conductive member to place the structure is a first position corresponding to one of the two logic states and for applying a current pulse at a different time to change the position of the structure from the first position to a different position, such different position corresponding to a different one of the two logic states. Output circuitry is provided for detecting the logic state of the bit stored by the memory cell, such output circuitry comprising a position sensor for detecting whether the structure is in the first position or in the second position.

Abstract: Structure for capacitive micromachined ultrasonic transducer (CMUT) device or other vibrating membrane device having non-uniform membrane so that membrane mass and stiffness characteristics may be substantially independently adjusted. CMUT having trenched membrane and/or membrane with non-uniform thickness or density. Method for operating transducer or vibrating membrane device. Array of devices at least some of which have non-uniform membrane properties. CMUT comprising substrate, support for membrane, and membrane extending over support to create cavity, membrane having non-uniform membrane thickness resulting from at least one of: thickening on upper surface of the membrane outside of cavity, thickening on lower surface of membrane inside cavity, trench on upper surface of membrane, trench on lower surface of the membrane, and any combination of two or more of these. Method for fabricating CMUT or vibrating membrane device having non-uniform membrane.

Abstract: An accelerator sensor includes a semiconductor substrate having a main front surface and a main rear surface, a first groove portion being formed along a front surface pattern, in the main front surface, a second groove portion being formed along a rear surface pattern, in the main rear surface, a through-hole being formed because of connection between at least parts of the first groove portion and the second groove portion and at least one groove width variation portion being formed in at least one of inner walls of the first groove portion. An offset of the rear surface pattern to the front surface pattern can be inspected easily by existence of the groove width variation portion.

Abstract: A pre-released structure device comprising: at least one first stacking, comprising at least one first layer based on at least one first material, arranged against a second stacking comprising at least one second layer based on at least one second material, at least one closed cavity, formed in the first and/or the second stacking, and arranged between a portion of the first stacking forming the pre-released structure and the second stacking, at least one spacer arranged in the cavity and linking the portion of the first stacking to the second stacking.

Abstract: An interconnection system is provided for a solid-state device. The solid-state that includes, a first layer, multiple devices and a first face. A second layer is bonded to the first face at a bonded face of the second layer that faces the first face. Electrically conductive bonds are between the first and second faces. Conductive paths are on the bonded face of the second layer and connect two or more of the conductive bonds.

Abstract: The resonator comprises two capacitively coupled electrodes. One of the electrodes is made of a p-type doped semiconductor material, whereas the other electrode is made of an n-type doped semiconductor material. The invention also comprises a method of using this specific selection of the doping for enhancing the output signal current from a resonator.

Abstract: An angular rate sensor 100 comprises a first structure 110 which includes a fixed portion 111 having an opening 114, a displacing portion 112 placed in the opening 114, and a connecting portion 113 adapted to connect the fixed portion 111 and the displacing portions 112; a second structure 130 which includes a weighting portion 132 joined to the displacing portion 112, and a pedestal portion 131 arranged to surround the weighting portions 132 and joined to the fixed portion 111, and is laminated in place on the first structure 110. A first body 140 formed by laminating a first metal layer 142 and a first insulating layer 141 thereon is joined to the fixed portion 111 such that the first insulating layer 141 faces the fixed portion 111. A second substrate 150 formed by laminating a second metal layer 152 and a second insulating layer 151 thereon is joined to the pedestal portion 131 such that the second insulating layer 151 faces the pedestal portion 131.

Abstract: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Abstract: An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

Abstract: A method for making a semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, is provided. In accordance with embodiments of the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.

Abstract: A stress-isolated MEMS device (14) includes a platform (26) suspended over a substrate wafer (24). In one embodiment, the platform (26) is suspended by springs (38), but other suspension techniques may also be used. A transducer (28) is formed over the platform (26). The transducer (28) includes immovable portions (50) and movable portions (52). The transducer (28) and platform (26) are sealed within a cavity (62) formed within a cap support (30) between a cap wafer (32) and the substrate wafer (24). A leadframe (22) is affixed to the substrate wafer (24). The cap wafer (32) and other portions of the device (14) become embedded in a package material (20) so that a substantially solid boundary forms between the cap wafer (32) and the package material (20).

Abstract: A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Abstract: A differential pressure sensor has a semiconductor wafer having a top and bottom surface. The top surface of the wafer has a central active area containing piezoresistive elements. These elements are passivated and covered with a layer of silicon dioxide. Each element has a contact terminal associated therewith. The semiconductor wafer has an outer peripheral silicon frame surrounding the active area. The semiconductor wafer is bonded to a glass cover member via an anodic or electrostatic bond by bonding the outer peripheral frame to the periphery of the glass wafer. An inner silicon dioxide frame forms a compression bond with the glass wafer when the glass wafer is bonded to the silicon frame. This compression bond prevents deleterious fluids from entering the active area or destroying the silicon. The above described apparatus is mounted on a header such that through holes in the glass wafer are aligned with the header terminals.

Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.

Abstract: A semiconductor device having a surface MEMS element, includes a semiconductor substrate, and an actuator which is arranged above the semiconductor substrate via a space and has a lower electrode, an upper electrode, and a piezoelectric layer sandwiched between the lower electrode and the upper electrode, at least an entire surface of the piezoelectric layer being substantially flat.

Abstract: A MEMS pixel sensor is provided with a thin-film mechanical device having a mechanical body, with a mechanical state responsive to a proximate environment. A thin-film electronic device converts the mechanical state into electrical signals. A pixel interface supplies power to the electronic device and transceives electrical signals. The sensor is able to operate dynamically, in real-time. For example, if the mechanical device undergoes a sequence of mechanical states at a corresponding plurality of times, the electronic device is able to supply a sequence of electrical signals to the pixel interface that are responsive to the sequence of mechanical states, at the plurality of times. Each MEMS pixel sensor may include a number of mechanical devices, and corresponding electronic devices, to provide redundancy or to measure a broadband response range.

Abstract: An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.

Abstract: An object of the present invention is to enhance the reliability of an MEMS sensor formed on a semiconductor integrated circuit device. To achieve this object, a semiconductor device of the present invention comprises: a semiconductor integrated circuit device; a lower passivation film of silicon nitride, etc. formed on the semiconductor integrated circuit device and having high moisture resistance and high chemical resistance; an MEMS portion formed on the lower passivation film and including a cavity 12; and an upper passivation film 11 formed on the top surface of the MEMS portion such that the MEMS portion is hermetically sealed by the upper and lower passivation films.

Abstract: An MEMS device including a semiconductor substrate having an upper and lower surface, and a support structure disposed at least partially in the semiconductor substrate. The support structure includes a plurality of support members oriented to define a plurality of cells in the semiconductor substrate. A thermally isolated membrane is disposed above the upper surface of the semiconductor substrate and is supported by the support structure. At least one functional component is mounted to the membrane. The plurality of cells are located substantially beneath the at least one functional component.

Abstract: An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

Abstract: A MEMS system including a fixed electrode and a suspended moveable electrode that is controllable over a wide range of motion. In traditional systems where an fixed electrode is positioned under the moveable electrode, the range of motion is limited because the support structure supporting the moveable electrode becomes unstable when the moveable electrode moves too close to the fixed electrode. By repositioning the fixed electrode from being directly underneath the moving electrode, a much wider range of controllable motion is achievable. Wide ranges of controllable motion are particularly important in optical switching applications.

Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.

Abstract: A field-effect transistor used as a sensor for measuring a gas or ion concentration utilizes a surface structure such as rings along with surface profiling, for example elevations of the rings and depressions therebetween, to decrease the surface conductivity between a guard ring and the FET, to thereby increase the concentration rise per unit time of a gas signal and increase the time for a potential on a channel region of the FET to approximate the potential on a guard ring. The rings, which may be arranged around the FET structure, may be defined by a surface material different from the remaining surface material and thus having different surface conductivities. The surface profiling, together with the rings, can be utilized to increase an amount of time that may describe the equalization of the channel region potential to the guard ring potential. The elevations may have a surface conductivity different from, for example smaller than, that of the depressions.

Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.

Abstract: One embodiment of a microelectronic device includes a movable plate including a lower surface, a bump positioned on the lower surface, and an anti-stiction coating positioned only on the bump.