Abstract: Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and body regions are formed by implanting dopants onto the filled trenches. This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

Abstract: A memory includes a semiconductor substrate. Cell transistors are on the substrate. Contact plugs each of which is buried between the adjacent cell transistors and electrically connected to a diffusion layer between the adjacent cell transistors. An interlayer dielectric film buries gaps between the contact plugs. A storage element is provided not above the contact plugs but above the interlayer dielectric film. A sidewall film covers a part of a side surface of the storage element, and is provided to overlap with one of the contact plugs as viewed from above a surface of the semiconductor substrate. A lower electrode is provided between a bottom of the storage element and the interlayer dielectric film and between the sidewall film and one of the contact plugs, and electrically connects the storage element to one of the contact plugs.

Abstract: In a method for manufacturing the functional element, a protective film covering an underlayer, a patterned multilayer film, and a patterned cap layer are formed, and the underlayer is then processed without newly forming a resist. Thereby, an electrode can be formed in steps less than ever before. Since the protective film formed on the patterned multilayer film and the patterned cap layer is used as a mask, the problem of the misregistration can be prevented.

Abstract: A multi-layered bottom electrode for an MTJ device on a silicon nitride substrate is described. It comprises a bilayer of alpha tantalum on ruthenium which in turn lies on a nickel chrome layer over a second tantalum layer.

Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.

Abstract: A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body.

Abstract: A spin Hall effect magnetoresistive memory comprises apparatus of a three terminal magnetoresistive memory cell having an MTJ stack, a functional magnetic layer having a magnetization anti-parallel or parallel coupled with a recording layer magnetization in the MTJ stack, and a SHE-metal base layer. The control circuitry coupled through the bit line and the two select transistors to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two bottom electrodes and to supply a bi-directional spin Hall effect recording current, and accordingly to directly switch the magnetization of the functional magnetic coupling layer and indirectly switching the magnetization of the recording layer through the coupling between the functional magnetic coupling layer and the recording layer.

Abstract: The present invention is directed to a method for fabricating a magnetic tunnel junction (MTJ) memory element. The method comprises the steps of providing a substrate having a contact dielectric layer, a bottom dielectric layer, a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; etching the top electrode layer with a first mask thereon to form a top electrode; etching the MTJ layer stack with the top electrode thereon to form a patterned MTJ; encapsulating the patterned MTJ with a passivation layer; depositing a top dielectric layer on top of the passivation layer and planarizing the same layer; forming a second mask on the top dielectric layer; and etching the bottom electrode layer, the etch stop layer, the passivation layer, and the top dielectric layer with the second mask thereon to form a bottom electrode.

Abstract: Various embodiments may configure a magnetic stack with a magnetically free layer, a reference structure, and a biasing layer. The magnetically free layer and reference structure can each be respectively configured with first and second magnetizations aligned along a first plane while the biasing layer has a third magnetization aligned along a second plane, substantially perpendicular to the first plane.

Abstract: A method for forming a MTJ in a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: The disclosed technology provides an electronic device and a fabrication method thereof, in which an etching margin in formation of a variable resistance element is secured and process difficulty is reduced. An electronic device according to an implementation includes a semiconductor memory, the semiconductor memory including: a variable resistance element including a stack of a first magnetic layer, a tunnel barrier layer and a second magnetic layer; a contact plug coupling a top of the variable resistance element and including a magnetism correcting layer; and a conductive line coupled to the variable resistance element through the contact plug including the magnetism correcting layer.

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Abstract: Provided is a magnetic random access memory to which spin torque magnetization reversal is applied, the magnetic random access memory being thermal stable in a reading operation and also being capable of reducing a current in a wiring operation. A magnetoresistive effect element formed by sequentially stacking a fixed layer, a nonmagnetic barrier layer, and a recording layer is used as a memory element. The recording layer adopts a laminated ferrimagnetic structure.

Abstract: A tunneling magneto-resistor reference unit for sensing a magnetic field includes a first MTJ (magnetic tunneling junction) device and a second MTJ device connected in parallel. The first MTJ device has a first pinned layer having a first pinned magnetization at a pinned direction, and a first free layer having a first free magnetization parallel to the pinned direction in a zero magnetic field. The second MTJ device has a second pinned layer having a second pinned magnetization at the pinned direction, and a second free layer having a second free magnetization anti-parallel to the pinned direction in a zero magnetic field. Major axes of the first and second MTJ devices have an angle of 45 degrees to a direction of an external magnetic field when sensed.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer includes body-centered cubic Co. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: Enhanced Hc and Hk in addition to higher thermal stability up to at least 400° C. are achieved in magnetic devices by adding dusting layers on top and bottom surfaces of a spacer in a synthetic antiferromagnetic (SAF) structure to give a RL1/DL1/spacer/DL2/RL2 reference layer configuration where RL1 and RL2 layers exhibit perpendicular magnetic anisotropy (PMA), the spacer induces antiferromagnetic coupling between RL1 and RL2, and DL1 and DL2 are dusting layers that enhance PMA. Dusting layers are deposited at room temperature to 400° C. RL1 and RL2 layers are selected from laminates such as (Ni/Co)n, L10 alloys, or rare earth-transition metal alloys. The reference layer may be incorporated in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Dusting layers and a similar SAF design may be employed in a free layer for Ku enhancement and to increase the retention time of a memory cell for STT-MRAM designs.

Abstract: A magnetic memory is described. In one aspect, the magnetic memory includes magnetic junctions and at least one semi-spin valve (SSV) line adjacent to the magnetic junctions. Each magnetic junction includes a magnetic free layer. The SSV line(s) include a ferromagnetic layer and a nonmagnetic layer between the ferromagnetic layer and the magnetic junctions. The SSV line(s) are configured to exert a spin accumulation induced torque on at least a portion of the magnetic junctions due to an accumulation of spin polarized current carriers from a current that is substantially in-plane. The free layer is configured to be written using at least the spin accumulation induced torque. In another aspect, the magnetic memory includes magnetic memory cells and at least one spin torque (ST) line that is analogous to the SSV line. Each magnetic memory cell includes magnetic junction(s) analogous to those above and magnetoelectric selection device(s).

Abstract: An improved crosspoint memory array device comprising a plurality of memory cells, each memory cell being disposed at an intersection region of bit and word conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein a back to back Schottky diode is located between each memory cell and one of the said conductive lines, and wherein each conductive line is electrically coupled to at least two thin film transistors (TFTs). The device is substantially produced in BEOL facilities without need of front end semiconductor production facilities, yet can be made with ultra high density and low cost.

Abstract: According to one embodiment, a magnetoresistive element includes first and second magnetic layers and a first nonmagnetic layer. The first magnetic layer has an axis of easy magnetization perpendicular to a film plane, and a variable magnetization. The second magnetic layer has an axis of easy magnetization perpendicular to a film plane, and an invariable magnetization. The first nonmagnetic layer is provided between the first and second magnetic layers. The second magnetic layer includes third and fourth magnetic layers, and a second nonmagnetic layer formed between the third and fourth magnetic layers. The third magnetic layer is in contact with the first nonmagnetic layer and includes Co and at least one of Zr, Nb, Mo, Hf, Ta, and W.

Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic includes a pinned layer, a nonmagnetic spacer layer, a free layer, and package structure(s). The pinned layer has a pinned layer perimeter and a top surface. The nonmagnetic spacer layer is on at least part of the top surface and between the pinned and free layers. The free layer has a free layer perimeter. The package structure(s) are ferromagnetic and encircles at least one of the free layer and the pinned layer. The package structure(s) are ferromagnetically coupled with the pinned layer. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A magnetic memory device may include a free magnetic structure and a reference magnetic structure that are separated from each other by a tunnel barrier. The free magnetic structure may include an exchange-coupling layer, and first and second free layers that are separated from each other by the exchange-coupling layer. The first free layer may be provided between the second free layer and the tunnel barrier. A thickness of the first free layer may be greater than a first maximum anisotropy thickness, being the thickness at which the first free layer has maximum perpendicular anisotropy. A thickness of the second free layer may be smaller than a second maximum anisotropy thickness, being the thickness at which the second free layer has maximum perpendicular anisotropy. A magnetic tunnel junction having two free layers with different thicknesses can enable a magnetic memory device that has increased MR ratio and reduced switching current.

Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-atan(?)) degrees.

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.

Abstract: Provided are a magnetic memory device and a method of fabricating the same. The device may include a cell selection device, a magnetic tunnel junction (MTJ), and a lower electrode connecting them. The lower electrode may include a vertical portion and a horizontal portion laterally extending from a side surface of the vertical portion. In the lower electrode, the vertical portion has a top surface higher than the horizontal portion and has a top surface including at least two parallel sides and other side at an angle thereto. The MTJ may be provided on the vertical portion of the lower electrode.

Abstract: In one embodiment a magnetic memory includes a memory device base and a plurality of memory cells disposed on the memory cell base, where each memory cell includes a layer stack comprising a plurality of magnetic and electrically conductive layers arranged in a stack of layers common to each other memory cell. The magnetic memory further includes an implanted matrix disposed between the memory cells and surrounding each memory cell, where the implanted matrix includes component material of the layer stack of each memory cell inter mixed with implanted species, where the implanted matrix comprises a non-conducting material and a non-magnetic material, wherein each memory cell is electrically and magnetically isolated from each other memory cell.

Abstract: A CoFeB or CoFeNiB magnetic layer wherein the boron content is 25 to 40 atomic % and with a thickness <20 Angstroms is used to achieve high perpendicular magnetic anisotropy and enhanced thermal stability in magnetic devices. A dusting layer made of Co, Ni, Fe or alloy thereof is added to top and bottom surfaces of the CoFeB layer to increase magnetoresistance as well as improve Hc and Hk. Another embodiment includes a non-magnetic metal insertion in the CoFeB free layer. The CoFeB layer with elevated B content may be incorporated as a free layer, dipole layer, or reference layer in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Thermal stability is increased such that substantial Hk is retained after annealing to at least 400° C. for 1 hour. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased.

Abstract: According to one embodiment, a semiconductor storage device is disclosed. The device includes first magnetic layer, second magnetic layer, first nonmagnetic layer between them. The first magnetic layer includes a structure in which first magnetic material film, second magnetic material film, and nonmagnetic material film between the first and second magnetic material films are stacked. The first magnetic material film is nearest to the first nonmagnetic layer in the first magnetic layer. The nonmagnetic material film includes at least one of Ta, Zr, Nb, Mo, Ru, Ti, V, Cr, W, Hf. The second magnetic material film includes stacked materials, including first magnetic material nearest to the first nonmagnetic layer among the stacked materials, and second magnetic material which is same magnetic material as the first magnetic material and has smaller thickness than the first magnetic material.

Abstract: A planarization process may planarize a media disk that has data trenches between data features and larger servo trenches between servo features. A filler material layer is deposited on the media disk and provides step coverage of the trenches. The filler material has data recesses over the data trenches and servo recesses over the servo trenches that must be removed to produce a planar media surface. A first planarization process is used to remove the data recesses and a second planarization process is used to remove the servo recesses.

Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode.

Abstract: According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes a free magnetic layer structure having a magnetization orientation that is variable, and a spin orbit coupling structure including a tunnel barrier including a metal oxide, and a metal layer, wherein the tunnel barrier and the metal layer are arranged one over the other, wherein the spin orbit coupling structure is adapted to generate, in response to an applied current, a field to interact with the free magnetic layer structure for switching the magnetization orientation of the free magnetic layer structure. According to further embodiments of the present invention, a method of forming a magnetoresistive device is also provided.

Abstract: Orthogonal spin-torque bit cells whose spin torques from a perpendicular polarizer and an in-plane magnetized reference layer are constructively or destructively combined. An orthogonal spin-torque bit cell includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque; an in-plane magnetized free layer and a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque combine and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction. The first spin-torque and second spin-torque can combine constructively to lower a switching current, increase a switching speed, and/or torque decrease an operating energy of the orthogonal spin-torque bit cell.

Abstract: A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell.

Abstract: A method and apparatus for coupling a MEMS device to a substrate is disclosed. The method includes providing a substrate with a conductor disposed over the substrate, adhering the MEMS device to the substrate, wherein a first elastomer adheres the MEMS device to the substrate. The MEMS device is electrically connected to the conductor using a wire bond.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

Abstract: The disclosed technology generally relates to methods of fabricating magnetic memory devices, and more particularly to methods of forming a magnetic tunnel junction (MTJ) stack. In one aspect, a method of forming the MTJ includes providing an MTJ material stack comprising a ferromagnetic material and forming thereon a protective mask layer to cover an active area of the MTJ material stack. The method additionally includes incorporating a glass-forming element into exposed portions of the ferromagnetic material. The method additionally includes at least partially amorphizing the exposed portions of the ferromagnetic material, wherein at least partially amorphizing transforms the exposed portions of the ferromagnetic material into an electrical insulator.

Abstract: A ring-shaped magnetoresistive memory device includes a ring-shaped magnetoresistive memory cell, a first conductor, and a second conductor. The first conductor is positioned on a first surface of the ring-shaped magnetoresistive memory cell for generating a first magnetic field pulse. The second conductor is positioned on a second surface of the ring-shaped magnetoresistive memory cell for generating a second magnetic field pulse. The first surface is opposite to the second surface. An extension direction of the first conductor is perpendicular to an extension direction of the second conductor. A time delay is between the first magnetic field pulse and the second magnetic field pulse.

Abstract: A magnetoresistive element according to an embodiment includes: a first to third ferromagnetic layers, and a first nonmagnetic layer, the first and second ferromagnetic layers each having an axis of easy magnetization in a direction perpendicular to a film plane, the third ferromagnetic layer including a plurality of ferromagnetic oscillators generating rotating magnetic fields of different oscillation frequencies from one another. Spin-polarized electrons are injected into the first ferromagnetic layer and induce precession movements in the plurality of ferromagnetic oscillators of the third ferromagnetic layer by flowing a current between the first and third ferromagnetic layers, the rotating magnetic fields are generated by the precession movements and are applied to the first ferromagnetic layer, and at least one of the rotating magnetic fields assists a magnetization switching in the first ferromagnetic layer.

Abstract: A detector for detecting an occurrence of a current strength of interest of a current of a signal to be sensed includes a magnetoresistive structure and a detection unit. The magnetoresistive structure varies a resistance depending on a magnetic field caused by the current of the signal to be sensed. Further, the detection unit generates and provides a current detection signal indicating an occurrence of the current strength of interest based on a detected magnitude of the varying resistance of the magnetoresistive structure.

Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment of the present invention as applied to a memory cell comprises a top electrode layer, an upper magnetic layer, a barrier layer, a lower magnetic layer and a bottom electrode layer in a pillar formed on a landing pad; and a sleeve of dielectric material generally surrounding sidewalls of at least the barrier layer and the lower magnetic layer and partially surrounding the bottom electrode layer. The bottom electrode layer includes a ledge that extends under the sleeve of dielectric material and separates the sleeve of dielectric material from the landing pad under the bottom electrode layer.

Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

Abstract: A device including at least two spintronic devices and a method of making the same. A magnetic connector extends between the two spintronic devices to conduct a magnetization between the two. The magnetic connector may further be disposed to conduct current to switch a magnetization of one of the two spintronic devices.

Abstract: One embodiment includes a metal layer including first and second metal portions; a ferromagnetic layer including a first ferromagnetic portion that directly contacts the first metal portion and a second ferromagnetic portion that directly contacts the second metal portion; and a first metal non-magnetic interconnect coupling the first ferromagnetic portion to the second ferromagnetic portion. The spin interconnect conveys spin polarized current suitable for spin logic circuits. The interconnect may be included in a current repeater such as an inverter or buffer. The interconnect may perform regeneration of spin signals. Some embodiments extend spin interconnects into three dimensions (e.g., vertically across layers of a device) using vertical non-magnetic metal interconnects.

Abstract: A magnetic memory device may include a free magnetic structure, a tunnel barrier layer, and a pinned magnetic structure wherein the tunnel barrier layer is between the free magnetic structure and the pinned magnetic structure. The pinned magnetic structure may include first and second pinned layers and an exchange coupling layer between the first and second pinned layers. The second pinned layer may be between the first pinned layer and the tunnel barrier layer, and the second pinned layer may include a junction magnetic layer and a buffer layer between the junction magnetic layer and the exchange coupling layer. The buffer layer may include a layer of a material including a non-magnetic metallic element. Related devices, structures, and methods are also discussed.

Abstract: A hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining free layer. The HOCL has a lower interface oxide layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during an anneal to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the free layer.

Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.

Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a magnetoresistive element provided on the semiconductor substrate and includes a storage layer, a tunnel barrier layer, and a reference layer which are stacked, the reference layer having a magnetization direction perpendicular to a principal surface of the semiconductor substrate, and a magnetic field generation section provided away from the magnetoresistive element and configured to generate a magnetic field perpendicular to the principal surface of the semiconductor substrate to reduce a magnetic field from the reference layer which is applied to the storage layer.