Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a plurality of magnetic layers including a nonmagnetic spacer layer. The magnetic junction also includes at least one diffusionless transformation layer. The magnetic junction is configured to be switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.

Abstract: A magnetoresistive element includes a first magnetic layer having an axis of magnetization perpendicular to the film surface and a fixed magnetization orientation; a second magnetic layer having an axis of magnetization perpendicular to the film surface and a changeable magnetization orientation; a first nonmagnetic layer arranged between the first and second magnetic layers; and a third magnetic layer having an axis of magnetization perpendicular to the film surface and a fixed magnetization orientation opposite that of the first magnetic layer. The first magnetic layer has a first magnetic material film in contact with the first nonmagnetic layer, a nonmagnetic material film in contact with the first magnetic material film, and a second magnetic material film containing Co100-xWx (0<x<40 at %) and in contact with the nonmagnetic material film. As current flows via the nonmagnetic layer, the magnetization orientation of the second magnetic layer changes.

Abstract: A hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining free layer. The HOCL has a lower interface oxide layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during an anneal to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the free layer.

Abstract: A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.

Abstract: A storage element includes: a storage layer which has magnetization perpendicular to a film surface, the direction of the magnetization being changed in accordance with information; a magnetization fixed layer which has magnetization perpendicular to a film surface used as a base of information stored in the storage layer; and an insulating layer of a nonmagnetic substance provided between the storage layer and the magnetization fixed layer. In the storage element described above, the magnetization of the storage layer is reversed using a spin torque magnetization reversal generated by a current flowing in a lamination direction of a layer structure including the storage layer, the insulating layer, and the magnetization fixed layer to store information, and the storage layer has a laminate structure including a magnetic layer and a conductive oxide.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a first pinned layer having a first pinned layer magnetization, a first nonmagnetic spacer layer, and a free layer having an easy axis. The first nonmagnetic spacer layer is between the first pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction and such that the free layer employs precessional switching.

Abstract: A magnetic memory device may include a lower electrode on a substrate, a memory element on the lower electrode, an upper electrode on the memory element, and a protection spacer enclosing a portion of a side surface of the lower electrode and protruding laterally from the side surface of the lower electrode. The protection spacer may have a bottom surface that is positioned at a level higher than that of a bottom surface of the lower electrode.

Abstract: High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.

Abstract: Provided are a magnetoresistance effect element with a stable magnetization direction perpendicular to film plane and a controlled magnetoresistance ratio, in which writing can be performed by magnetic domain wall motion, and a magnetic memory including the magnetoresistance effect element. The magnetoresistance ratio is controlled by forming a ferromagnetic layer of the magnetoresistance effect element from a ferromagnetic material including at least one type of 3d transition metal or a Heusler alloy. The magnetization direction is changed from a direction in the film plane to a direction perpendicular to the film plane by controlling the film thickness of the ferromagnetic layer on an atomic layer level.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a reference layer, a nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. A portion of the magnetic junction includes at least one magnetic substructure. The magnetic substructure includes at least one Fe layer and at least one nonmagnetic insertion layer. The at least one Fe layer shares at least one interface with the at least one nonmagnetic insertion layer. Each of the at least one nonmagnetic insertion layer consists of at least one of W, I, Hf, Bi, Zn, Mo, Ag, Cd, Os and In.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a magnetoresistive element provided on the substrate. The magnetoresistive element includes a first magnetic layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer or the second magnetic layer includes a first region, second region, and third region whose ratios of crystalline portion are higher in order closer to the tunneling barrier.

Abstract: A method and apparatus provide a magnetic memory including magnetic junctions on a substrate. The apparatus include an RIE chamber and an ion milling chamber. The chambers are coupled such that the magnetic memory is movable between the chambers without exposing the magnetic memory to ambient. The method provides magnetic junction layers and a hard mask layer on the magnetic junction layers. A hard mask is formed from the hard mask layer using an RIE. The magnetic junction layers are ion milled after the RIE and without exposing the magnetic memory to an ambient after the RIE. The ion milling defines at least part of each magnetic junction. A magnetic junction may be provided. The magnetic junction includes pinned, nonmagnetic spacer, and free layers. The free layer has a width of not more than twenty nanometers and is switchable when a write current is passed through the magnetic junction.

Abstract: A ferromagnetic/ferroelectric heterostructure thin film is disclosed that exhibits significant magneto-electric coupling. The ferromagnetic/ferroelectric heterostructure thin film includes a) a base layer of silicon substrate, b) a first copper layer deposited on the silicon substrate, c) a first iron layer deposited on the copper layer, d) first aluminum layer deposited on the first iron layer, e) a polymer layer exhibiting ferroelectric properties deposited on the first aluminum layer, f) a second aluminum layer deposited on the polymer layer; g) a second iron layer deposited on the second aluminum layer, and h) a second copper layer deposited on the second iron layer.

Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

Abstract: A thin film magnetoresistive sensor for detecting a magnetic field components perpendicular and parallel to the plane of the sensor substrate is disclosed. The sensing element comprises a free layer, a reference layer, and a spacer layer between the free layer and the reference layer. The easy-axis magnetization inherent to the material of the free layer is arranged to be perpendicular to the plane of the sensor substrate. The magnetization direction of the reference layer is confined to a direction parallel to the substrate plane. The reference layer consists of a ferromagnetic layer exchange coupled to an antiferromagnetic layer, or consists of a ferromagnetic layer having a higher coercive force than that of the free layer. The spacer layer is composed of an insulating material or a conductive material. The magnetoresistive sensor further includes an array of aforementioned sensing elements coupled to an electronic device to provide three-axis sensing.

Abstract: A magnetic electronic device comprises a substrate, a buffer layer, a first CoFeB layer, a first metal oxidation layer and a capping layer. The buffer layer is disposed above the substrate. The first CoFeB layer is disposed above the buffer layer. The first metal oxidation layer is disposed above the first CoFeB layer. The capping layer is disposed above the first metal oxidation layer and covers the first metal oxidation layer. A manufacturing method of the magnetic electronic device is also disclosed.

Abstract: A magnetoresistance element includes a first magnetic layer having first and second surfaces, a second magnetic layer, an intermediate layer provided between the first surface and the second magnetic layer, a first layer provided on the second surface, containing B and at least one element selected from Hf, Al, Mg, and Ti and having third and fourth surfaces, a second layer provided on the fourth surface and containing B and at least one element selected from Hf, Al, and Mg, and an insulating layer provided on a sidewall of the intermediate layer and containing at least one element selected from the Hf, Al, and Mg contained in the second layer.

Abstract: A device for modulating terahertz waves includes a metal layer (703) including a continuous metal portion (705) and island metal portions (707). The metal portions (705, 707) are separated by apertures (709). The device further includes a semiconductor layer (715) affixed to a bottom surface of the metal layer (703). The semiconductor layer (715) includes carrier regions (717) located below the apertures (709). The transmission of terahertz waves through the apertures (709) is modulated by changing a voltage applied across the aperture via voltage source (715). By injecting free carriers into carrier regions (717) due to a change of the voltage an extraordinary terahertz transmission effect of the metal layer (703) can be switched off. A small increase in the free-carrier absorption is significantly enhanced by the Fabry-Perot resonance, resulting in a substantial decrease in transmission.

Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

Abstract: According to one embodiment, a magnetic memory includes a cell transistor including a first source/drain diffusion layer and a second source/drain diffusion layer, a first contact on the first source/drain diffusion layer, a memory element on the first contact, and a second contact on the second source/drain diffusion layer, the second contact including a first plug on the second source/drain diffusion layer, and a second plug on the first plug.

Abstract: A vertical Hall Effect element includes one or more of: a low voltage P-well region disposed at a position between pickups of the vertical Hall Effect element, Light-N regions disposed under the pickups, a pre-epi implant region, or two epi regions to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: A sensor device includes a substrate, an IC chip, a sensor element, bonding wires, and a lid. The substrate includes a plurality of metal posts which are disposed so as to be electrically independent of each other and an insulator which is filled in a gap between faces different from first faces and second faces of the plurality of metal posts and integrally fixes the plurality of metal posts. The IC chip has electrode pads on an active face and is fixed to a first metal post. The sensor element has vibrating portions and is supported by the IC chip by bonding a supporting portion to the active face of the IC chip. The bonding wires electrically connect the electrode pads with second metal posts. The lid is disposed so as to cover the IC chip and the sensor element.

Abstract: A magnetoresistive element according to an embodiment includes: a base layer; a first magnetic layer formed on the base layer, and including a first magnetic film having an axis of easy magnetization in a direction perpendicular to a film plane, the first magnetic film including MnxGa100-x (45?x<64 atomic %); a first nonmagnetic layer formed on the first magnetic layer; and a second magnetic layer formed on the first nonmagnetic layer, and including a second magnetic film having an axis of easy magnetization in a direction perpendicular to a film plane, the second magnetic film including MnyGa100-y (45?y<64 atomic %). The first and second magnetic layers include different Mn composition rates from each other, a magnetization direction of the first magnetic layer is changeable by a current flowing between the first magnetic layer and the second magnetic layer via the first nonmagnetic layer.

Abstract: A synthetic antiferromagnet serving as a reference layer for a magnetic tunnel junction is a laminate with a plurality of “x+1” magnetic sub-layers and “x” non-magnetic spacers arranged in an alternating fashion, with a magnetic sub-layer at the top and bottom of the laminated stack. Each spacer has a top and bottom surfaces that interface with adjoining magnetic sub-layers generating antiferromagnetic coupling between the adjoining sub-layers. Perpendicular magnetic anisotropy is induced in each magnetic sub-layer through an interface with a spacer. Thus the dipole field exerted on a free layer is substantially reduced compared with that produced by a conventional synthetic antiferromagnetic reference layer. Magnetic sub-layers are preferably Co while Ru, Rh, or Ir may serve as non-magnetic spacers.

Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

Abstract: A magnetic memory element includes a memory layer having magnetic anisotropy on the film surface thereof in the perpendicular direction and in which the magnetization direction is variable, a reference layer having magnetic anisotropy on the film surface thereof in the perpendicular direction and in which the magnetization direction is not variable, and a tunnel barrier layer which is interposed between the memory layer and the reference layer. The memory layer is made of an alloy including cobalt (Co) andiron (Fe). A plurality of oxygen atoms are present on both interfaces of the memory layer.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

Abstract: A transducer is disclosed that includes a multiply resonant composite, the composite having a resonator bar of a piezoelectric single crystal configured in a d32 transverse length-extensional resonance mode having a crystallographic orientation set such that the thickness axis is in the <110> family and resonance direction is the <001> family.

Abstract: A thermoelectric conversion element includes: a magnetic layer; a conductive film formed on the magnetic layer and configured to generate an electromotive force in an in-plane direction by inverse spin-Hall effect; and two terminal sections formed to contact with the conductive film at two portions whose potentials are different to each other by the electromotive force. Each of the two terminal sections contacts with the conductive film in a continuous or discrete contact surface. A longitudinal direction of a minimum rectangle which encompasses the continuous or discrete contact surface of each of the two terminal sections intersects with the direction of the electromotive force.

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

Abstract: A microelectromechanical system device including anchors and mass is provided. Electrical interconnections are formed on the mass by using a insulation layer of mass, an electrical insulation trench and conductive through hole. The electrical interconnections replace the cross-line structure without adding additional processing steps, thereby reducing the use of the conductive layer and the electrical insulation layer. A method for fabricating the microelectromechanical system device is also provided.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer.

Abstract: A memory storage device including a lower electrode formed to be separate for each of a plurality of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer. The memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer. The memory storage layer and the upper electrode are formed in common to plural memory cells.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and in regard to the insulating layer and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film.

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

Abstract: A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer.

Abstract: According to one embodiment, a storage device includes first electrodes, second electrodes, a resistance change layer provided between the first electrodes and the second electrodes, and ion metal particles that are formed in an island form between the first electrodes and the resistance change layer and that contain a metal movable inside the resistance change layer. The first electrodes and the second electrodes are formed of a material which is more unlikely to be ionized as compared to the metal, and the first electrodes are in contact with the resistance change layer in an area around the ion metal particles.

Abstract: A TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, COBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. One embodiment is represented by (NBC/BC)n where n?2. A second embodiment is represented by (NBC/BC)n/NBC where n?1. In every embodiment, a NBC layer contacts the tunnel barrier and NBC layers each with a thickness from 2 to 8 Angstroms are formed in alternating fashion with one or more BC layers each 10 to 80 Angstroms thick. Total free layer thickness is <100 Angstroms. The free layer configuration described herein enables a significant noise reduction (SNR enhancement) while realizing a high TMR ratio, low magnetostriction, low RA, and low Hc values.

Abstract: A magnetoresistive effect element uses a perpendicularly magnetized material and has a high TMR ratio. Intermediate layers composed of an element metal having a melting point of 1600° C. or an alloy containing the metal on an outside of a structure consisting of a CoFeB layer, an MgO barrier layer, and a CoFeB layer. By inserting the intermediate layers, crystallization of the CoFeB layer during annealing is advanced from an MgO (001) crystal side, so that the CoFeB layer has a crystalline orientation in bcc (001).

Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area.

Abstract: Spin transfer torque memory elements and memory devices are provided. In one embodiment, the spin transfer torque memory element includes a first portion including CoFeB, a second portion including CoFeB, an intermediate portion interposed between the first and second portions, a third portion adjoining the second portion opposite the intermediate portion, and a fourth portion adjoining the third portion opposite the second portion. The intermediate portion includes MgO. The third portion includes at least one of Ag, Au, Cr, Cu, Hf, Mo, Nb, Os, Re, Ru, Ta, W, and Zr. The fourth portion includes at least one alloy of Co, Fe, Pd, and Pt.

Abstract: Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.

Abstract: Voltage controlled magneto-electric tunnel junctions and memory devices are described which provide efficient high speed voltage switching of non-volatile magnetic devices (MeRAM) at high cell densities. A multi-bit-per-cell (MBPC) MeRAM is described which requires only a single transistor to write and read two data bits from the one MBPC MeRAM cell.

Abstract: A nanoscale tunnel magneto-resistance (TMR) sensor comprising an in-plane-magnetized reference layer and a free layer comprising interfacial perpendicular anisotropy, wherein the free layer comprises a sensing layer for sensing resistance as a function of applied magnetic field and is tunable to vary the direction of the sensing layer magnetization to be in-plane, canted, or out-of-plane.

Abstract: A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract: Magnetic memory cells include a magnetic tunnel junction and a first electrode, which is electrically coupled to the magnetic tunnel junction by a first conductive structure. This conductive structure includes a blocking layer and a seed layer, which extends between the blocking layer and the magnetic tunnel junction. The blocking layer is formed as an amorphous metal compound. In some of the embodiments, the blocking layer is a thermally treated layer and an amorphous state of the blocking layer is maintained during and post thermal treatment.