Abstract: A semiconductor device includes a semiconductor layer (2) and a dielectric stack (3) on the semiconductor layer. A plurality of etchant openings (24-1,2 . . . ) are formed through the dielectric stack (3) for passage of etchant for etching a plurality of overlapping sub-cavities (4-1,2 . . . ), respectively. The etchant is introduced through the etchant openings to etch a composite cavity (4) in the semiconductor layer by simultaneously etching the plurality of overlapping sub-cavities into the semiconductor layer.

Abstract: An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material.

Abstract: Disclosed is a method for detecting a mechanical fault state of a semiconductor arrangement, using a temperature profile.

Abstract: A power supply device is disclosed that is able to satisfy the power requirements of a device in service and has high efficiency. The power supply device includes a first power supply; a voltage step-up unit that steps up an output voltage of the first power supply; a voltage step-down unit that steps down an output voltage of the voltage step-up unit; and a load that is driven to operate by an output voltage of the voltage step-down unit. The voltage step-up unit steps up the output voltage of the first power supply to a lower limit of an operating voltage of the voltage step-down unit.

Abstract: A microfluidic system.

Abstract: Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

Abstract: A semiconductor device includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.

Abstract: A chip-type semiconductor ceramic electronic component including a ceramic body made of a semiconductor ceramic, first external electrodes formed on opposite end surfaces of the ceramic body, and second external electrodes extending to cover surfaces of the first external electrodes and part of side surfaces of the ceramic body. A curvature radius of a corner portion of the ceramic body is R (?m), a maximum thickness of a layer of the first external electrode layer, which is in contact with the ceramic body, measured from the end surface of the ceramic body is y (?m), and a minimum thickness of a layer of the second external electrode, which is in contact with the side surface of the ceramic body, measured from an apex of the corner portion of the ceramic body is x (?m), and 20?R?50, ?0.4 x+0.6?y?0.4 is satisfied when 0.5?x?1.1, and ?0.0076 x+0.16836?y?0.4 is satisfied when 1.1?x?9.0.

Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.

Abstract: A detector for detecting electromagnetic waves, the detector having an antenna for receiving the electromagnetic waves, a semiconductor element, wherein a termination section of the semiconductor element establishes a termination resistor of the antenna, wherein the termination section is provided for heating a temperature-sensitive part of the semiconductor element, wherein the semiconductor element comprises a temperature-dependent characteristic that is dependent from the temperature of the temperature sensitive part and a measurement unit for measuring the temperature-dependent characteristic of the semiconductor element.

Abstract: A substrate for an LED submount may include a plurality of placement locations on its substrate top side and a plurality of pairs each composed of an electrical anode connection and an electrical cathode connection, wherein the anode connections are arranged on a first side section of the substrate top side and the cathode connections are arranged on a second side section of the substrate top side, having at least one connection dividing conductor track leading from one placement location past at least two other placement locations to an electrical connection, wherein the connection dividing conductor track leads past the at least two other placement locations on the inside.

Abstract: A temperature sensor structure for a semiconductor device. One embodiment provides a semiconductor substrate including the semiconductor device. A dissipation region of the semiconductor device is adjacent to a main surface of the semiconductor substrate. A first layer arrangement is disposed on the main surface of the semiconductor substrate adjacent to the dissipation region of the semiconductor device. A second layer arrangement is disposed on the first layer arrangement with an insulation layer for galvanic separation therebetween. The first and second layer arrangements and the insulation layer form a layer structure on the main surface above the dissipation region. A circuit element is disposed in the second layer arrangement, the circuit element having a temperature-dependent characteristic and being coupled thermally to the dissipation region.

Abstract: Embodiments of the invention include a temperature sensor method for providing an output voltage response that is linear to the temperature of the integrated circuit to which the temperature sensor belongs and/or the integrated circuit die on which the temperature sensor resides. The output voltage of the temperature sensor has an adjustable gain component and an adjustable voltage offset component that both are adjustable independently based on circuit parameters. The inventive temperature sensor includes an offset circuit that diverts a portion of current from the scaled PTAT current before the current is sourced through the output resistor. The offset circuit includes a bandgap circuit arrangement, a voltage to current converter arrangement, and a current mirror arrangement that are configured to provide a voltage offset adjustable based on independent circuit parameters such as resistor value ratios and transistor device scaling ratios.

Abstract: An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.

Abstract: A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation.

Abstract: A sensor for selectively determining the presence and measuring the amount of hydrogen in the vicinity of the sensor. The sensor comprises a MEMS device coated with a nanostructured thin film of indium oxide doped tin oxide with an over layer of nanostructured barium cerate with platinum catalyst nanoparticles. Initial exposure to a UV light source, at room temperature, causes burning of organic residues present on the sensor surface and provides a clean surface for sensing hydrogen at room temperature. A giant room temperature hydrogen sensitivity is observed after making the UV source off. The hydrogen sensor of the invention can be usefully employed for the detection of hydrogen in an environment susceptible to the incursion or generation of hydrogen and may be conveniently used at room temperature.

Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.

Abstract: An integrated circuit having a resistance temperature sensor composed of a first resistance structure formed within a trench, and a second resistance structure formed within a mesa region is disclosed. This embodiment makes it possible to suppress or reduce manufacturing-technological fluctuations of the width of the trenches to a resistance value of the resistance temperature sensor.

Abstract: In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.

Abstract: A heater pattern is arranged on at least one substrate among substrates configuring a package, and a temperature in the package is controlled by controlling a quantity of electricity carried to the heater pattern corresponding to the ambient temperature of a sensor chip in the package.

Abstract: A substrate including a sensor unit, wherein the sensor unit includes a coil wound at least once arranged on the surface of the sensor or embedded within and near the surface thereof. With such an arrangement, an electric current that corresponds to information with respect to the substrate flows through the coil.

Abstract: A thin-film semiconductor device comprises a temperature sensor formed of a thin-film semiconductor and sensing a temperature as current, and a current-voltage converter formed of a thin-film semiconductor and having temperature dependence in which its current-voltage characteristic is different from that of the temperature sensor. A temperature sensed by the temperature sensor is converted to a voltage by the current-voltage converter.

Abstract: A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.

Abstract: Provided are a thermistor with 3 terminals, a thermistor-transistor including the thermistor, a circuit for controlling heat of a power transistor using the thermistor-transistor, and a power system including the circuit. The circuit includes: a thermistor-transistor which comprises a thermistor having a resistance decreasing with an increase in temperature and a control transistor connected to the thermistor; and at least one power transistor which is connected to a driving device to control a supply of power to the driving device, wherein the thermistor-transistor is adhered to one of a surface and a heat-emitting part of the at least one power transistor and is connected to one of a base, a gate, a collector, and a drain of the at least one power transistor to decrease or block a current flowing in the at least one power transistor when the temperature of the at least one power transistor rises, so as to prevent the power transistor from heating up.

Abstract: A temperature sensor with a bandgap circuit is provided. The bandgap circuit is covered by a buffer layer of photoresist. The device is packaged in a housing. By providing the buffer layer, mechanical stress in the bandgap circuit, as it is e.g. caused by different thermal expansion coefficients of the packaging and the chip, can be reduced. This improves the accuracy of the device.

Abstract: A thermistor device having a high-speed response to temperature and a large ON/OFF ratio at the operating temperature. The thermistor device comprises a first layer of a first material having a positive temperature coefficient of resistance and a second layer of a second material having a semiconductivity and formed directly on the first layer. As the first material changes from conductive to a semiconductive or an insulative at or near the transition temperature TM-I, the interface between the first and second layer changes to a pn junction.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract: Methods and apparatuses to measure temperatures of integrated circuits are disclosed. New circuit arrangements for measuring temperature using various types of integrated circuit sensor elements are discussed. Embodiments comprise methods and apparatuses arranged to measure temperature based upon current leakage rates of different integrated circuit sensor elements. The methods and apparatuses generally involve using a pulse module to generate a charge for the integrated circuit elements. In these method and apparatus embodiments, one or more elements form a decay module to sense when the voltage decays to a threshold value. The method and apparatus embodiments may also have a module to calculate or infer a temperature from the rate of the voltage decay.

Abstract: A method for forming a flow sensor having self-supported heat-carrying elements is disclosed. Self-supported heat-carrying elements are capable of operating with higher thermal efficiency, enabling lower power consumption and higher sensitivity, due to a lack of heat loss into a supporting membrane. Self-supported heat-carrying elements facilitate wider operating temperature range and compatibility with harsh media.

Abstract: Provided are an electronic cooling device and a fabrication method thereof. The method may include forming an insulating layer on a semiconductor substrate, forming first and second silicide layers on the insulating layer, forming separate paired p-type and n-type semiconductors on each of the first and second silicide layers, forming a first interlayer dielectric (ILD) layer on the p-type and n-type semiconductors, exposing top surfaces of the n-type and p-type semiconductors, forming a third silicide layer on one semiconductor on each of the first and second silicide layers, forming a second ILD layer on the third silicide layer, and etching the second and first ILD layers to form contact holes exposing top surfaces of the first and second silicide layers.

Abstract: A temperature compensated voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference. The transistor widths of two P-MOS transistors are adjusted to minimize voltage variation over a temperature range.

Abstract: A solid-state imaging device includes first pixels and second pixels. Each of the first pixels and the second pixels includes a p-type diffusion layer formed in a semiconductor substrate and an n-type diffusion layer formed on the p-type diffusion layer. A first p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the first pixels. A second p-type implantation layer having a lower impurity concentration than the first p-type implantation layer or no p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the second pixels.

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract: The invention relates to MEMS devices. In one embodiment, a micro-electromechanical system (MEMS) device comprises a resonator element comprising a semiconducting material, and at least one trench formed in the resonator element and filled with a material comprising oxide. Further embodiments comprise additional devices, systems and methods.

Abstract: Embodiments of systems and methods for estimating channel temperatures of a field effect transistor structure are disclosed. One method embodiment, among others, comprises receiving geometrical values corresponding to a field effect transistor (FET) structure, and associating the geometrical values of the FET structure to elliptical cylinder and prolate spheroidal coordinates to provide a closed form expression.

Abstract: The present invention discloses a gas pendulum style level posture sensing chip and its manufacturing method and a level posture sensor. The gas pendulum style level posture sensing chip includes: a semiconductor substrate; two sets of arm thermosensitive fuses formed on the surface of the semiconductor substrate, each set of the thermosensitive fuses including two thermosensitive fuses in parallel to each other, the two sets of thermosensitive fuses being vertical to each other; electrodes formed at the two ends of the thermosensitive fuses. For the level posture sensing chip and sensor provided by the present invention, the parallelism and verticality of the thermosensitive fuses is high in precision such that the more accurate measurement can be implemented.

Abstract: Getter structure comprising a substrate and at least one getter material-based layer mechanically connected to the substrate by means of at least one support, in which the surface of the support in contact with the substrate is smaller than the surface of a first face of the getter material layer, in which said first face is in contact with the support, and a second face of the getter material layer, opposite said first face is at least partially exposed.

Abstract: A microelectronic package, a method of forming the package and a system incorporating the package. The package includes a substrate; a die bonded to the substrate; and a thermal sensor connected to the substrate.

Abstract: The Lateral-Moving Micromachined Thermal Bimorph provides the capability of achieving in-plane thermally-induced motion on a microchip, as opposed to the much more common out-of-plane, or vertical, motion seen in many devices. The present invention employs a novel fabrication process to allow the fabrication of a lateral bimorph in a fundamentally planar set of processes. In addition, the invention incorporates special design features that allow the bimorph to maintain material interfaces.

Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.

Abstract: There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured to determine a temperature of the first semiconductor die and to provide a reset protection signal to the first semiconductor die when the temperature of the first semiconductor die is substantially equal to a preset temperature so as to protect the first semiconductor die from thermal runaway. The reset protection signal can cause the first semiconductor die to be in a sleep mode or a reset state.

Abstract: A pressure sensor includes a base substrate silicon fusion bonded to a cap substrate with a chamber disposed between the base substrate and the cap substrate. Each of the base substrate and the cap substrate include silicon. The base substrate includes walls defining a cavity and a diaphragm portion positioned over the cavity, wherein the cavity is open to an environment to be sensed. The chamber is hermetically sealed from the environment.

Abstract: A sensing apparatus includes a holding substrate, a sensing chip and a protection layer. The sensing chip is mounted on the holding substrate and electrically connected to the holding substrate. The sensing chip has a sensing region and a non-sensing region other than the sensing region. The sensing region senses image data of an object and thus generates a sensed signal outputted to the holding substrate. The protection layer is formed by a packaging material and is simultaneously processed and integrally formed to cover the sensing region and the non-sensing region of the sensing chip and the holding substrate. The protection layer has an exposed upper surface, which has one portion serving as a sensing surface in contact with the object. The entire protection layer is composed of the same material.

Abstract: Solid-state memories are disclosed that are comprised of cross-point memory arrays. The cross-point memory arrays include a first plurality of electrically conductive lines and a second plurality of electrically conductive lines that cross over the first plurality of electrically conductive lines. The memory arrays also include a plurality of memory cells located between the first and second conductive lines. The memory cells are formed from a metallic material, such as FeRh, having the characteristic of a first order phase transition due to a change in temperature. The first order phase transition causes a corresponding change in resistivity of the metallic material.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ?? A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: The present invention provides a non-volatile switching element having a novel structure that operates at a high speed and enables high integration, and an integrated circuit that includes such non-volatile switching elements. The switching element includes: a switching film formed on a substrate, made of a material causing a 10 times or greater change in electric resistance with a temperature change within a range of ±80 K from a predetermined temperature; a Peltier element causing the switching film to have the temperature change; a heat conducting/electric insulating film provided between the switching film and the Peltier element, to conduct heat from the Peltier element; and a pair of electrodes connected to the switching film.

Abstract: Microstructures can be formed as patterned layers on a substrate and then erecting the microstructures out of the plane of the substrate. The microstructures may be formed over circuits in the substrate. In some embodiments the patterned layer provides resiliently-flexible members such as cantilevers or springs that can be buckled to permit an edge defined by the patterned layer to engage a surface of the substrate. In some embodiments deformation of the resiliently-flexible members results the edge being forced against the substrate. Such microstructures may be applied in a wide range of applications including supporting optical elements, sensors, antennas or the like out of the plane of a substrate. Examples of accelerometer structures are described.

Abstract: A sensor device for sensing air flow speed at the exterior of an aircraft, comprising a substrate having an upper side on which is mounted a diaphragm over an aperture or recess in the substrate, the diaphragm being thermally and electrically insulative, and mounting on its upper surface a heating element comprising a layer of resistive material, and wherein electrical connections to the heating element are buried in the diaphragm and/or the substrate, and provide electrical terminals at the lower side of the substrate. The heating element is exposed to the environment, but the remaining electrical parts of the device are not exposed.