Abstract: An electronic component has a semiconductor chip with chip contacts. The chip contacts are mechanically fixed on a wiring structure and electrically connected to the wiring structure. The wiring structure is formed as a region of a structured metal plate or as a region of a structured metal layer of a metal-clad base plate. Ideally, a panel having a number of component positions is provided for receiving a number of such an electronic component.

Abstract: A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad.

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.

Abstract: A semiconductor integrated circuit device is formed by a semiconductor substrate having an SiGe layer and a first Si layer epitaxially grown thereover, and on which there are element formation regions each partitioned by element isolation regions; a shallow groove isolation, which has a groove formed in each of the element isolation regions and an insulating film inside of the groove, said groove penetrating through the first Si layer and having a bottom in the SiGe layer; a second Si layer formed between the shallow groove isolation and the SiGe layer; and a semiconductor element formed over the main surface of the semiconductor substrate in the element formation regions. This construction enables a reduction in leakage current via the walls of the shallow groove isolation of the strained substrate, thereby improving the element isolation properties.

Abstract: The invention proposes a semiconductor configuration having a substrate, which has at least one component integrated therein. The substrate has a first main side with a metalization. At least parts of the metalization are underlaid with an insulation layer located in the substrate. By virtue of the fact that the insulation layer is realized in the form of a trench lattice, it is possible to reduce parasitic capacitances and undesirable signal power losses in the case of high-frequency signals.

Abstract: The present invention is provided to a semiconductor device and a method of fabricating the same. A spacer consisting of SiCxHy or SiOCxHy having a low dielectric constant is formed at the sidewall of a trench or a hole that is formed in an interlayer insulating film. It is therefore possible to reduce the dielectric constant while reducing critical dimension loss of the trench or the hole. Therefore, the present invention has advantages that it can enhance the operating speed of the device by minimizing parasitic capacitance and prohibiting RC delay and crosstalk.

Abstract: A device having electrically isolated low voltage and high voltage substrate regions includes low voltage and high voltage trench isolation structures in which a deep portion of the high voltage isolation trench provides electrical isolation in the high voltage regions. The high voltage isolation trench structures include a shallow portion that is simultaneously formed with the low voltage trench isolation structures. The deep portion of the high voltage isolation trench has a bottom surface and shares a continuous wall surface with the shallow portion that extends from the bottom surface to the principal surface of the substrate. A process for fabricating the device includes the use of a single resist pattern to simultaneously form the low voltage isolation trench structures and the shallow portion of the high voltage isolation structures.

Abstract: A method for enhancing the on-current carrying capability of a MOSFET device is disclosed. In an exemplary embodiment, the method includes recessing fill material formed within a shallow trench isolation (STI) adjacent the MOSFET so as to expose a desired depth of a sidewall of the STI, thereby increasing the effective size of a parasitic corner device of the MOSFET. The threshold voltage of the parasitic corner device is then adjusted so as to be substantially equivalent to the threshold voltage of the MOSFET device.

Abstract: A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.

Abstract: A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench.

Abstract: A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isolation trench located in the doped layer and having a dielectric layer located on a sidewall thereof. The semiconductor device may further include a conductive material located within the isolation trench and an interconnect that electrically connects the conductive material and the doped layer.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: Substrates with embedded free space light guiding channels for optical interconnects, and methods for making such substrates are shown. The method comprising steps of a groove in a first generally planar body, and combining the first body with a second generally planar body to form the substrate, and providing input and output ports to enable light to travel into and out of the groove. The first and second bodies may be made of silicon, polymers or combinations of the two. Additional generally planar bodies may be incorporated to provide for complex, 3D optical signal routing within the substrate.

Abstract: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: The semiconductor substrate of the integrated circuit includes at least one dielectrically isolating, vertical buried trench (2) having a height at least five times greater than its width, the trench laterally separating two regions (4, 5), and an epitaxial semiconductor layer (6) coveting the trench. An application is advantageously suited to MOS, CMOS and BiCMOS technologies.

Abstract: A process for insulating the interior of the trenches of trench type MOSgated devices in which a capping oxide is formed over the top of the trenches to span approximately a 3 micron gap and then reflowing the oxide at 1050° C. in pure O2 to flush air out of the trenches and leaving an at least partially evacuated sealed volume in each of the trenches.

Abstract: A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.

Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

Abstract: A semiconductor device comprises a substrate (11) having an insulating layer (12) formed on a surface thereof, and a silicon layer (13) located on a surface of the insulating layer. A trench (14) extends from a surface of the silicon layer (13) through the insulating layer (12) and into the substrate (11). An insulating liner (14a) is located on the side walls and the base of the trench (14), and an in-fill (14b) of thermally-conductive material is formed within the insulating liner. The insulating liner (14a), the in-fill material (14b) and the distance over which the trench 14) extends into the substrate (11) are such as to promote flow of heat from the silicon layer (13) to the substrate.

Abstract: A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: A semiconductor and a method of manufacturing thereof form a region with a sufficient gettering effect. A p-type channel MOSFET and an n-type channel MOSFET are formed in an n-type semiconductor layer, which is isolated in a form of islands on an SOI substrate. A high-concentration impurity diffused region is formed in such a manner as to surround the p-type channel MOSFET and the n-type channel MOSFET. The high-concentration impurity diffused region has a surface concentration of between 1×1018 atom/cm3 and 5×1020 atom/cm3 for achieving a desired gettering effect.

Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.

Abstract: A semiconductor isolation structure. The semiconductor isolation structure includes a substrate. A first device and a second device are formed within the substrate. An isolation region is formed within the substrate between the first device and the second device. The isolation region includes a deep region which extends into the substrate. The deep region includes a deep region cross-sectional area. A shallow region extends to the surface of the substrate. The shallow region includes a shallow region cross-sectional area. The deep region cross-sectional area is greater than the shallow region cross-sectional area. For an alternate embodiment, the deep region includes an oxide and the shallow region includes a protective wall. The protective wall can be formed from an oxide and a nitride.

Abstract: A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

Abstract: In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).

Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.

Abstract: A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Abstract: A recess is produced in a material layer by creating at least a first and a second structure in various steps. The layers define each other laterally and extend to the bottom of the recess. The first structure and the second structure are so narrow that they can be made by creating conformally produced layers that have an independent thickness and are smaller than the depth of the recess. The conformally produced layers are formed in an appropriate deposition process. A covering structure can be produced on top of the first and second structure. An opening can be made in the covering structure, through which the first structure and the second structure can be removed in an etching step.

Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: A microfabricated device includes a substrate having a device layer and substantially filled, isolating trenches; a doped region of material formed by photolithographically defining a region for selective doping of said device layer, selectively doping said region, and thermally diffusing said dopant; circuits on said device layer formed using a substantially standard circuit technology; and at least one structure trench in the substrate which completes the definition of electrically isolated micromechanical structural elements.

Abstract: A method of making a trench MOSFET structure having upper trench corner protection, the method not requiring trench corner rounding or sacrificial oxide/strip steps. The trench MOSFET structure fabricated according to the method of the present invention exhibits higher oxide breakdown voltage and lower gate-to-source capacitance.

Abstract: A semiconductor transistor formed between trench device isolation regions comprises; a gate electrode formed on a device formation region with the intervention of a gate insulating film and extended over the trench device isolation regions, a distance from an interface between the gate electrode and the gate insulating film to the surface of the device formation region and a distance from said interface to the trench device isolation region being the same, and a gate electrode wiring formed in self-alignment with the gate electrode to have the same length as the length of the gate electrode and connected on the gate electrode on the device formation region.

Abstract: The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer.

Abstract: A method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners including providing a shallow trench isolation (STI) feature included in a semiconductor process surface the STI feature including an anisotropically etched trench formed into a semiconductor substrate extending through a thickness including a thermally grown silicon dioxide layer overlying the semiconductor substrate and a metal nitride hardmask layer overlying the thermally grown silicon dioxide layer said anisotropically etched trench being back filled with a silicon dioxide filling material; removing excess silicon dioxide filling material overlying the hardmask layer according to a chemical mechanical polishing (CMP) process; removing the hard mask layer according to a wet chemical etching process; and, re-growing the thermally grown silicon dioxide layer including re-oxidizing to at least an originally formed thermally grown silicon dioxide layer thickness.

Abstract: A circuit structure has at least two etching trenches disposed at sidewalls of a silicon block left behind during the etching of the structure. The etching trenches are disposed at angles with respect to one another that are prescribed by the form of the silicon block left behind. Semiconductor layer structures which can interact with one another diagonally across are in each case accommodated in the etching trenches. In this case, the function of the entire circuit structure results from the interaction of the layer structures disposed in the various etching trenches.

Abstract: It is possible to obtain a semiconductor device with an element isolation structure showing a good isolation characteristic by filing an interior of a minute trench with a good quality insulating film free of a defect such as a void, and a manufacturing method therefor. The semiconductor device includes a semiconductor substrate and an isolation insulator. A trench is formed on a main surface of the semiconductor substrate. The isolation insulator is formed in an interior of the trench using a thermal oxidation method to isolate element forming regions from each other on the main surface of the semiconductor substrate. The isolation insulator is a lamination body formed by a plurality of oxide film layers.

Abstract: A process for creating silicon isolation regions which utilizes silicon islands or pillars as sources of silicon for silicon dioxide (or silicon oxide) fields. These silicon oxide fields separate active areas within a device. By providing multiple sources of silicon for silicon oxide formation, the described invention minimizes the use of trench wall edges as silicon sources for silicon oxide growth. This reduction in stress helps to minimize encroachment and undergrowth or bird's beak formation. This process also leads to a reduced step height between the field oxide and active areas, thus providing a more planar wafer surface.

Abstract: A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

Abstract: Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

Abstract: A semiconductor device in which the potential of a conductive support substrate can be kept to be a predetermined potential, while an SOI substrate is used as a chip substrate, without adding a new step and providing a rear electrode, is provided. In a chip, on the main surface of a first Si substrate of a P-type, a SiO2 film and a second Si substrate of a P-type are laminated in this order. The chip has, in the second Si substrate, isolation trenches, an outermost isolation trench, a plurality of element forming regions isolated by these trenches, second element forming regions, a peripheral region, and a peripheral region connection wiring which connects a contact region of the peripheral region with a contact region connected with a predetermined potential, for example, a ground potential in the second element forming region surrounded by, for example, the isolation trench.

Abstract: In order that the yield can be enhanced, the method of manufacturing a semiconductor device comprises the steps of: forming first holes 101a not penetrating a support side silicon wafer 101; forming a ground insulating film 102; forming primary connection plugs 105a by charging copper into the first holes 101a; forming a semiconductor film 108 on one face side of the support side silicon wafer 101 through an intermediate insulating film 109; forming elements on the semiconductor film 108; exposing bottom faces of the primary connection plugs 105a by polishing the other face of the support side silicon wafer 101; forming second holes 111 extending from an element forming face of the semiconductor film 108 to the primary connection plugs 105; and forming auxiliary connection plugs 112a for electrically connecting the elements with the primary connection plugs 105a by charging copper into the second holes 111.

Abstract: An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).

Abstract: Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.

Abstract: A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.

Abstract: A second trench (105b) is formed inside a semiconductor layer (102), penetrating a base layer (103) and moreover extends along a second direction (D2) while being connected to one end portion of each first portion (P1) of a first trench (105a) extending along a first direction (D1). A second gate control electrode (107b) is connected to a first gate control electrode (107a) at the one end portion, filling the inside of the second trench (105b). A gate contact portion (109) extending along the second direction (D2) exposes part of an upper surface of the second gate control electrode (107b). A gate aluminum electrode (108) is connected to the second gate control electrode (107b) through the gate contact portion (109), protruding outside beyond an end (103e) of the base layer (103) by a distance (W0).