Abstract: A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

Abstract: An apparatus for fabricating encapsulated micro-channels in a substrate is described. The apparatus includes the formation of a thin film layer over an area of a substrate. Following the formation of the thin layer, a periodic array of access windows are formed within the thin film layer along dimensions of one or more desired micro-channels. Following formation of the access windows, the one or more micro-channels are formed within an underlying layer of the substrate. Finally, the one or more micro-channels are encapsulated, thereby closing the one or more access windows along the dimensions of the desired micro-channels. Accordingly, the apparatus is suitable in one context for rapid prototyping of micro-electromechanical systems in the areas of, for example, RF micro-systems, fluidic micro-systems and bio-fluidic applications. In addition, the apparatus enables the rapid prototyping of integrated circuits.

Abstract: A second trench (105b) is formed inside a semiconductor layer (102), penetrating a base layer (103) and moreover extends along a second direction (D2) while being connected to one end portion of each first portion (P1) of a first trench (105a) extending along a first direction (D1). A second gate control electrode (107b) is connected to a first gate control electrode (107a) at the one end portion, filling the inside of the second trench (105b). A gate contact portion (109) extending along the second direction (D2) exposes part of an upper surface of the second gate control electrode (107b). A gate aluminum electrode (108) is connected to the second gate control electrode (107b) through the gate contact portion (109), protruding outside beyond an end (103e) of the base layer (103) by a distance (W0).

Abstract: A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.

Abstract: A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.

Abstract: A semiconductor device provided with an isolation oxide film formed by a trench isolation technique is described. The device prevents the development of crystal defects from the corners of a trench and secures stable operating characteristics. The semiconductor device is provided with an isolation oxide film formed so that boundaries between an active region and the isolation oxide film extend in a direction inclined at an angle in the range of 45°±10° to the cleavage plane of a silicon substrate. The isolation oxide film has a interior wall oxide film of a thickness in the range of 50 Å to 1000 Å coating the side walls and the bottom wall of a trench, and a filling oxide film filling up the trench coated with the interior wall oxide film. The edges of the active region contiguous to the isolation oxide film are rounded properly.

Abstract: An insulating layer in a field effect transistor is formed of superfine ceramic particles dispersed in a polymeric matrix. The characteristics of the insulating layer can be changed by varying the mix of ceramic particles and matrix components. Appropriate selection of components can provide a high dielectric constant material which is not subject to pinholes, has a high voltage breakdown and is chemically resistant. The material can be applied at relatively low processing temperatures, using a wide range of coating techniques, and is highly suited for use with polymeric substrates.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: A semiconductor device adopting shallow trench isolation for reducing an internal stress of a semiconductor substrate. The semiconductor device is composed of a semiconductor substrate provided with a trench for isolation, and an insulating film formed to cover the trench for relaxing an internal stress of the semiconductor substrate. The insulating film includes a first portion disposed to be opposed to a bottom of the trench, and a second portion disposed to be opposed to a side of the trench. A first thickness of the first portion is different from a second thickness of the second portion.

Abstract: An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.

Abstract: A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

Abstract: Vertical power devices include a semiconductor substrate having a first surface thereon and a drift region of first conductivity type therein. A quad arrangement of trenches are provided that extend into the first surface of the semiconductor substrate and define a drift region mesa therebetween. A base region of second conductivity type is included. The base region extends into the drift region and forms a first P-N rectifying junction therewith. A source region of first conductivity type is provided that extends into the base region and forms a second P-N rectifying junction therewith. A quad arrangement of insulated electrodes is provided in the quad arrangement of trenches. An insulated gate is provided on the drift region mesa. A source electrode is also provided that extends on the first surface. The source electrode is electrically connected to the source and base regions and to the quad arrangement of insulated electrodes.

Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Abstract: A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.

Abstract: A semiconductor device has both a logic section and a non-volatile memory (NVM) section. Transistors in both sections are separated by trench isolation. The logic isolation has narrower trenches than NVM trenches and both types of trenches have corners at the tops thereof. The trenches are lined by growing an oxide that is necessarily to take care of the plasma damage of the substrate, which is preferably silicon, that occurs during the formation of the trenches. These oxide liners are grown to a greater thickness in the NVM trenches than in the logic trenches to obtain a greater degree of corner rounding in the NVM trenches. This growth differential is achieved by selectively implanting the NVM trenches with a species that speeds oxide growth or selectively implanting the logic trenches with a species that retards oxide growth. As a further alternative, the NVM trenches can be implanted with a growth enhancing species and the logic trenches with a retarding species.

Abstract: A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.

Abstract: A trench is formed on a primary surface of a semiconductor substrate, and is filled with trench material to separate the surface region of the semiconductor substrate into plural active regions. At least a portion of the surface of the trench material adjoining the semiconductor substrate is depressed by a predetermined depth with reference to the primary surface of the semiconductor device. Thus, prevented is a decrease in a drain current of a semiconductor device having a trench isolation structure.

Abstract: A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Abstract: An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 74 (e.g. a well) formed in the substrate having a first conductivity type, a second region 84 below the first region 74 having a second conductivity type, and a trench formed in the substrate having a depth at least substantially as deep as the well. The trench 70 is filled with a non-conductive material 71 that forms a frame around the transistor, whereby soft errors due to electron-hole pairs caused by ionizing radiation in the frame are substantially eliminated.

Abstract: A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting layer. Such structure improves, for example, an operational speed by reducing junction capacitance, prevents a hot carrier effect from occurring by weakening an electric field around the drain region, and improves reliability by preventing a latch up from occurring. The semiconductor device includes a gate electrode formed on the semiconductor substrate, sidewall spacers formed at the sidewalls of the gate electrode, an impurity layer formed in the semiconductor substrate below each sidewall spacer, a trench formed in the semiconductor substrate at both sides of the gate electrode, oxide spacers formed at the bottom inside corner of each trench, and a conductive material filling up each trench.

Abstract: In a semiconductor substrate (100), semiconductor regions (1, 2, 3, 5) belonging to the IGBT are formed in an IGBT region (20) and semiconductor regions (1, 4) belonging to the diode are formed in a diode region (21). The IGBT and the diode are connected in anti-parallel to each other. A trench (15) in which an insulator (16) is buried is formed between the IGBT region (20) and the diode region (21). The insulator (16) restricts the reverse recovery current which flows from the diode region (21) into the IGBT region (20). Thus, semiconductor regions of an IGBT and a diode connected in anti-parallel with each other are fabricated in a single semiconductor substrate and the chip size is reduced.

Abstract: Techniques for etching a wafer layer using multiple layers of the same photoresistant material and structures formed using such techniques are provided. In a method, first, multiple layers of the same photoresist material are formed over the wafer layer to form a composite photoresist layer. The composite photoresist layer is patterned and developed to form a patterned photoresist layer. Exposed portions of the wafer layer are then removed using the pattern photoresist layer. Each of the multiple layers of photoresist may, for example, be formed to a maximum rated thickness for the photoresist material. Structures formed using this process may have relatively small dimensions (e.g., widths of 5 microns or less or a spacing or pitch of 5 microns or less). In addition, structures may also have sidewalls which are relatively long, smooth, and/or vertical.

Abstract: A silicon substrate comprises a silicon-on-insulator (SOI) portion which includes an insulating silicon dioxide layer beneath a device layer. SOI circuit structures, including SOI field effect transistors, are formed in the device layer. The substrate also comprises a bulk portion. Bulk semiconductor circuit structures are formed in wells in the bulk portion. The bulk circuit structures may be coupled to the SOI circuit structures.

Abstract: A compensation component includes a drift path formed of p-conducting and n-conducting layers which are led around or along a trench. A process for producing the compensation component is also provided.

Abstract: A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing the stress in the silicon layer. Embodiments include forming a patterned dielectric layer on an SOI substrate, forming sidewall spacers thereon, and etching the underlying silicon layer followed by oxidation or controlled etching to form the trench with downwardly decreasing side surfaces.

Abstract: The power MOSFET has a semiconductor layer formed on a highly doped semiconductor substrate of a first conductivity type. The semiconductor layer is itself of the other conductivity type and a highly doped source zone of the other conductivity type and a highly doped drain zone of the other conductivity type are formed in the semiconductor layer. The power MOSFET also has a gate electrode. A metallically conductive connection runs between the source zone and the semiconductor substrate, so that the power MOSFET is in the form of a source-down MOSFET, and the heat can be dissipated via the semiconductor substrate or a cooling fin fitted there.

Abstract: This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench-trench short circuiting.

Abstract: A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode. The regions have a second conduction type, are disposed between the transistor configuration and the substrate edge, and extend from the substrate surface into the substrate and surround the transistor configuration. At least two adjacent insulating trench regions are disposed between the regions and extend from the substrate surface into the substrate for isolating the doped regions from one another. The trenches may have a smaller depth than the doped regions. A method for fabricating a semiconductor configuration includes providing a substrate having a first conduction type and producing regions in the substrate by introducing a dopant. The regions have a second conduction type.

Abstract: Trenches are formed by using stripe-form patterns with the same width and the same interval as a mask in the surface area of a silicon substrate and element isolation regions of STI structure are formed by filling insulating films into the trenches. Further, slits for isolating floating gates are formed by etching a polysilicon layer by using stripe-form patterns with the same width and the same interval as a mask. In addition, control gates (word lines) are formed by subjecting the polysilicon layer to the anisotropic etching process by using stripe-form patterns with the same width and the same interval as a mask.

Abstract: Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure.

Abstract: A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.

Abstract: On one side of a shallow trench isolation region formed on the surface of a p type well, an n type source region is provided while on the other side thereof, an n type drain region is provided so as to sandwich the shallow trench isolation region. In the drain region, a bent portion to allow a breakdown current to flow is provided and connected to a gate of a MOSFET comprising a circuit to be protected. Furthermore, a well contact connected to the source region is formed on the well surface and this well contact is grounded. When a positive high voltage which is higher than a predetermine voltage is applied to the drain region, since electric fields concentrate at the bent portion, a breakdown current flows from this bent portion toward the well contact. Thereafter, a current flows between the source and the drain.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: The invention includes a shallow trench isolation structure having a trench formed in the Si substrate and having an upper surface, a liner layer formed in the trench overlying the upper surface of the trench, a gettering material layer formed on the liner layer; and a filler oxide formed on the gettering material layer The gettering material layer inhibits the diffusion of metallic contaminants from the filler oxide into the surrounding silicon substrate regions

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: A semiconductor device having a self-aligned contact pad and the method for manufacturing the device are disclosed. The semiconductor device includes: an isolation region formed in a semiconductor substrate; multiple conductive structures formed on the top surface of the semiconductor substrate; self-aligned conductive pads filling spaces between adjacent conductive structures and between the isolation region and the conductive structures. The method includes: forming a conductive structure on a semiconductor substrate; forming insulating sidewall spacers on the conductive structures, forming a conductive layer that fills spaces between the conductive structures and contacts the semiconductor substrate; and patterning the conductive layer.

Abstract: A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

Abstract: There is disclosed a semiconductor device in which trenches are formed at predetermined intervals on a silicon substrate. In each trench, a first silicon oxide film is formed with the upper region of the first silicon oxide film protruding from a main substrate surface. A second silicon oxide film is formed from a boundary of the upper region in the first silicon oxide film and substrate over to the substrate surface. The height of the second silicon oxide film from the substrate surface is smaller than that of the upper region from the substrate surface. An active region is defined/formed on the substrate surface by an isolating film formed of the first and second silicon oxide films. A gate oxide film is formed on an active region surface, and a gate electrode is formed on the gate oxide film and extended from the active region over to the upper part of the isolating film.

Abstract: A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer.

Abstract: A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or “offset” towards a shallower part.

Abstract: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, comprising a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

Abstract: A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad.

Abstract: A device isolation structure and a method thereof including a semiconductor substrate wherein a field isolation region including a plurality of dummy active regions and an active region are defined, a plurality of trenches formed among the regions, a filling layer filled in the plurality of trenches, a gate insulation layer formed on the semiconductor substrate having the filling layer, and a second conduction layer formed on the gate insulation layer, is capable of preventing a dishing from being generated in etching by forming the plurality of dummy active regions in the field isolation region and basically preventing the wide trenches from being formed, minimizing a parasitic capacitance generated in the dummy active-gate insulation layer-gate insulation layer in the field isolation region, and simplifying an isolation process by using the dummy active pattern.

Abstract: A semiconductor device including a trench element separation structure and adapted to a high degree of integration without having crystal defects produced in a semiconductor substrate, and a method of manufacturing the same. The semiconductor device includes a trench element separation region in a prescribed region of the semiconductor substrate, the wall of the semiconductor substrate which forms an inside surface of a trench is covered with a first insulation film, and a second insulation film and a third insulation film are filled inside the trench being stacked in layers in this order.

Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Abstract: The present invention provides a process for fabricating a semiconductor component, comprising the following steps: providing a trench (15) in a substrate (1); depositing a liner layer (8) on the resulting structure using a nonconformal deposition process, so that the thicknesses (dL1, d L3) of the liner layer (8) on the trench walls and on the trench base are significantly smaller than the thickness (dL2) of the liner layer (8) on the substrate surface; providing a layer (10) of an insulating material on the resulting structure by means of a conformal deposition process; and anisotropic etching of the layer (10) of the insulating material in order to remove the layer (10) from a region of the trench base. The invention also provides a corresponding semiconductor component.