Abstract: The present invention provides a semiconductor manufacturing method. A substrate having a plurality of first trenches can be provided. The substrate can include a first pattern formed between two adjacent first trenches. A first dielectric layer can be deposited onto the substrate. The first dielectric layer can cover at least one side wall of the first pattern. A second dielectric layer can be deposited onto the substrate. The second dielectric layer can fill the first trenches. The first pattern can be severed to form a second pattern on the substrate. The second dielectric layer can be removed from the first trenches.

Abstract: Described herein are compositions and methods for forming silicon oxide films. In one aspect, the film is deposited from at least one silicon precursor compound, wherein the at least one silicon precursor compound is selected from the following Formulae A and B: as defined herein.

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Abstract: A capacitor that includes a substrate having a principal surface; a dielectric film on the principal surface of the substrate; and an electrode layer on the dielectric film. The substrate has a recess structure portion with at least one recess portion in a second region outside a first region where the electrode layer overlaps the dielectric layer when viewed in a plan view from a normal direction of the principal surface of the substrate, and the dielectric film is on the recess structure portion.

Abstract: A mask frame assembly and an evaporation apparatus are disclosed. The mask frame assembly comprises a frame and a mask plate fixed on the frame. The mask frame assembly is provided with alignment marks, which comprise a first alignment hole arranged in the frame and a second alignment hole arranged in the mask plate. The first alignment hole is a through hole. The mask frame assembly effectively solves a problem in which liquid residuals in alignment holes of the frame interfere with alignment.

Abstract: Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

Abstract: Described herein are compositions and methods for forming silicon oxide films. In one aspect, the film is deposited from at least one silicon precursor compound, wherein the at least one silicon precursor compound is selected from the following Formulae A and B: as defined herein.

Abstract: Provided is a high-frequency module capable of improving a shielding performance for a specific component. In a high-frequency module 1a, a component 3c that is mounted on a top surface 20a of a multilayer wiring board 2 is surrounded by a shield film 6 coating a surface of a sealing-resin layer 4, a plurality of metallic pins 5a arranged in the sealing-resin layer 4 so as to surround the component 3c, an outer electrode 8c formed on a bottom surface 20b of the multilayer wiring board 2 so as to be located at a position that overlaps with the component 3c when viewed in a direction perpendicular to the top surface 20a of the multilayer wiring board 2, and a plurality of connection conductors (via conductors 10b and pad electrodes 11) connecting the metallic pins 5a and the outer electrode 8c to one another.

Abstract: A high frequency module includes a plurality of components on an upper surface of a multilayer wiring substrate, a sealing resin layer on the upper surface of the multilayer wiring substrate, a shield wall surrounding one of the components within the sealing resin layer, and a shield film on an upper surface of the sealing resin layer. The shield film covers a portion of the upper surface of the sealing resin layer that overlaps the one of the components but not the other components viewed from a direction perpendicular to the upper surface of the multilayer wiring substrate. An upper end of the shield wall is exposed from the upper surface of the sealing resin layer to be connected to the shield film, and a lower end thereof is exposed from a lower surface of the sealing resin layer to be connected to the multilayer wiring substrate.

Abstract: A transient voltage suppression device with improved electrostatic discharge (ESD) robustness includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second doped well having the second conductivity type, a second heavily-doped area having the first conductivity type, and a first current blocking structure. The first doped well is arranged in the semiconductor substrate. The first heavily-doped area is arranged in the first doped well. The second doped well is arranged in the semiconductor substrate. The second heavily-doped area is arranged in the second doped well. The first current blocking structure is arranged in the semiconductor substrate, spaced from the bottom of the semiconductor substrate, and arranged between the first doped well and the second doped well.

Abstract: A method for manufacturing a semiconductor device having a local interconnect structure includes providing a semiconductor substrate having a gate on an active region, a hardmask layer on the gate, and a first dielectric layer on the gate, etching the first dielectric layer to form a first interconnect trench on the active region, forming a metal silicide layer at a bottom of the first interconnect trench, forming a first metal layer filling the first interconnect trench, forming a second dielectric layer on the gate and the first interconnect trench, etching the second dielectric layer to form a second interconnect trench in a staggered pattern relative to the first interconnect trench, etching the second dielectric layer to form a third interconnect trench, forming a second metal layer in the second interconnect trench and in the third interconnect trench to form the local interconnect structure.

Abstract: Bisaminoalkoxysilanes of Formula I, and methods using same, are described herein: R1Si(NR2R3)(NR4R5)OR6??I where R1 is selected from hydrogen, a C1 to C10 linear alkyl group, a C3 to C10 branched alkyl group, a C3 to C10 cyclic alkyl group, a C3 to C10 alkenyl group, a C3 to C10 alkynyl group, a C4 to C10 aromatic hydrocarbon group; R2, R3, R4, and R5 are each independently selected from hydrogen, a C4 to C10 branched alkyl group, a C3 to C10 cyclic alkyl group, a C3 to C10 alkenyl group, a C3 to C10 alkynyl group, and a C4 to C10 aromatic hydrocarbon group; R6 is selected from a C1 to C10 linear alkyl group, a C3 to C10 branched alkyl group, a C3 to C10 cyclic alkyl group, a C3 to C10 alkenyl group, a C2 to C10 alkynyl group, and a C4 to C10 aromatic hydrocarbon group.

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

Abstract: A method for forming a dielectric structure includes forming an auxiliary layer over a substrate, and forming a hole within the auxiliary layer. A fill material is deposited into the hole. The auxiliary layer is removed to form the dielectric structure having a negative taper. The dielectric structure has a top critical dimension greater than a bottom critical dimension.

Abstract: A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source region and the drain region, and a gate electrode which is formed in the trench. The gate electrode includes a first electrode buried over a bottom of the trench; a second electrode formed over the first electrode; and a liner electrode having an interface part which is positioned between the first electrode and the second electrode and a side part, which is positioned on sidewalls of the second electrode and overlaps with the source region and the drain region.

Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

Abstract: Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.

Abstract: A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.

Abstract: Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.

Abstract: Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.

Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.

Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer, and a source/drain (S/D) region. The substrate has a trench, and the memory material layer is formed on a sidewall of the trench. The first gate layer, the second gate layer, and the first dielectric layer, which is formed between the first gate layer and the second gate layer, are filled in the trench. The source/drain region is formed in the substrate and adjacent to the memory material layer. The first gate layer is extended in a direction perpendicular to a direction in which the source/drain region is extended.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.

Abstract: Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

Abstract: In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.

Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.

Abstract: Line trenches are formed in a stack of a bulk semiconductor substrate and an oxygen-impermeable layer such that the depth of the trenches in the bulk semiconductor substrate is greater than the lateral spacing between a pair of adjacently located line trenches. Oxygen-impermeable spacers are formed on sidewalls of the line trenches. An isotropic etch, either alone or in combination with oxidation, removes a semiconductor material from below the oxygen-impermeable spacers to expand the lateral extent of expanded-bottom portions of the line trenches, and to reduce the lateral spacing between adjacent expanded-bottom portions. The semiconductor material around the bottom portions is oxidized to form a semiconductor oxide portion that underlies multiple oxygen-impermeable spacers. Semiconductor-on-insulator (SOI) portions are formed above the semiconductor oxide portion and within the bulk semiconductor substrate.

Abstract: An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.

Abstract: A method of fabricating an image sensor includes the steps of: forming at least two photosites in a semiconductor substrate; forming a trench between the photosites; forming a thin liner on at least the sidewalls of the trench; depositing a conductive material having a first refractive index in the trench; and forming a region surrounded by the conductive material and having a second refractive index lower than the first index of refraction within the conductive material in the trench.

Abstract: A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.

Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

Abstract: Electrostatic discharge devices and methods of forming thereof are disclosed. In one embodiment, a semiconductor device includes an electrostatic discharge (ESD) device region disposed within a semiconductor body. A first ESD device is disposed in a first region of the ESD device region, and a second ESD device disposed in a second region of the ESD device region. The second region is separated from the first region by a first trench.

Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.

Abstract: An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.

Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

Abstract: A polysilicon-filled isolation trench in a substrate is effective to isolate adjacent semiconductor devices from one another. A silicon nitride cap is provided to protect the polysilicon in the isolation trench from subsequent field oxidation. The cap has lateral boundaries that extend between the side boundaries of the polysilicon and the sidewalls of the trench. Subsequent field oxide regions formed adjacent to the trench establish a gap dimension from the substrate to a top surface of the field oxide regions adjacent to the polysilicon side boundaries that is no less than half of the field oxide thickness.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

Abstract: A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.

Abstract: A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

Abstract: Electrostatic discharge devices and methods of forming thereof are disclosed. In one embodiment, a semiconductor device includes an electrostatic discharge (ESD) device region disposed within a semiconductor body. A first ESD device is disposed in a first region of the ESD device region, and a second ESD device disposed in a second region of the ESD device region. The second region is separated from the first region by a first trench.

Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

Abstract: A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel.

Abstract: The invention relates to a semiconductor arrangement and method for production thereof, wherein the semiconductor arrangement is provided with an integrated circuit arranged on a substrate. The integrated circuit is structured on the front face of the substrate and at least one capacitor is connected to the integrated circuit, wherein the at least one capacitor is designed as a monolithic deep structure in trenches. The trenches are arranged in at least one first group and at least one second group, the trenches of a group running essentially parallel to each other and the first and second group are at an angle to each other, essentially at right angles to each other.

Abstract: Disclosed is a semiconductor structure for producing a handle wafer contact in trench insulated SOI discs which may be used as a deep contact (7, 6, 30?) to the handle wafer (1) of a thick SOI disc as well as for a trench insulation (40). Therein, the same method steps are used for both structures which are used as deep contact to the handle wafer of the thick SOI disc as well as trench insulation.

Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.