With Means To Increase Surface Area (e.g., Grooves, Ridges, Etc.) Patents (Class 257/534)
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Patent number: 8878340Abstract: Devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like, are provided herein. In particular, the device includes a composite thermal capacitor including a phase change material and a high thermal conductivity material in thermal communication with the phase change material. The high thermal conductivity material is also in thermal communication with an active regeneration cooling device. The heat from the composite thermal capacitor is dissipated by the active regeneration cooling device.Type: GrantFiled: August 30, 2013Date of Patent: November 4, 2014Assignee: Georgia Tech Research CorporationInventors: Andrei G. Fedorov, Craig Green, Yogendra Joshi
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Patent number: 8866260Abstract: An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vdd and Vss, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.Type: GrantFiled: November 12, 2009Date of Patent: October 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hau-Tai Shieh, Chen-Hui Hsieh
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Patent number: 8860115Abstract: A capacitor includes a lower electrode having a curved surface, a first seed on a sidewall of the lower electrode, which the first seed includes a metal silicide and has a shape corresponding to the curved surface of the lower electrode, a dielectric layer on the lower electrode, the dielectric layer covering the first seed, and an upper electrode on the dielectric layer.Type: GrantFiled: March 12, 2013Date of Patent: October 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jong-Ryul Jun
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Patent number: 8853823Abstract: The capacitor of a nonvolatile memory device includes first and second electrodes formed in the capacitor region of a semiconductor substrate to respectively have consecutive concave and convex shape of side surfaces formed along each other and a dielectric layer formed between the first and the second electrodes.Type: GrantFiled: November 3, 2011Date of Patent: October 7, 2014Assignee: SK Hynix Inc.Inventor: Je il Ryu
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Publication number: 20140284671Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.Type: ApplicationFiled: March 22, 2013Publication date: September 25, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
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Publication number: 20140246652Abstract: An interdigitated capacitor includes a substrate and a pair of comb-like electrodes both formed on the semiconductor substrate and horizontally arranged thereon, each of the pair of comb-like electrodes including finger electrodes having a curved profile.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: International Business Machines CorporationInventor: International Business Machines Corporation
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Publication number: 20140239448Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frederick G. Anderson, Natalie B. Feilchenfeld, Zhong-Xiang He, Theodore J. Letavic, Yves T. Ngu
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Patent number: 8816475Abstract: Semiconductor devices having capacitors are provided. The semiconductor device includes spiral storage nodes disposed on a semiconductor substrate to vertically extend along spiral lines, a dielectric layer on the spiral storage nodes, and a plate node formed on the dielectric layer of the spiral storage nodes.Type: GrantFiled: August 17, 2012Date of Patent: August 26, 2014Assignee: SK Hynix Inc.Inventor: Hyung Ju Jin
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Patent number: 8816474Abstract: One or more embodiments relate to a semiconductor device, comprising: a substrate; and a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together, each of the second conductive vias passing through the substrate, the second conductive vias spacedly disposed from the first conductive vias.Type: GrantFiled: August 7, 2008Date of Patent: August 26, 2014Assignee: Infineon Technologies AGInventors: Andre Hanke, Oliver Nagy
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Patent number: 8809956Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.Type: GrantFiled: October 13, 2011Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsiu-Ying Cho
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Patent number: 8803285Abstract: A semiconductor device has a capacitive structure formed by sequentially layering, on a wiring or conductive plug, a lower electrode, a capacitive insulation film, and an upper electrode. The semiconductor device has, as the capacitive structure, a thin-film capacitor having a lower electrode structure composed of an amorphous or microcrystalline film or a laminate of these films formed on a polycrystalline film.Type: GrantFiled: May 8, 2007Date of Patent: August 12, 2014Assignee: Renesas Electronics CorporationInventors: Hiroto Ohtake, Naoya Inoue, Ippei Kume, Takeshi Toda, Yoshihiro Hayashi
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Publication number: 20140210050Abstract: Provided is a method of manufacturing a capacitor of a display apparatus, the display apparatus being formed on a substrate and including a thin film transistor, which includes an active layer, a gate electrode, and source and drain electrodes, a display device connected to the thin film transistor, and the capacitor, the method including: forming an electrode layer on the substrate; forming a passivation layer on the electrode layer; patterning the passivation layer to form a first pattern including first branch patterns parallel to each other, and a second pattern including second branch patterns parallel to each other and interposed between the first branch patterns; and forming first and second electrodes by etching the electrode layer using the first and second patterns as masks.Type: ApplicationFiled: August 21, 2013Publication date: July 31, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Seong-Min Wang, Mu-Gyeom Kim, Tae-An Seo, Gug-Rae Jo, Dae-Young Lee, Jung-Gun Nam, Dae-Hwan Jang
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Publication number: 20140203404Abstract: Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.Type: ApplicationFiled: January 21, 2013Publication date: July 24, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jihong Choi, John J. Zhu, PR Chidambaram, Bin Yang, Lixin Ge
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Publication number: 20140197519Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.Type: ApplicationFiled: January 17, 2013Publication date: July 17, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jihong Choi, John J. Zhu, PR Chidambaram, Bin Yang, Lixin Ge
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Publication number: 20140191366Abstract: Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Colin J. Brodsky, Anne C. Friedman, Herbert Lei Ho, Byeong Yeol Kim, Dan Mihai Mocuta, Garrett W. Oakley, Chienfan Yu
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Publication number: 20140191365Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: Intermolecular, Inc.Inventors: Sergey Barabash, Dipankar Pramanik
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Patent number: 8766404Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.Type: GrantFiled: January 10, 2013Date of Patent: July 1, 2014Assignee: Intermolecular, Inc.Inventors: Sergey Barabash, Dipankar Pramanik
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Patent number: 8754462Abstract: A semiconductor device includes a first electrode electrically connected to an upper surface of a semiconductor element, a first internal electrode electrically connected to a lower surface of the semiconductor element and having a plurality of first comb finger portions and a first connection portion connecting the plurality of first comb finger portions together, a second electrode electrically connected to the first internal electrode, a second internal electrode electrically connected to a lower surface of the first electrode and having a plurality of second comb finger portions and a second connection portion connecting the plurality of second comb finger portions together, the plurality of second comb finger portions being interdigitated with but not in contact with the plurality of first comb finger portions, and a lower dielectric filling the space between the plurality of first comb finger portions and the plurality of second comb finger portions.Type: GrantFiled: January 3, 2013Date of Patent: June 17, 2014Assignee: Mitsubishi Electric CorporationInventors: Noboru Miyamoto, Yoshikazu Tsunoda
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Patent number: 8729616Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.Type: GrantFiled: December 18, 2012Date of Patent: May 20, 2014Assignee: Texas Instruments IncorporatedInventors: Imran Mahmood Khan, Allan T. Mitchell, Kaiping Liu
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Patent number: 8716834Abstract: A semiconductor device that can prevent reduction in the amplitude of electromagnetic waves transmitted from a reader/writer, and can prevent heating of an element forming layer due to a change in a magnetic field. The semiconductor device of the invention has an element forming layer formed over a substrate, and an antenna connected to the element forming layer. The element forming layer has at least wires such as a power supply wire and a ground wire that are arranged in a non-circular shape. The element forming layer and the antenna may be provided so as to overlap each other at least partially. The antenna may be provided above or below the element forming layer.Type: GrantFiled: December 21, 2005Date of Patent: May 6, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Yoshitaka Moriya
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Patent number: 8710569Abstract: A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.Type: GrantFiled: January 5, 2012Date of Patent: April 29, 2014Assignee: Renesas Electronics CorporationInventors: Ken Inoue, Masayuki Hamada
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Patent number: 8710626Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.Type: GrantFiled: July 18, 2012Date of Patent: April 29, 2014Assignee: Seiko Instruments Inc.Inventors: Ayako Inoue, Naoto Saitoh
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Patent number: 8686541Abstract: The present invention provides technology directed to a semiconductor device and a method of manufacturing the same. According to the present invention, metal contact plugs are formed to come into contact with both sidewalls of a capacitor, including lower electrodes, dielectric layers, and an upper electrode. Accordingly, contact resistance can be reduced because the contact area of the upper electrode and the metal contact plugs forming the capacitor, can be increased. Furthermore, the number of chips per wafer can be increased because the area in which the metal contact plugs and the capacitor are formed can be reduced. In addition, the generation of noise can be reduced because the contact area of the capacitor and the metal contact plugs is increased and thus voltage at the upper electrode is stabilized.Type: GrantFiled: July 13, 2011Date of Patent: April 1, 2014Assignee: Hynix Semiconductor Inc.Inventor: Jai Yong Woo
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Patent number: 8674423Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.Type: GrantFiled: November 22, 2011Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: David S. Collins, Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel
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Patent number: 8659063Abstract: A pin capacitor of a semiconductor device includes a first isolation layer formed in a substrate and defining a dummy active area, a plurality of gates formed over the first isolation layer, a spacer formed at both sidewalls of each of the gates, and a plug formed over the dummy active area and in contact with the spacer. The substrate and the plug are coupled to a ground unit, and the gate is coupled to a pad unit. That is, the pin capacitor includes a first capacitor including the gate, the isolation layer, and the substrate and a second capacitor including the gate, the spacer, and the plug, which are coupled in parallel to each other.Type: GrantFiled: December 8, 2010Date of Patent: February 25, 2014Assignee: Hynix Semiconductor Inc.Inventor: Jeong-Soo Kim
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Patent number: 8643142Abstract: Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are provided above the stack. Contact structures extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers.Type: GrantFiled: November 21, 2011Date of Patent: February 4, 2014Assignee: SanDisk Technologies Inc.Inventors: Masaaki Higashitani, Peter Rabkin
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Publication number: 20140027883Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.Type: ApplicationFiled: October 1, 2013Publication date: January 30, 2014Applicant: Micron Technology, Inc.Inventor: Yongjun Jeff Hu
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Publication number: 20140015102Abstract: A semiconductor device includes a substrate wafer and having a front face and a back face. A front hole is formed in the front face and a multilayer capacitor is formed in the front hole. A back hole is formed in the back face of the substrate wafer to expose at least a portion of the multilayer capacitor. A front electrical connection on the front face and a back electrical connection in the back hole are used to make electrical connection to first and second conductive plates of the multilayer capacitor which are separated by a dielectric layer. The front hole may have a cylindrical shape or an annular shape.Type: ApplicationFiled: July 5, 2013Publication date: January 16, 2014Inventors: Pierre Bar, Sylvain Joblot
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Publication number: 20140001598Abstract: Atomic layer deposition (ALD) of TaAlC for capacitor integration is generally described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in at least one of the dielectric layers, the MIM capacitor includes an electrode having a conformal layer of TaAlC and the MIM capacitor is electrically coupled to one or more of the semiconductor devices. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 21, 2011Publication date: January 2, 2014Inventors: Nick Lindert, Ruth A. Brain, Joseph M. Steigerwald, Timothy E. Glassman, Andre Baran
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Patent number: 8618635Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.Type: GrantFiled: October 27, 2010Date of Patent: December 31, 2013Assignee: Infineon Technologies AGInventors: Sunoo Kim, Moosung Chae, Bum Ki Moon
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Patent number: 8610249Abstract: Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.Type: GrantFiled: March 30, 2012Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Publication number: 20130313681Abstract: A capacitance structure includes a first input terminal configured to input a first input signal, a first output terminal configured to output the first output signal, a second input terminal configured to input a second input signal, a second output terminal configured to output a second output signal, and a plurality of trench cells. Each of the plurality of trench cells includes a first electrode and a second electrode. The first electrodes of the plurality of trenches are interconnected to form a first electrode of the capacitor structure, the second electrodes of the plurality of trench cells are interconnected to form a second electrode of the capacitor structure, the first electrode of the capacitor structure is connected to the first input signal, and the second electrode of the capacitor structure is connected to the input second signal.Type: ApplicationFiled: May 24, 2013Publication date: November 28, 2013Inventors: Mehmet GOEKCEN, Jacek KRUPPA, Thomas STEINECKE
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Patent number: 8592946Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.Type: GrantFiled: March 14, 2011Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventor: Huilong Zhu
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Publication number: 20130307121Abstract: A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.Type: ApplicationFiled: July 8, 2013Publication date: November 21, 2013Inventors: VEERARAGHAVAN S. BASKER, WILFRIED E. HAENSCH, EFFENDI LEOBANDUNG, TENKO YAMASHITA, CHUN-CHEN YEH
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Patent number: 8587088Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.Type: GrantFiled: February 17, 2011Date of Patent: November 19, 2013Assignee: Apple Inc.Inventor: Nicholas Seroff
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Patent number: 8575721Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.Type: GrantFiled: August 23, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventor: Ryuichi Okamura
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Publication number: 20130270677Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width.Type: ApplicationFiled: June 10, 2013Publication date: October 17, 2013Applicant: Elpida Memory, Inc.Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
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Patent number: 8546915Abstract: An integrated circuit having a place-efficient capacitor includes a lower capacitor electrode having a surface area comprised of an inner surface area of a partial opening and a via opening formed in a patterned dielectric layer on a semiconductor substrate, a capacitor insulating layer overlying the lower capacitor electrode, and an upper capacitor electrode including a metal fill material filling the partial opening and the via opening and having a surface area that includes the inner surface area of the partial opening and via opening.Type: GrantFiled: July 5, 2012Date of Patent: October 1, 2013Assignee: GLOBLFOUNDRIES, Inc.Inventor: Dmytro Chumakov
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Patent number: 8536678Abstract: A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias.Type: GrantFiled: October 17, 2012Date of Patent: September 17, 2013Assignee: QUALCOMM IncorporatedInventors: Matthew Michael Nowak, Shiqun Gu
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Publication number: 20130234291Abstract: A semiconductor device includes a first electrode electrically connected to an upper surface of a semiconductor element, a first internal electrode electrically connected to a lower surface of the semiconductor element and having a plurality of first comb finger portions and a first connection portion connecting the plurality of first comb finger portions together, a second electrode electrically connected to the first internal electrode, a second internal electrode electrically connected to a lower surface of the first electrode and having a plurality of second comb finger portions and a second connection portion connecting the plurality of second comb finger portions together, the plurality of second comb finger portions being interdigitated with but not in contact with the plurality of first comb finger portions, and a lower dielectric filling the space between the plurality of first comb finger portions and the plurality of second comb finger portions.Type: ApplicationFiled: January 3, 2013Publication date: September 12, 2013Inventors: Noboru MIYAMOTO, Yoshikazu TSUNODA
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Patent number: 8519510Abstract: Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.Type: GrantFiled: June 21, 2011Date of Patent: August 27, 2013Assignee: Intel CorporationInventors: Brian S. Doyle, Uday Shah, Satyarth Suri, Ramanan V. Chebiam
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Publication number: 20130207233Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.Type: ApplicationFiled: March 27, 2013Publication date: August 15, 2013Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Semiconductor Manufacturing International (Shanghai) Corporation
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Publication number: 20130207232Abstract: Semiconductor devices having capacitors are provided. The semiconductor device includes spiral storage nodes disposed on a semiconductor substrate to vertically extend along spiral lines, a dielectric layer on the spiral storage nodes, and a plate node formed on the dielectric layer of the spiral storage nodes.Type: ApplicationFiled: August 17, 2012Publication date: August 15, 2013Applicant: SK HYNIX INC.Inventor: Hyung Ju JIN
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Patent number: 8492874Abstract: Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.Type: GrantFiled: February 4, 2011Date of Patent: July 23, 2013Assignee: QUALCOMM IncorporatedInventors: Je-Hsiung Lan, Matthew Michael Nowak, Evgeni P. Gousev, Jonghae Kim, Clarence Chui
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Publication number: 20130181326Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
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Patent number: 8487406Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.Type: GrantFiled: September 19, 2011Date of Patent: July 16, 2013Assignee: Broadcom CorporationInventors: Hooman Darabi, Qiang Li, Bo Zhang
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Publication number: 20130161792Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region.Type: ApplicationFiled: December 17, 2012Publication date: June 27, 2013Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventor: Maxim Integrated Products, Inc.
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Patent number: 8471363Abstract: A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.Type: GrantFiled: September 27, 2011Date of Patent: June 25, 2013Assignee: Denso CorporationInventors: Kazushi Asami, Yasuhiro Kitamura
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Publication number: 20130147015Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.Type: ApplicationFiled: February 12, 2013Publication date: June 13, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machines Corporation
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Publication number: 20130134557Abstract: Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.Type: ApplicationFiled: January 24, 2013Publication date: May 30, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machines Corporation