With Means To Increase Surface Area (e.g., Grooves, Ridges, Etc.) Patents (Class 257/534)
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Patent number: 8039923Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: November 10, 2009Date of Patent: October 18, 2011Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Patent number: 8004064Abstract: A thin film capacitor with a trench structure having a base substance and a pair of electrodes provided on the base substance, and a dielectrode provided between the electrodes. The trench pattern is configured to have a first pattern and a second pattern separate from the first pattern. The first pattern having a plurality of protrusions provided upright at predetermined intervals, and the second pattern separate from the first pattern having a plurality of recesses provided at predetermined intervals, are provided at the side of the base substance where the dielectric film is formed. Trenches are each defined by the outer wall of each protrusion and the inner wall of each recess.Type: GrantFiled: March 26, 2008Date of Patent: August 23, 2011Assignee: TDK CorporationInventor: Shigeru Shoji
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Patent number: 7999350Abstract: After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.Type: GrantFiled: September 8, 2008Date of Patent: August 16, 2011Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Wen-Hwa Chen, Hsien-Chie Cheng, Yun-Chiao Chen
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Patent number: 7994610Abstract: A capacitor in an IC has a first layer of conductive strips extending along a first direction (Z-direction). A first plurality of conductive strips in the first layer forms a portion a first node of the capacitor and alternates with a second plurality of conductive strips forming a portion of a second node of the capacitor. A plate layer adjacent to the first layer has a third plurality of conductive strips forming a portion the first node. Each strip in the third plurality of conductive strips is adjacent to another strip forming a part of the first node. The strips in the plate layer extend along a second direction (X-direction) orthogonal to the first direction. A first via electrically connects a first conductive strip in the first plurality of conductive strips in the first layer to a second conductive strip in the plate layer.Type: GrantFiled: November 21, 2008Date of Patent: August 9, 2011Assignee: Xilinx, Inc.Inventor: Patrick J. Quinn
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Publication number: 20110180900Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.Type: ApplicationFiled: April 5, 2011Publication date: July 28, 2011Applicant: PANASONIC CORPORATIONInventors: Koichi HIRANO, Tetsuyosyi Ogura, Seiichi Nakatani
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Publication number: 20110156209Abstract: In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115).Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Byron Lovell Williams, Maxwell Walthour Lippitt, III, Betty Mercer, Scott Montgomery, Binghua Hu
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Patent number: 7960264Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.Type: GrantFiled: October 8, 2010Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventor: Huilong Zhu
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Patent number: 7960773Abstract: This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.Type: GrantFiled: February 3, 2009Date of Patent: June 14, 2011Assignee: Industrial Technology Research InstituteInventors: Shu-Ming Chang, Chia-Wen Chiang
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Publication number: 20110095312Abstract: An object of the present invention is to provide a semiconductor device having high operation characteristic and reliability. The measures taken are: A pixel capacitor is formed between an electrode comprising anodic capable material over an organic resin film, an anodic oxide film of the electrode and a pixel electrode above. Since the anodic oxide film is anodically oxidized by applied voltage per unit time at 15 V/min, there is no wrap around on the electrode, and film peeling can be prevented.Type: ApplicationFiled: October 25, 2010Publication date: April 28, 2011Inventors: Satoshi Murakami, Shunpei Yamazaki, Jun Koyama, Mitsuaki Osamè, Yukio Tanaka, Yoshiharu Hirakata
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Patent number: 7932554Abstract: A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.Type: GrantFiled: June 26, 2007Date of Patent: April 26, 2011Assignee: Hynix Semiconductor Inc.Inventor: Tae Kyun Kim
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Patent number: 7888773Abstract: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.Type: GrantFiled: October 27, 2006Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Jun Won, Jung-Min Park
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Patent number: 7884442Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.Type: GrantFiled: February 26, 2007Date of Patent: February 8, 2011Assignee: Raytheon CompanyInventors: David D. Heston, Jon E. Mooney
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Patent number: 7880267Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.Type: GrantFiled: August 28, 2006Date of Patent: February 1, 2011Assignee: Micron Technology, Inc.Inventor: Badih El-Kareh
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Patent number: 7872329Abstract: Effective area of a capacitor is to be increased while suppressing increase in number of manufacturing steps. In a semiconductor device, a silicon substrate includes a plurality of first recessed portions having a first depth from the main surface thereof, a second recessed portion provided in a region other than the first recessed portion and having a second depth from the main surface, and a third recessed portion provided in at least one of the plurality of first recessed portions and having a third depth from the bottom portion of the first recessed portion. The second recessed portion and the third recessed portion have the same depth, and a decoupling condenser is provided so as to fill the at least one of the first recessed portion and the third recessed portion provided therein, and an isolation insulating layer is provided so as to fill the remaining first recessed portions, and the second recessed portion is filled with a gate electrode.Type: GrantFiled: July 18, 2008Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventor: Kazuhiko Sanada
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Publication number: 20100327410Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.Type: ApplicationFiled: December 30, 2009Publication date: December 30, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Cheol Hwan PARK, Ho Jin CHO, Dong Kyun LEE
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Patent number: 7859081Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.Type: GrantFiled: March 29, 2007Date of Patent: December 28, 2010Assignee: Intel CorporationInventors: Brian S. Doyle, Robert S. Chau, Suman Datta, Vivek De, Ali Keshavarzi, Dinesh Somasekhar
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Patent number: 7851843Abstract: A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.Type: GrantFiled: October 8, 2008Date of Patent: December 14, 2010Assignee: Industrial Technology Research InstituteInventors: Heng-Yuan Lee, Chieh-Shuo Liang, Lurng-Shehng Lee
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Patent number: 7847371Abstract: The present invention aims to provide an electronic component capable of reducing the occurrence of cracks at the joining portion with a board etc. A capacitor 1 (laminated ceramic capacitor) being one example of the electronic component of the present invention is provided with an element assembly 10 (ceramic) and a pair of external electrodes 20 formed on both side surfaces of the element assembly. In the element assembly 10, a dielectric layer 12 and an internal electrode 14 are laminated alternately. The external electrode 14 has such constitution that a first electrode layer connected with the internal electrode 14, a second electrode layer (electroconductive resin layer) including a hardened product of epoxy resin containing an epoxy compound having a molecular weight of 2000 or more and plural epoxy groups as the base compound, a third electrode layer composed of Ni and a fourth electrode layer composed of Sn are formed in this order from the element assembly side.Type: GrantFiled: February 23, 2007Date of Patent: December 7, 2010Assignee: TDK CorporationInventors: Takashi Komatsu, Kouji Tanabe
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Publication number: 20100289120Abstract: In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process.Type: ApplicationFiled: July 26, 2010Publication date: November 18, 2010Inventor: AKIHIKO SATO
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Patent number: 7820488Abstract: A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts to transfer the heat away from the substrate to a heat sink.Type: GrantFiled: October 31, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Sri M. Sri-Jayantha, Gareth Hougham, Sung Kang, Lawrence Mok, Hien Dang, Arun Sharma
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Patent number: 7816762Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.Type: GrantFiled: August 7, 2007Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Eric Thompson
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Publication number: 20100258907Abstract: An exemplary aspect of the invention provides a novel semiconductor device and a method for manufacturing the same.Type: ApplicationFiled: April 5, 2010Publication date: October 14, 2010Applicant: Elpida Memory, Inc.Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
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Publication number: 20100258908Abstract: In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a suicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulatingType: ApplicationFiled: June 24, 2010Publication date: October 14, 2010Inventors: BRIAN S. DOYLE, Dinesh Somasekhar, Robert S. Chau, Suman Datta
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Patent number: 7812425Abstract: A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film.Type: GrantFiled: September 30, 2008Date of Patent: October 12, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Koji Yamakawa, Soichi Yamazaki
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Patent number: 7812450Abstract: The present invention relates to an electrode 100 with high capacitance. The electrode includes a conducting substrate 10 with a number of nano-sized structures 13 thereon and a coating 15. The nano-sized structures are concave-shaped and are of a size in the range from 2 nanometers to 50 nanometers. The nano-sized structures are configured for increasing specific surface area of the electrode. The present invention also provides a method for making the above-described electrode. The method includes steps of providing a conducting substrate, forming a number of nano-sized structures on the conducting substrate, and forming a coating on the nano-sized structures.Type: GrantFiled: March 28, 2006Date of Patent: October 12, 2010Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Ga-Lane Chen
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Patent number: 7795662Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.Type: GrantFiled: July 11, 2007Date of Patent: September 14, 2010Assignee: Panasonic CorporationInventors: Hideyuki Arai, Takashi Nakabayashi
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Publication number: 20100181607Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.Type: ApplicationFiled: March 29, 2010Publication date: July 22, 2010Inventors: Brian S. Doyle, Robert S. Chau, Vivek De, Suman Datta, Dinesh Somasekhar
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Publication number: 20100127351Abstract: A capacitor in an integrated circuit (“IC”) has a first node conductor formed in a first metal layer of the IC with a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to the first direction. A first capital element extends along the first direction, and a first serif element extends from the capital element. The capacitor also has a second node conductor having a second spine, a second vertical element extending from the second spine toward the first spine, a second capital element, and a second serif element extending from the second capital between the first vertical element and the first serif element.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Applicant: Xilinx, Inc.Inventor: Patrick J. Quinn
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Patent number: 7713832Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating pattern over a semiconductor substrate. The interlayer insulating pattern defines a plurality of storage node regions. A lining conductive film is formed over the interlayer insulating pattern including the storage node region. A capping insulating film is formed over the lining conductive film. The capping insulating film over the interlayer insulating film and the lining conductive film are selectively etched between two neighboring storage node regions to form a recess exposing the interlayer insulating pattern on the bottom of the recess and the lining conductive film on sidewalls of the recess. The capping insulating film and the lining conductive film is shaped to be planar so that the lining conductive layer is electrically separated from each other to form a respective lower storage electrode. A supporting pattern is formed to fill the recess.Type: GrantFiled: December 4, 2007Date of Patent: May 11, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Young Deuk Kim
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Publication number: 20100072573Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.Type: ApplicationFiled: December 3, 2009Publication date: March 25, 2010Inventors: David D. Marreiro, Sudhama C. Shastri, Gordon M. Grivna, Earl D. Fuchs
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Patent number: 7675138Abstract: A first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and a second capacitor is formed on the substrate and connected to a second differential node of the differential circuit. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate.Type: GrantFiled: September 30, 2005Date of Patent: March 9, 2010Assignee: Broadcom CorporationInventor: Bo Zhang
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Publication number: 20100044833Abstract: According to the preferred embodiment, an integrated capacitor having a comb-meander structure is provided. The integrated capacitor comprises a first comb-shaped metal pattern; a second comb-shaped metal pattern interdigitating with the first comb-shaped metal pattern; and a meandering metal pattern traversing a spacing between the first and second comb-shaped metal patterns.Type: ApplicationFiled: August 25, 2008Publication date: February 25, 2010Inventors: Tao Cheng, Wen-Lin Chen
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Publication number: 20100032803Abstract: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Maxwell Walthour Lippitt, III, Stephen Arlon Meisner, Lee Alan Stringer, Stephen Fredrick Clark, Fred Percy Debnam, II, Byron Lovell Williams
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Patent number: 7649241Abstract: A semiconductor device having a variable capacitance capacitor and a method of manufacturing the same are disclosed. An example semiconductor device includes a capacitor having a bottom electrode, a dielectric layer and an upper electrode, formed on a semiconductor substrate. The example semiconductor also includes a first insulating layer formed on the semiconductor substrate to cover the capacitor, a plurality of first contact plugs formed in a plurality of first via holes of the first insulating layer, each of which is electrically connected to either the bottom electrode or the upper electrode, a first metal wiring formed on the first insulating layer and connected to the bottom electrode through the first contact plug, a second contact plug formed on the first insulating layer and connected to the upper electrode through the first contact plug, and a second insulating layer formed on the first insulating layer to cover the first metal wiring and the second contact plug.Type: GrantFiled: December 22, 2003Date of Patent: January 19, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Kyung Yun Jung
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Patent number: 7625803Abstract: The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least two prongs. Each of the prongs is surrounded by a lateral periphery. A dielectric material extends around the lateral peripheries of the prongs, and a storage node surrounds an entirety of the lateral peripheries of the prongs. The storage node is separated from the reference plate by at least the dielectric material. Also, the invention includes electronic systems comprising novel capacitor constructions.Type: GrantFiled: February 6, 2006Date of Patent: December 1, 2009Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 7615816Abstract: A buried plate region for a semiconductor memory storage capacitor is self aligned with respect to an upper portion of a deep trench containing the memory storage capacitor.Type: GrantFiled: March 28, 2007Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ramachandra Divakaruni, Chun-Yung Sung
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Patent number: 7598592Abstract: A capacitor structure for an integrated circuit. An insulating layer is disposed on a substrate. A first conductive line is embedded in a first level of the insulating layer. A second conductive line is embedded in a second level of the insulating layer lower than the first level and has a projection onto the substrate completely covered by the first conductive line. A third conductive line is embedded in the second level of the insulating layer and separated from the second conductive line by a predetermined space, and has a projection onto the substrate partially covered by the first conductive line. The second conductive line is coupled to the first conductive line by at least one first conductive plug and has a polarity opposite to the third conductive line.Type: GrantFiled: February 16, 2007Date of Patent: October 6, 2009Assignee: Via Technologies, Inc.Inventors: Chun-Sheng Chen, Ying-Che Tseng
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Patent number: 7582901Abstract: An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.Type: GrantFiled: February 17, 2005Date of Patent: September 1, 2009Assignee: Hitachi, Ltd.Inventors: Kenichi Takeda, Tsuyoshi Fujiwara, Toshinori Imai, Tsuyoshi Ishikawa, Toshiyuki Mine, Makoto Miura
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Patent number: 7573121Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.Type: GrantFiled: August 31, 2006Date of Patent: August 11, 2009Assignee: Micron Technology, Inc.Inventors: Donald L Yates, Garry A Mercaldi, James J Hofmann
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Patent number: 7573118Abstract: A programming method of a MOS electric fuse including preparing, as a fuse element, a MOS transistor which has a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region, and applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the first impurity region, and short-circuiting the gate dielectric film only between the gate electrode and the first impurity region.Type: GrantFiled: July 12, 2007Date of Patent: August 11, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Kushida
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Publication number: 20090189251Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.Type: ApplicationFiled: April 11, 2008Publication date: July 30, 2009Inventors: Yu-Wei Ting, Shing-Hwa Renn, Yu-Teh Chiang, Chung-Ren Li, Tieh-Chiang Wu
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Patent number: 7564089Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate, and including a bottom electrode, a dielectric film formed on the bottom electrode, and a top electrode formed on the dielectric film and having a plurality of hole patterns.Type: GrantFiled: August 5, 2004Date of Patent: July 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Yamazaki, Katsuaki Natori, Koji Yamakawa
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Patent number: 7557398Abstract: The compensation capacitor includes: a charge accumulating element having a diffusion layer, a dielectric layer, and a gate electrode layer, wherein the gate electrode layer, the dielectric layer, and the diffusion layer are stacked in this order, and at least partially overlap with each other when viewed from a direction of stacking; a metal layer for applying a voltage to the diffusion layer, the metal layer being formed above the charge accumulating element; and a contact for electrically connecting the diffusion layer and the metal layer, the contact extending between the diffusion layer and the metal layer in the direction of stacking. The gate electrode layer has a form of a mesh which extends in a direction which is perpendicular to the direction of stacking. The contact extends through an aperture of the mesh of the gate electrode layer.Type: GrantFiled: April 11, 2006Date of Patent: July 7, 2009Assignee: Elpida Memory, Inc.Inventor: Ken Ota
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Patent number: 7557426Abstract: A semiconductor component including an integrated capacitor structure having at least two groups of at least partly electrically conductive planes and which is patterned in such a way that in at least each group of planes at least one plane has a plurality of strip elements, first strip elements including a first polarity of the capacitor structure and second strip elements including a second polarity of the capacitor structure, the first strip elements together with second strip elements being at least partly interlinked in one another and strip elements of the same polarity at least partly overlapping in at least two planes, the first group of planes being electrically conductively connected by way of vertical connections (vias) to strip elements of the same polarity of the second group of planes, the strip elements of the same polarity of the second group of planes being interconnected with lateral connecting elements.Type: GrantFiled: September 29, 2006Date of Patent: July 7, 2009Assignee: Infineon Technologies AGInventors: Peter Baumgartner, Phillip Riess
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Patent number: 7554172Abstract: An electrode plate for an electricity storage and discharge device, which includes a plurality of I/O convergence terminals evenly distributed along a periphery of the electrode plate, and a plurality of conductive structures, each conductive structure for one of the I/O convergence terminals, wherein each conductive structure is of a radial pattern that centers on the one of the I/O convergence terminals, and radiates towards the interior of the electrode plate.Type: GrantFiled: April 7, 2005Date of Patent: June 30, 2009Inventor: Tai-Her Yang
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Publication number: 20090121318Abstract: A semiconductor device with a multi-layer wiring structure includes a first conductive region: a second conductive region that has an upper surface located in a higher position than the first conductive region with respect to the substrate; an insulating that covers the first and second conductive regions; a wiring groove that is formed in the insulating film so as to expose the second conductive region; a contact hole that is formed in the insulating film so as to expose the first conductive region; and a wiring pattern that fills the wiring groove and the contact hole. In this semiconductor device, the upper surface of the wiring pattern is located on the same plane as the upper surface of the insulating film.Type: ApplicationFiled: October 15, 2008Publication date: May 14, 2009Applicant: FUJITSU LIMITEDInventor: Taiji Ema
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Publication number: 20090085161Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: ApplicationFiled: February 13, 2008Publication date: April 2, 2009Applicant: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Publication number: 20090039467Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.Type: ApplicationFiled: August 7, 2007Publication date: February 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil K. Chinthakindi, Eric Thompson
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Publication number: 20090001516Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating pattern over a semiconductor substrate. The interlayer insulating pattern defines a plurality of storage node regions. A lining conductive film is formed over the interlayer insulating pattern including the storage node region. A capping insulating film is formed over the lining conductive film. The capping insulating film over the interlayer insulating film and the lining conductive film are selectively etched between two neighboring storage node regions to form a recess exposing the interlayer insulating pattern on the bottom of the recess and the lining conductive film on sidewalls of the recess. The capping insulating film and the lining conductive film is shaped to be planar so that the lining conductive layer is electrically separated from each other to form a respective lower storage electrode. A supporting pattern is formed to fill the recess.Type: ApplicationFiled: December 4, 2007Publication date: January 1, 2009Inventor: Young Deuk Kim
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Patent number: 7462912Abstract: Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.Type: GrantFiled: February 24, 2006Date of Patent: December 9, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Soon-Hong Ahn, Jung-Hwa Lee