Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

Abstract: Provided is an alkylsilane laminate with which it is possible to obtain an organic semiconductor film having excellent semiconductor properties. Such a laminate can be useful for an organic thin-film transistor. The alkylsilane laminate comprises an underlayer (Sub) having hydroxyl groups at the surface and an alkylsilane thin film (AS) formed on this underlayer. The alkylsilane laminate is a laminate wherein the critical surface energy Ec of the alkylsilane thin film and the number of carbons (X) of the alkylsilane satisfies the following formula (1): Ec?29.00?0.63x (mN/m) (1) Also provided is a thin-film transistor (10) having such an alkylsilane laminate (Sub, AS).

Abstract: A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.

Abstract: A thin-film semiconductor device manufacturing method according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating film above the substrate; forming an amorphous film (amorphous silicon film) above the substrate; forming a crystalline film (crystalline silicon film) including a first crystal and a second crystal, by crystallizing the amorphous film, the first crystal (i) containing subgrains formed with different crystal orientations in a single crystal and (ii) including a subgrain boundary formed by plural crystal planes between the subgrains, the second crystal having an average crystal grain size smaller than an average crystal grain size of the first crystal; thinning the crystalline film; and forming a source electrode and a drain electrode above the substrate.

Abstract: A method for forming a polycrystalline film, a polycrystalline film formed by the method and a thin film transistor fabricated from the polycrystalline film are provided. The method comprises the steps of: providing a substrate; forming a thermal conductor layer on the substrate; etching the thermal conductor layer until the substrate is exposed to form a thermal conductor pattern; forming a seed layer on the thermal conductor layer and the substrate; etching the seed layer to form seed crystals on both sidewalls of the thermal conductor; forming an amorphous layer on the substrate, the thermal conductor layer and the seed crystals; etching the amorphous layer; and recrystallizing the amorphous layer to form a polycrystalline layer.

Abstract: The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

Abstract: The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.

Abstract: Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole.

Abstract: A thin film transistor, a method of manufacturing the same, and a display device including the same, the thin film transistor including a substrate; a polysilicon semiconductor layer on the substrate; and a metal pattern between the semiconductor layer and the substrate, the metal pattern being insulated from the semiconductor layer, wherein the polysilicon of the semiconductor layer includes a grain boundary parallel to a crystallization growing direction, and a surface roughness of the polysilicon semiconductor layer defined by a distance between a lowest peak and a highest peak in a surface thereof is less than about 15 nm.

Abstract: A method of fabricating a semiconductor device that includes providing a gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, and forming an amorphous semiconductor layer on at least a source region portion and a drain region portion of the SOI layer. The amorphous semiconductor layer is converted to a crystalline semiconductor material, wherein the crystalline semiconductor material provides a raised source region and a raised drain region of the semiconductor device. The method may be applicable to planar semiconductor devices and finFET semiconductor devices.

Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.

Abstract: A method of fabricating a semiconductor device that includes providing a gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, and forming an amorphous semiconductor layer on at least a source region portion and a drain region portion of the SOI layer. The amorphous semiconductor layer is converted to a crystalline semiconductor material, wherein the crystalline semiconductor material provides a raised source region and a raised drain region of the semiconductor device. The method may be applicable to planar semiconductor devices and finFET semiconductor devices.

Abstract: A thin film transistor is provided. In this thin film transistor, the thickness of the gate is increased. Therefore, the source and drain of this thin film transistor can be disposed on the side wall of the gate to decrease the occupied area of the thin film transistor. An array substrate and a display device using the thin film transistor are also provided.

Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.

Abstract: A thin film transistor and a method for fabricating the same are disclosed. The thin film transistor includes: a gate electrode formed on a substrate and having a plurality of horizontal electrode parts spaced apart at regular intervals; a gate insulating film formed over the entire surface of the substrate including the gate electrode; an active pattern formed on the gate insulating film above the plurality of horizontal electrode parts; an etch stop film pattern formed above the active pattern and the gate insulating film so as to overlap top portions of the active pattern and the gate electrode and; a source electrode formed on the active pattern, the gate insulating film, and the etch stop film pattern so as to overlap top portions of adjacent horizontal electrode parts; and a drain electrode formed on the active pattern, the gate insulating film, and the etch stop film pattern so as to overlap top portions of horizontal electrode parts located on the outermost ends.

Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.

Abstract: A display substrate having a low resistance signal line and a method of manufacturing the display substrate are provided. The display substrate includes an insulation substrate, a gate line, a data line and a pixel electrode. The gate line gate line is formed through a sub-trench and an opening portion. The sub-trench is formed in the insulation substrate and the opening portion is formed through a planarization layer on the insulation substrate at a position corresponding to the position of the sub-trench. The data line crosses the gate line. The pixel electrode is electrically connected to the gate line and the data line through a switching element. Thus, a signal line is formed through a trench formed by using a planarization layer and an insulation substrate, so that a resistance of the signal line may be reduced.

Abstract: A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing.

Abstract: A method of manufacturing a thin film transistor includes: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an organic semiconductor layer on the gate insulating layer; forming an organic semiconductor pattern by selectively removing part of the organic semiconductor layer by means of a laser ablation method; and forming source and drain electrodes on the organic semiconductor pattern.

Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating film, and a control electrode. The first semiconductor region includes a silicon carbide of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, includes a silicon carbide of a second conductivity type, and has a first main surface. The third semiconductor region is provided on the second semiconductor region and includes the silicon carbide of the first conductivity type. The film is provided on the surface. The electrode is provided on the film, and has a first region close to the third semiconductor region side, and a second region closer to the first semiconductor region side than the first region. An effective work function of is the first region is larger than an effective work function of the second region.

Abstract: A photosensor includes a sensing switching element, a sensing element, and a reset switching element. The sensing switching element includes an output terminal connected to a sensing signal line, a control terminal connected to a first gate line, and an input terminal connected to the first node. The sensing element includes an output terminal connected to a first node, a control terminal connected a second gate line disposed next to the first gate line, and an input terminal connected to a source voltage line transmitting a source voltage. The sensing element senses light. The reset switching element includes an output terminal connected to the first node, a control terminal connected to the second gate line, and an input terminal connected to a driving voltage line transmitting a driving voltage.

Abstract: There are provided a TFT, a TFT substrate using the TFT, a method of fabricating the TFT substrate, and an LCD. The TFT includes a source region, a drain region, and a gate electrode having an opening. The opening of the gate electrode is to enhance the light sensing ability of the TFT when it is used as a light sensor, since light is incident into a region where the opening is formed. The TFT including the gate having the opening can be used in a substrate of a flat display or an LCD using such a substrate. The above TFT can sense light incident from outside the display to adjust the brightness of the screen according to the external illumination.

Abstract: A thin film transistor includes nanowires. More specifically, the thin film transistor includes nanowires aligned between and extending to opposite facing lateral surfaces of source/drain electrodes on a substrate. The nanowires extend in a direction parallel to a major surface defining the substrate to form a semiconductor channel layer. Also disclosed herein is a method for fabricating the thin film transistor.

Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.

Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer; a charge storage film that is formed on the first insulating film, includes C60 fullerenes, and is not less than 0.5 monolayer but is less than 1.0 monolayer; a second insulating film formed on the charge storage film; and a control electrode formed on the second insulating film.

Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

Abstract: An object is to provide a light-emitting device having a structure in which an external connection portion can easily be connected and a method for manufacturing the light-emitting device. A light-emitting device includes a lower support 110, a base insulating film 112 over the lower support 110 which has a through-hole 130, a light-emitting element 127 over the base insulating film 112, and an upper support 122 over the light-emitting element 127. An electrode 131 is provided in the through-hole 130, and the external connection terminal 132 electrically connected to the electrode 131 is provided below the base insulating film 112. The external connection terminal 132 is electrically connected to the external connection portion 133 and functions as a terminal that inputs a signal or a power supply into the light-emitting device. This light-emitting device has a structure in which an external connection portion can easily be connected.

Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

Abstract: It is an object of the present invention to provide a semiconductor device capable of preventing deterioration due to penetration of moisture or oxygen, for example, a light-emitting apparatus having an organic light-emitting device that is formed over a plastic substrate, and a liquid crystal display apparatus using a plastic substrate. According to the present invention, devices formed on a glass substrate or a quartz substrate (a TFT, a light-emitting device having an organic compound, a liquid crystal device, a memory device, a thin-film diode, a pin-junction silicon photoelectric converter, a silicon resistance element, or the like) are separated from the substrate, and transferred to a plastic substrate having high thermal conductivity.

Abstract: Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer.

Abstract: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode is performed by the same photomask as that used for forming a channel etch type TFT, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics.

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract: A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 ? to 800 ?. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer.

Abstract: A thin film transistor includes a substrate, a source electrode and a drain electrode formed on the substrate, a channel layer formed between the source electrode and the drain electrode, an insulative layer covering the channel layer and a gate electrode formed on the insulative layer. An atomic-doping layer is formed in the channel layer. The atomic-doping layer is delta-doping with no more than one layer of atom.

Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a silicon carbide film are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the silicon carbide film is formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.

Abstract: An organic light emitting diode (OLED) display device and method of fabrication that includes a substrate having a device region, an outer dam region and an encapsulation region. The encapsulation region includes an inner dam region, an outer dam region and an encapsulation region that correspond to the device region. An encapsulation agent is formed in the encapsulation region of the encapsulation substrate, and filling dams are formed of the same material in the outer dam region and the inner dam region of the encapsulation substrate.

Abstract: A light-emitting device includes a drive transistor for controlling the quantity of current supplied to a light-emitting element, a capacitor element electrically connected to a gate electrode of the drive transistor, and an electrical continuity portion for electrically connecting the drive transistor and the light-emitting element, these elements being disposed on a substrate. The electrical continuity portion is disposed on the side opposite to the capacitor element with the drive transistor disposed therebetween.

Abstract: A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

Abstract: A dielectric layer for an electronic device, such as a thin-film transistor, is provided. The dielectric layer comprises a molecular glass. The resulting dielectric layer is very thin, pure, and stable. Processes and compositions for fabricating such a dielectric layer are also disclosed.

Abstract: A thin film transistor device includes a first conductivity type thin film transistor and a second conductivity type thin film transistor. The first conductivity type thin film transistor includes a first patterned doped layer, a first gate electrode, a first source electrode, a first drain electrode and a first semiconductor pattern. The second conductivity type thin film transistor includes a second patterned doped layer, a second gate electrode, a second source electrode, a second drain electrode and a second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern form a patterned semiconductor layer. The first patterned doped layer is disposed under the first semiconductor pattern, and the second patterned doped layer is disposed on the second semiconductor pattern.

Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.

Abstract: A thin film transistor (TFT) and an organic light emitting display apparatus are provided. The TFT includes: a substrate; a gate electrode on the substrate; an active layer insulated from the gate electrode; source/drain electrodes electrically connected to the active layer; a first insulating film on the source/drain electrodes; a light blocking layer on the first insulating film; and a second insulating film on the light blocking layer.

Abstract: A thin film transistor, a method of fabricating the thin film transistor, and an organic light emitting diode (OLED) display device equipped with the thin film transistor of which the thin film transistor includes a substrate, a buffer layer disposed on the substrate, a first semiconductor layer and a second semiconductor layer disposed on the buffer layer, a gate electrode insulated from the first semiconductor layer and the second semiconductor layer, a gate insulating layer insulating the gate electrode from the first semiconductor layer and the second semiconductor layer, and source and drain electrodes insulated from the gate electrode and partially connected to the second semiconductor layer, wherein the second semiconductor layer is disposed on the first semiconductor layer.

Abstract: A thin film transistor is provided. The thin film transistor disposed on a substrate includes a gate electrode, a gate dielectric layer, a patterned semiconductor layer, a source electrode, a drain electrode covered with an anticorrosive conductive layer, a patterned passivation layer and a transparent conductive layer. The anticorrosive conductive layer includes indium tin oxide or indium zinc oxide, and is used to prevent the drain electrode from being over etched during the process of etching the passivation layer. A method for manufacturing the thin film transistor is also provided herein.

Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.

Abstract: The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.

Abstract: The present invention provides an inexpensive display device that includes an ion sensor portion and a display and that can be miniaturized. The present invention is a display device that includes an ion sensor portion including an ion sensor circuit and a display including a display-driving circuit. The display device has a substrate, and at least one portion of the ion sensor circuit and at least one portion of the display-driving circuit are formed on the same main surface of the substrate.

Abstract: An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, the exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region, wherein a data line crosses the gate line to define the pixel region and is connected to the source electrode, a passivation layer on the source and drain electrodes and the data line.