Abstract: Provided is a thin film semiconductor device such as an organic light-emitting display which includes a thin film transistor (TFT) having a lightly doped region. The thin film semiconductor includes a substrate, a first active pattern, a first lower conductive pattern, and a first upper conductive pattern. The first active pattern is disposed on the substrate and includes a channel region, a lightly doped region, and a heavily doped region. The first lower conductive pattern is disposed on the first active pattern and covers the channel region. The first upper conductive pattern is disposed on the first lower conductive pattern and covers the channel region and the lightly doped region.

Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

Abstract: According to an aspect of the present invention, there is provided a thin-film transistor (TFT) sensor, including a bottom gate electrode on a substrate, an insulation layer on the bottom gate electrode, an active layer in a donut shape on the insulation layer, the active layer including a channel through which a current generated by a charged body flows, an etch stop layer on the active layer, the etch stop layer including a first contact hole and a second contact hole, and a source electrode and a drain electrode burying the first and second contact holes, the source and drain electrodes being disposed on the etch stop layer so as to face each other.

Abstract: A thin film transistor comprises a semiconductor layer; first and second dielectric layers disposed on opposite sides of the semiconductor layer; a first metal layer forming first and second terminals on the opposite side of the first dielectric layer from the semiconductor layer, one of said first and second terminals extending through said first dielectric layer into contact with the semiconductor layer, the first and second terminals and the first dielectric layer forming a capacitor; and a second metal layer forming a third terminal on the opposite side of the second dielectric layer from the semiconductor layer. The first and second terminals may be source and drain terminals, and the third terminal may be a gate terminal. The first metal layer may be divided to form the first and second terminals. The third terminal may be shared with one of the first and second terminals.

Abstract: To reduce parasitic capacitance between a gate electrode and a source electrode or drain electrode of a dual-gate transistor. A semiconductor device includes a first insulating layer covering a first conductive layer; a first semiconductor layer, second semiconductor layers, and an impurity semiconductor layer sequentially provided over the first insulating layer; a second conductive layer over and at least partially in contact with the impurity semiconductor layer; a second insulating layer over the second conductive layer; a third insulating layer covering the three semiconductor layers, the second conductive layer, and the second insulating layer; and a third conductive layer over the third insulating layer. The third conductive layer overlaps with a portion of the first semiconductor layer, which does not overlap with the second semiconductor layers, and further overlaps with part of the second conductive layer.

Abstract: A display device includes a display area and a terminal area formed outside the display area. The display area has a plurality of scanning lines and a plurality of video signal lines that cross the scanning lines. The terminal area has a first terminal having a semiconductor chip connected thereto, a first line, a second line, and an inspection thin-film transistor. The inspection thin-film transistor has a gate electrode connected to the first line, a source electrode connected to the second line, and a drain electrode. The first terminal is connected to any of the plurality of scanning lines and the plurality of video signal lines.

Abstract: A thin-film transistor device includes a gate electrode formed above a substrate, a gate insulating film formed on the gate electrode, a crystalline silicon thin film that is formed above the gate insulating film and has a channel region, an amorphous silicon thin film formed on the crystalline silicon thin film, and a source electrode and a drain electrode that are formed above the channel region, and the crystalline silicon thin film has a half-width of a Raman band corresponding to a phonon mode specific to the crystalline silicon thin film of 5.0 or more and less than 6.0 cm?1, and an average crystal grain size of about 50 nm or more and 300 nm or less.

Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.

Abstract: A field effect transistor including a semiconductor layer including a composite oxide which contains In, Zn, and one or more elements X selected from the group consisting of Zr, Hf, Ge, Si, Ti, Mn, W, Mo, V, Cu, Ni, Co, Fe, Cr, Nb, Al, B, Sc, Y and lanthanoids in the following atomic ratios (1) to (3): In/(In+Zn)=0.2 to 0.8??(1) In/(In+X)=0.29 to 0.99??(2) Zn/(X+Zn)=0.29 to 0.99??(3).

Abstract: A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

Abstract: An IR sensing transistor according to an exemplary embodiment of the present invention includes: a light blocking layer formed on a substrate; a gate insulating layer formed on the light blocking layer; a semiconductor formed on the gate insulating layer; a pair of ohmic contact members formed on the semiconductor; a source electrode and a drain electrode formed on respective ones of the ohmic contact members; a passivation layer formed on the source electrode and the drain electrode; and a gate electrode formed on the passivation layer, wherein substantially all of the gate insulating layer lies on the light blocking layer.

Abstract: A method for forming a polycrystalline film, a polycrystalline film formed by the method and a thin film transistor fabricated from the polycrystalline film are provided. The method comprises the steps of: providing a substrate; forming a thermal conductor layer on the substrate; etching the thermal conductor layer until the substrate is exposed to form a thermal conductor pattern; forming a seed layer on the thermal conductor layer and the substrate; etching the seed layer to form seed crystals on both sidewalls of the thermal conductor; forming an amorphous layer on the substrate, the thermal conductor layer and the seed crystals; etching the amorphous layer; and recrystallizing the amorphous layer to form a polycrystalline layer.

Abstract: A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate.

Abstract: A thin film transistor substrate includes a base substrate, a gate electrode, a gate insulating layer, a surface treating layer, an active layer, a source electrode and a drain electrode. The gate electrode is formed on the base substrate. The gate insulating layer is formed on the base substrate to cover the gate electrode. The surface treating layer is formed on the gate insulating layer by treating the gate insulating layer with a nitrogen-containing gas to prevent leakage current. The active layer is formed on the surface treating layer to cover the gate electrode. The source electrode and the gate electrode that are spaced apart from each other by a predetermined distance are formed on the active layer.

Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region.

Abstract: Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled.

Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.

Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract: A thin film transistor for increasing the conductivity of a channel region and suppressing the leakage current of a back channel region, and a display device including the thin film transistor, are discussed. According to an embodiment, the thin film transistor includes a gate electrode arranged on a substrate, a source electrode and a drain electrode spaced from each other on the substrate, a gate insulating film to insulate the gate electrode from the source electrode and the drain electrode, and a semiconductor layer insulated from the gate electrode through the gate insulating film, the semiconductor layer including a channel region and a back channel region, the semiconductor layer made of (In2O3)x(Ga2O3)y(ZnO)z(0?x?5, 0?y?5, 0?z?5), wherein X or Z is greater than Y in the channel region of the semiconductor layer, and Y is greater than X and Z in the back channel region of the semiconductor layer.

Abstract: A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.

Abstract: The present invention provides a photovoltaic cell having a large short-circuit current density and a large photoelectric conversion efficiency.

Abstract: A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.

Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

Abstract: A thin film transistor and a manufacturing method for the same, an array substrate, and a display device are disclosed. The thin film transistor comprises: a substrate (1) and a gate (2), a first gate insulating layer (3) and an active layer (4) which are disposed in order on the substrate, the first gate insulating layer (3) covers the gate (2), the active layer (4) covers the first gate insulating layer (3), and a material for the first gate insulating layer comprises aluminum oxide.

Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.

Abstract: A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.

Abstract: According to embodiments of the invention, there are provided a TFT array substrate, a manufacturing method thereof and a liquid crystal display. The manufacturing method comprises manufacturing a pattern including a gate electrode, a gate insulating layer pattern with a via hole, a pattern including an active layer, a pattern including source and drain electrodes and a pattern including a first electrode on a substrate. The formation of the gate insulating layer pattern with the via hole and the pattern including the active layer are completed through one patterning process, the pattern including the gate electrode at least includes the gate electrode and a gate leading wire, the via hole of the gate insulating layer is located over the gate leading wire, and the active layer is located over the gate electrode.

Abstract: A thin film transistor, comprising: a substrate; a first electrode formed on the substrate; a first insulation layer formed on the first electrode; a gate electrode formed on the first insulation layer; a second insulation layer formed on the gate electrode; an active layer penetrating through the first and second insulation layers and electrically isolated from the gate electrode; and a second electrode formed on the active layer and electrically connected to the first electrode through the active layer, wherein the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode.

Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.

Abstract: A semiconductor device, disposed on a substrate, includes a first channel layer, a patterned doped layer, a gate insulating layer, a conducting gate electrode, a second channel layer, a first electrode and a second electrode, and a third electrode and a fourth electrode. The first channel layer is disposed on the substrate and in a first region. The patterned doped layer includes a doped gate electrode disposed in a second region, and two contact electrodes electrically connected to two sides of the first channel layer, respectively. The conducting gate electrode is disposed on the gate insulating layer in the first region. The second channel layer is disposed on the gate insulating layer in the second region. The first electrode and the second electrode are electrically connected to the contact electrodes, respectively. The third electrode and the fourth electrode are electrically connected to two sides of the second channel layer, respectively.

Abstract: A vertical thin film transistor includes a substrate, a first wall, a second wall, a source electrode, a drain electrode, a semiconductor layer, a gate insulating layer, and a gate electrode. The first wall and the second walls are spaced apart from each other on the substrate. The source electrode is formed on a top surface of the first wall. The drain electrode is provided on the substrate between the first and second walls. The semiconductor layer is formed on the source electrode, a sidewall of the first wall, and the drain electrode. The gate insulating layer covers the first and second walls, the source and drain electrodes, and the semiconductor layer. The gate electrode is disposed between the first and second walls in a planar view. The vertical thin film transistor may be formed without a mask.

Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.

Abstract: Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.

Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.

Abstract: The present invention provides a method of an active-matrix thin film transistor array, comprising of two levels of metallic interconnections formed from one layer of metallic conductor; and thin-film transistors with source, drain and gate electrodes either fully or partially replaced with metal, and wherein the pixel electrodes are polycrystalline silicon.

Abstract: A thin film transistor includes: a source region; a drain region; and a polycrystalline thin film active channel region connected to the source region and the drain region, the active channel region comprising grains and being doped with a two-dimensional pattern comprising a plurality of doped regions, the plurality of doped regions each comprising at least portions of a plurality of the grains and at least one grain boundary.

Abstract: A method for manufacturing a thin-film transistor, includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; removing at least a portion of a region of an altered layer, the region contacting the semiconductor layer, the altered layer being a surface layer of the protective layer that is altered by the dry etching; and forming a passivation layer having a major component identical to a major component of the protective layer so as to contact the semiconductor layer in a region in which the altered layer has been removed.

Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.

Abstract: One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.

Abstract: A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film.

Abstract: It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it is possible to reduce the voltage drop and a deadened signal.

Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.

Abstract: Disclosed is a fullerene derivative having a formula of F-Cy, wherein F is an open-cage fullerene, and Cy is a chalcogenyl group. The fullerene derivative can be applied to hydrogen storage material and an optoelectronic device such as an organic light emitting diode (OLED), a solar cell, or an organic thin film transistor (TFT).

Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a pair of silicon carbide films are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the pair of silicon carbide films are formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.

Abstract: Provided are an electronic device and methods of fabricating the same, the electronic device include a device-substrate, a stacked structure, and an electrode. The stacked structure includes a graphene thin film between a first insulator and a second insulator. The electrode is disposed over the stacked structure.

Abstract: According to present invention, system on panel without complicating the process of TFT can be realized, and a light-emitting device that can be formed by lower cost than that of the conventional light-emitting device can be provided. A light-emitting device is provided in which a pixel portion is provided with a pixel including a light-emitting element and a TFT for controlling supply of current to the light-emitting element; a TFT included in a drive circuit and a TFT for controlling supply of current to the light-emitting element include a gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor film, which overlaps with the gate electrode via the gate insulating film, a pair of second semiconductor films formed over the first semiconductor film; the pair of second semiconductor films are doped with an impurity to have one conductivity type; and the first semiconductor film is formed by semiamorphous semiconductor.

Abstract: A pixel unit, comprising: an active area pixel electrode and a passive area pixel electrode disposed in the same layer; a thin film transistor switch electrically connected to the active area pixel electrode; and a coupling electrode disposed in a different layer from the active area pixel electrode and electrically connected to the active area pixel electrode, wherein the coupling electrode and the passive area pixel electrode are arranged to be at least partly overlapped with each other to form a coupling capacitance. The present invention also discloses an array substrate comprising the pixel unit and a liquid crystal display comprising the array substrate.

Abstract: A semiconductor device according to an embodiment includes: first and second semiconductor regions each having a protruded shape provided on a substrate, the first semiconductor region including a first source, a first drain, and a first channel provided between the first source and the first drain and extending in a first direction from the first source to the first drain, the first channel having a first width in a second direction perpendicular to the first direction, and the second semiconductor region including a second source, a second drain, and a second channel provided between the second source and the second drain and extending in a third direction from the second source to the second drain, the second channel having a second width in a fourth direction perpendicular to the third direction that is wider than the first width of the first channel.

Abstract: A method for producing a low temperature polycrystalline silicon thin film, comprising steps of: providing a substrate; forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film, wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate.