Field Effect Device In Non-single Crystal, Or Recrystallized, Semiconductor Material Patents (Class 257/66)
  • Publication number: 20140034956
    Abstract: An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 6, 2014
    Applicant: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Cheng Hu, Lun Zhu, Zhiwei Zhu, Shili Zhang, Wei Zhang
  • Publication number: 20140034955
    Abstract: The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 6, 2014
    Applicant: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Cheng Hu, Luo Zhu, Zhiwei Zhu, Shili Zhang, Wei Zhang
  • Publication number: 20140034951
    Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm3 to about 4E23 atoms/cm3. The source and the drain are connected with the silicon-rich channel layer.
    Type: Application
    Filed: October 8, 2013
    Publication date: February 6, 2014
    Applicant: Au Optronics Corporation
    Inventors: An-Thung Cho, Wan-Yi Liu, Chia-Kai Chen, Wu-Hsiung Lin, Chun-Hsiun Chen, Wei-Ming Huang
  • Patent number: 8643015
    Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yu Yamazaki, Jun Koyama, Takayuki Ikeda, Hiroshi Shibata, Hidehito Kitakado, Takeshi Fukunaga
  • Patent number: 8642402
    Abstract: To provide a method for producing a thin film transistor improved in stability, uniformity, reproducibility, heat resistance, durability or the like, a thin film transistor, a thin film transistor substrate, an image display apparatus, an image display apparatus and a semiconductor device. In the semiconductor device, a crystalline oxide is used as an N-type transistor and the electron carrier concentration of the crystalline oxide is less than 2×1017/cm3. Furthermore, the crystalline oxide is a polycrystalline oxide containing In and one or more positive divalent elements selected from Zn, Mg, Cu, Ni, Co and Ca, and the atomic ratio In [In] and the positive divalent element [X][X]/([X]+[In]) is 0.0001 to 0.13.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: February 4, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue, Futoshi Utsuno, Masashi Kasami
  • Patent number: 8643021
    Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame, Takashi Hirosure, Saishi Fujikawa
  • Publication number: 20140027717
    Abstract: Pixel control structure for use in a backplane for an electronic display, including a transistor that has a gate, a source, a drain, and an organic semiconductor element. The pixel control structure is formed by a first patterned conductive layer portion, a second patterned conductive layer portion, a dielectric layer portion, and an organic patterned semiconductive layer portion. The dielectric layer portion comprises an overlap region defined by overlap of the second conductive layer portion over the first conductive layer portion. The overlap region defines an overlap boundary, defined by an edge portion of the first patterned conductive layer portion and an edge portion of the second patterned conductive layer portion. The patterned semiconductive layer portion extends over the overlap region and away from the overlap region so as to extend from both first and second edge portions.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: Polymer Vision B.V.
    Inventors: Nick A.J.M. van Aerle, Erik Van Veenendaal, Pieter Van Lieshout, Christoph Wilhelm Sele, Joris P.V. Maas
  • Patent number: 8637866
    Abstract: A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshiyuki Isa, Yasuhiro Jinbo, Sachiaki Tezuka, Koji Dairiki, Hidekazu Miyairi, Shunpei Yamazaki, Takuya Hirohashi
  • Publication number: 20140021473
    Abstract: A semiconductor structure includes a gate, an oxide channel layer, a gate insulating layer, a source, a drain and a dielectric stacked layer. The oxide channel layer is stacked over the gate, with the gate insulting layer disposed therebetween. The source and the drain are disposed on a side of the oxide channel layer and in parallel to each other. A portion of the oxide channel layer is exposed between the source and the drain. The dielectric stacked layer is disposed on the substrate and includes plural of first inorganic dielectric layers with a first refraction index and plural of second inorganic dielectric layers with a second refraction index that are stacked alternately. At least one of the first inorganic dielectric layers directly covers the source, the drain and the portion of the oxide channel layer. The first refraction index is smaller than the second refraction index.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 23, 2014
    Applicant: E INK HOLDINGS INC.
    Inventors: Tzung-Wei Yu, Fang-An Shu, Yao-Chou Tsai, Kuan-Yi Lin
  • Publication number: 20140021477
    Abstract: Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form.
    Type: Application
    Filed: January 25, 2013
    Publication date: January 23, 2014
    Inventor: Venkatraman PRABHAKAR
  • Patent number: 8633484
    Abstract: An organic light emitting display and method of fabricating thereof, the display including a substrate including a first thin film transistor region and a second thin film transistor region; a buffer layer on the substrate; a first and a second semiconductor layer on the buffer layer; a gate insulating layer on the substrate; gate electrodes on the gate insulating layer and corresponding to the first semiconductor layer and the second semiconductor layer, respectively; source/drain electrodes insulated from the gate electrode and being connected to the first semiconductor layer and the second semiconductor layer, respectively; an insulating layer on the substrate; a first electrode connected to the source/drain electrode electrically connected to the first semiconductor layer; an organic layer on the first electrode; and a second electrode on the organic layer, wherein portions of the buffer layer corresponding to a source/drain region of the first semiconductor layer include a metal catalyst.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: January 21, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Lee, Tae-Hoon Yang, Bo-Kyung Choi, Byoung-Kwon Choo, Kyu-Sik Cho, Yong-Hwan Park, Sang-Ho Moon, Min-Chul Shin, Yun-Gyu Lee, Joon-Hoo Choi
  • Patent number: 8633523
    Abstract: A thin film transistor which may be included in a pixel circuit includes: a substrate; a semiconductor layer formed on the substrate and including a source region, a first drain region spaced apart from the source region by a first current path, and a second drain region spaced apart from the source region by a second current path having a length different from that of the first current path; a gate electrode insulated from the semiconductor layer by a gate insulating layer; a source electrode connected to the source region of the semiconductor layer; a first drain electrode connected to the first drain region of the semiconductor layer; and a second drain electrode connected to the second drain region of the semiconductor layer. Currents having different magnitudes may be simultaneously provided through the first current path and the second current path.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: January 21, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Woo Park, Dong-Hwan Kim
  • Patent number: 8633485
    Abstract: To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a second semiconductor layer provided over the first semiconductor layer and having an amorphous semiconductor, and a source region and a drain region provided over the second semiconductor layer are provided. The first semiconductor layer has high crystallinity than the second semiconductor layer. The second semiconductor layer includes an impurity region having a conductivity type different from a conductivity type of the source region and the drain region between the source region and the drain region.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Kobayashi, Yoshiyuki Kurokawa, Shunpei Yamazaki, Daisuke Kawae
  • Publication number: 20140014964
    Abstract: In a semiconductor device, gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 16, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Yosuke Tsukamoto, Tomoaki Atsumi, Masayuki Sakakura
  • Patent number: 8624252
    Abstract: The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Gen Fujii, Hiroko Shiroguchi, Masafumi Morisue
  • Patent number: 8624665
    Abstract: Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-moo Choi, Won-joo Kim, Tae-hee Lee, Dae-kil Cha
  • Patent number: 8624244
    Abstract: A thin film transistor includes a gate electrode, a semiconductor layer, and a source electrode and a drain electrode placed on the semiconductor layer and electrically connected with the semiconductor layer. The semiconductor layer includes a light-transmitting semiconductor film and an ohmic conductive film placed on the light-transmitting semiconductor film and having a lower light transmittance than the light-transmitting semiconductor film. The ohmic conductive film is formed not to protrude from the light-transmitting semiconductor film. The ohmic conductive film is formed in separate parts with a channel part between the source electrode and the drain electrode interposed therebetween. The source electrode and the drain electrode are connected to the light-transmitting semiconductor film through the ohmic conductive film.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: January 7, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Reiko Noguchi, Kazunori Inoue, Masaru Aoki, Toshihiko Iwasaka
  • Patent number: 8624259
    Abstract: An organic light-emitting display device includes a substrate; a thin-film transistor on the substrate; a first insulating layer covering the thin-film transistor; a first electrode on the first insulating layer, and electrically connected to the thin-film transistor; a second insulating layer on the first insulating layer so as to cover the first electrode, and having an opening for exposing a part of the first electrode; a porous member in the second insulating layer; a second electrode on the second insulating layer, and facing the first electrode so as to correspond to the opening; and an organic emission layer between the first electrode and the second electrode so as to correspond to the opening. The organic light-emitting display device may prevent degradation of characteristics of an organic light-emitting device due to discharge of gas from an organic material.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeon-Hwa Lee, Won-Jong Kim, Ji-Young Choung, Joon-Gu Lee, Darby Choi, Young-Woo Song, Jong-Hyuk Lee
  • Publication number: 20140001477
    Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: WEIZE CHEN, HUBERT M. BODE, RICHARD J. DE SOUZA, PATRICE M. PARRIS
  • Publication number: 20140003148
    Abstract: An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Inventors: Jie Sun, Brian Cleereman, Minsoo Lee
  • Patent number: 8617939
    Abstract: A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8618543
    Abstract: Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel layer contacting the source and the drain is crystallized. In the method of manufacturing the TFT, the channel layer is formed of an oxide semiconductor, and a metal component is injected into the channel layer so as to crystallize at least a portion of the channel layer contacting the source and the drain. The metal component can be injected into the channel layer by depositing and heat-treating a metal layer or by ion-implantation.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ha Lee, Dong-hun Kang, Jae-cheol Lee, Chang-jung Kim, Hyuck Lim
  • Publication number: 20130341625
    Abstract: By controlling the luminance of light emitting element not by means of a voltage to be impressed to the TFT but by means of controlling a current that flows to the TFT in a signal line drive circuit, the current that flows to the light emitting element is held to a desired value without depending on the characteristics of the TFT. Further, a voltage of inverted bias is impressed to the light emitting element every predetermined period. Since a multiplier effect is given by the two configurations described above, it is possible to prevent the luminance from deteriorating due to a deterioration of the organic luminescent layer, and further, it is possible to maintain the current that flows to the light emitting element to a desired value without depending on the characteristics of the TFT.
    Type: Application
    Filed: August 23, 2013
    Publication date: December 26, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mai Akiba, Jun Koyama
  • Patent number: 8614445
    Abstract: Provided is an alkylsilane laminate with which it is possible to obtain an organic semiconductor film having excellent semiconductor properties. Such a laminate can be useful for an organic thin-film transistor. The alkylsilane laminate comprises an underlayer (Sub) having hydroxyl groups at the surface and an alkylsilane thin film (AS) formed on this underlayer. The alkylsilane laminate is a laminate wherein the critical surface energy Ec of the alkylsilane thin film and the number of carbons (X) of the alkylsilane satisfies the following formula (1): Ec?29.00?0.63x (mN/m) (1) Also provided is a thin-film transistor (10) having such an alkylsilane laminate (Sub, AS).
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: December 24, 2013
    Assignee: Teijin Limited
    Inventors: Takashi Kushida, Hiroyoshi Naito
  • Publication number: 20130334533
    Abstract: A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 19, 2013
    Inventor: Shunpei Yamazaki
  • Patent number: 8610652
    Abstract: Provided are display apparatuses and methods of operating the same. In a display apparatus, a display image may be continuously held for longer than about 10 msec after the power of the display panel is turned off. The display apparatus may indicate a liquid crystal display (LCD) apparatus including an oxide thin film transistor (TFT). Off leakage current of the oxide TFT may be less than about 10?14 A.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hoon Lee, Do-hyun Kim, Sang-wook Kim, Chang-jung Kim
  • Publication number: 20130328053
    Abstract: A transistor that may be used in electronic displays to selectively activate one or more pixels. The transistor includes a metal layer, a silicon layer deposited on at least a portion of the metal layer, the silicon layer includes an extension portion that extends a distance past the metal layer, and at least three lightly doped regions positioned in the silicon layer. The at least three lightly doped regions have a lower concentration of doping atoms than other portions of the silicon layer forming the transistor.
    Type: Application
    Filed: September 27, 2012
    Publication date: December 12, 2013
    Applicant: Apple Inc.
    Inventors: Abbas Jamshidi Roudbari, Cheng-Ho Yu, Shih Chang Chang, Ting-Kuo Chang
  • Publication number: 20130328050
    Abstract: It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.
    Type: Application
    Filed: August 15, 2013
    Publication date: December 12, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinari Higaki, Masayuki Sakakura, Shunpei Yamazaki
  • Publication number: 20130328049
    Abstract: A thin-film transistor substrate includes a gate line, and a gate electrode connected to the gate line, on a base substrate; an insulating layer on the gate electrode, the insulating layer including a first part and a second part, the first part having a hydrophobic property and the second part having a hydrophilic property; a data line extended in a different direction from the gate line, and a source electrode connected to the data line and on the second part of the insulating layer; a drain electrode on the second part of the insulating layer, the drain electrode spaced apart from the source electrode; a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes, where the semi-conductor pattern exposes the first part of the insulating layer; and a pixel electrode in contact with the drain electrode.
    Type: Application
    Filed: October 16, 2012
    Publication date: December 12, 2013
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae-Young CHOI, Bo-Sung KIM
  • Patent number: 8604483
    Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: December 10, 2013
    Assignee: Sony Corporation
    Inventors: Hisao Hayashi, Masahiro Fujino, Yasushi Shimogaichi, Makoto Takatoku
  • Publication number: 20130320317
    Abstract: An embodiment of the invention provides a thin film transistor substrate includes: a substrate; and a plurality of transistors, wherein each of the transistors includes a gate electrode disposed on the substrate; a first diffusion barrier layer disposed on the substrate and covering an upper surface and a ring sidewall of the gate electrode; a gate insulating layer disposed on the first diffusion barrier layer; an active layer disposed on the gate insulating layer and over the gate electrode; a source electrode disposed on the substrate and electrically connected to the active layer; a drain electrode disposed on the substrate and electrically connected to the active layer; and a protective layer covering the source electrode and the drain electrode.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 5, 2013
    Inventor: Kuan-Feng LEE
  • Patent number: 8598588
    Abstract: In some embodiments, a method of processing a film is provided, the method comprising defining a plurality of spaced-apart regions to be pre-crystallized within the film, the film being disposed on a substrate and capable of laser-induced melting; generating a laser beam having a fluence that is selected to form a mixture of solid and liquid in the film and where a fraction of the film is molten throughout its thickness in an irradiated region; positioning the film relative to the laser beam in preparation for at least partially pre-crystallizing a first region of said plurality of spaced-apart regions; directing the laser beam onto a moving at least partially reflective optical element in the path of the laser beam, the moving optical element redirecting the beam so as to scan a first portion of the first region with the beam in a first direction at a first velocity, wherein the first velocity is selected such that the beam irradiates and forms the mixture of solid and liquid in the first portion of the firs
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: December 3, 2013
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8598020
    Abstract: In a method of depositing a crystalline germanium layer on a substrate, a substrate is placed in the process zone comprising a pair of process electrodes. In a deposition stage, a crystalline germanium layer is deposited on the substrate by introducing a deposition gas comprising a germanium-containing gas into the process zone, and forming a capacitively coupled plasma of the deposition gas by coupling energy to the process electrodes. In a subsequent treatment stage, the deposited crystalline germanium layer is treated by exposing the crystalline germanium layer to an energized treatment gas or by annealing the layer.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: December 3, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Derek R Witty
  • Patent number: 8598587
    Abstract: An optical sensor preventing damage to a semiconductor layer, and preventing a disconnection and a short circuit of a source electrode and a drain electrode, and a manufacturing method of the optical sensor is provided. The optical sensor includes: a substrate; an infrared ray sensing thin film transistor including a first semiconductor layer disposed on the substrate; a visible ray sensing thin film transistor including a second semiconductor layer disposed on the substrate; a switching thin film transistor including a third semiconductor layer disposed on the substrate; and a semiconductor passivation layer enclosing an upper surface and a side surface of an end portion of at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun Jong Yeo, Hong-Kee Chin, Byeong Hoon Cho, Ki-Hun Jeong, Jung Suk Bang, Woong Kwon Kim, Sung Ryul Kim, Dae Cheol Kim, Kun-Wook Han
  • Patent number: 8598584
    Abstract: In the thin-film transistor device: the stacked thickness of either a source electrode or a drain electrode and a corresponding one of silicon layers is the same value or a value close to the same value as the stacked thickness of a first channel layer and a second channel layer; the stacked thickness of the first channel layer and the second channel layer is the same in a region between the source electrode and the drain electrode and above the source electrode and the drain electrode; the first channel layer and the second channel layer are sunken in the region between the source electrode and the drain electrode, following a shape between the source electrode and the drain electrode; and the gate electrode has one region overlapping with the source electrode and an other region overlapping with the drain electrode.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: December 3, 2013
    Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hisao Nagai, Sadayoshi Hotta, Genshiro Kawachi
  • Patent number: 8598050
    Abstract: Disclosed are a laser annealing method and apparatus capable of forming a crystalline semiconductor thin film on the entire surface of a substrate without sacrificing the uniformity of crystallinity in a seam portion in a long-axis direction of laser light, the crystalline semiconductor thin film having good properties and high uniformity to an extent that the seam portion is not visually recognizable. During the irradiation of a linear beam, portions corresponding to the edges of the linear beam are shielded by a mask 10 which is disposed on the optical path of a laser light 2, and the mask 10 is operated so that the amount of shielding is periodically increased and decreased.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: December 3, 2013
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Patent number: 8592832
    Abstract: An organic light emission diode (OLED) display device and a method of fabricating the same, wherein the OLED display device includes a substrate including a pixel region and a non-pixel region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, and including a channel region and source/drain regions, a gate electrode disposed to correspond to the channel region of the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, source/drain electrodes electrically connected to the source/drain regions of the semiconductor layer, and an interlayer insulating layer insulating the gate electrode from the source/drain electrodes, wherein areas of the buffer layer, the gate insulating layer and the interlayer insulating layer that are on the non-pixel region, respectively, are removed, and the partially removed area is 8% to 40% of a panel area.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: November 26, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Hoon Yang, Han-Hee Yoon, Kil-Won Lee, Jang-Soon Im, Ji-Yong Noh
  • Publication number: 20130306975
    Abstract: Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer.
    Type: Application
    Filed: July 1, 2012
    Publication date: November 21, 2013
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Sagy LEVY, Fredrick JENNE, Krishnaswamy RAMKUMAR
  • Publication number: 20130306969
    Abstract: A thin film transistor which may be included in a pixel circuit includes: a substrate; a semiconductor layer formed on the substrate and including a source region, a first drain region spaced apart from the source region by a first current path, and a second drain region spaced apart from the source region by a second current path having a length different from that of the first current path; a gate electrode insulated from the semiconductor layer by a gate insulating layer; a source electrode connected to the source region of the semiconductor layer; a first drain electrode connected to the first drain region of the semiconductor layer; and a second drain electrode connected to the second drain region of the semiconductor layer. Currents having different magnitudes may be simultaneously provided through the first current path and the second current path.
    Type: Application
    Filed: August 14, 2012
    Publication date: November 21, 2013
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin-Woo Park, Dong-Hwan Kim
  • Publication number: 20130306968
    Abstract: A transistor structure disposed on a substrate includes a gate electrode, a gate insulating layer overlapping the gate electrode, a channel layer overlapping the gate electrode, and a plurality of first electrodes and a plurality of second electrodes overlapping the gate electrode. The gate insulating layer is disposed between the channel layer and the gate electrode. Besides, the gate insulating layer is located among the first electrodes, the second electrodes, and the gate electrode. The first electrodes and the second electrodes are alternately arranged along a first direction. Each of the first electrodes has a first width along the first direction. Each of the second electrodes has a second width along the first direction. A ratio of the first width to the second width ranges from 2 to 20. A driving circuit structure having the transistor structure is also provided.
    Type: Application
    Filed: August 3, 2012
    Publication date: November 21, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Jyu-Yu Chang, Chun-Wei Lai, Po-Yuan Shen, Wen-Jung Lee, Chih-Wei Tai
  • Publication number: 20130299837
    Abstract: In a thin-film semiconductor device, a semiconductor layer has a bandgap energy of 1.6 eV or less, an insulating layer formed above the semiconductor layer includes: a first insulating layer region placed outside of a first contact opening and above one end of a gate electrode; a second insulating layer region placed outside of a second contact opening and above the other end of the gate electrode which opposes the one end; and a third insulating layer region being rectangular and placed between the first contact opening and the second contact opening.
    Type: Application
    Filed: July 12, 2013
    Publication date: November 14, 2013
    Inventors: Hiroshi HAYASHI, Takahiro KAWASHIMA, Genshiro KAWACHI
  • Publication number: 20130299836
    Abstract: A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate.
    Type: Application
    Filed: July 12, 2013
    Publication date: November 14, 2013
    Inventors: Hajime Kimura, Rumo Satake
  • Publication number: 20130299835
    Abstract: A field effect semiconductor device includes a semiconductor body having a main horizontal surface and a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged between the first semiconductor region and the main horizontal surface, an insulating layer arranged on the main horizontal surface, and a first metallization arranged on the insulating layer. The first and second semiconductor regions form a pn-junction. The semiconductor body further has a deep trench extending from the main horizontal surface vertically below the pn-junction and including a conductive region insulated from the first semiconductor region and the second semiconductor region, and a narrow trench including a polycrystalline semiconductor region extending from the first metallization, through the insulating layer and at least to the conductive region.
    Type: Application
    Filed: March 25, 2013
    Publication date: November 14, 2013
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze
  • Publication number: 20130299834
    Abstract: A semiconductor device may include a plurality of memory cells. The memory cells may be formed with respective fin shaped active regions with respective recesses formed therein. Thicknesses of the fins may be made relatively thicker around the recesses, such as by selective epitaxial growth around the recesses. The additional thicknesses may be asymmetrical so that portions of the fin on one side are larger than an opposite side. Related methods and systems are also disclosed.
    Type: Application
    Filed: February 19, 2013
    Publication date: November 14, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Seok Lee, Dae-Ik Kim
  • Publication number: 20130300968
    Abstract: The present invention provides a substrate for a liquid crystal display panel, the substrate being capable of effectively suppressing the occurrence of crosstalk and flicker without decreasing the aperture ratio. One aspect of the present invention is a substrate for a liquid crystal display panel, provided with: a light-shielding electroconductive member; a thin-film transistor arranged in a layer above the light-shielding electroconductive member; a transparent electrode wiring line arranged in a layer above the thin-film transistor, and a pixel electrode arranged in a layer above the transparent electrode wiring line. The light-shielding electroconductive member is a light-shielding element that covers the channel region of the thin-film transistor and is a wiring line connected to the transparent electrode wiring line, and the transparent electrode wiring line has a portion opposing the pixel electrode, with an insulating film disposed therebetween.
    Type: Application
    Filed: January 19, 2012
    Publication date: November 14, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Nami Okajima, Masahiro Fujiwara
  • Patent number: 8581258
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 12, 2013
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau
  • Patent number: 8581257
    Abstract: The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: November 12, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsuhito Murai, Shinya Tanaka, Hideki Kitagawa, Hajime Imai, Mitsunori Imade, Tetsuo Kikuchi, Kazunori Morimoto, Junya Shimada, Jun Nishimura
  • Patent number: 8575620
    Abstract: The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Chikao Yamasaki, Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada
  • Patent number: 8575605
    Abstract: An organic light-emitting display device includes: a substrate having a transistor region and a thin-film transistor having a gate electrode, a source/drain electrode and an active layer sequentially formed on the transistor region, wherein a portion of the source/drain electrode is between the active layer and substrate.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: November 5, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Seong-Kweon Heo
  • Patent number: 8575612
    Abstract: The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: November 5, 2013
    Assignee: AU Optronics Corp.
    Inventors: Chien-Chih Lee, Pei-Yi Shen, Ching-Yang Cheng, Shu-Ming Huang