Abstract: A power interconnection system comprising a plurality of z-axis compliant connectors passing power and ground signals between a first circuit board to a second circuit board is disclosed. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance interconnect.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: A first microelectronic element is provided with leads having anchor ends connected to contacts and tip ends moveable with respect to the first microelectronic element. The leads can be provided on a carrier sheet that is assembled to the first microelectronic element, or may be formed in situ on the surface of the first element. The leads may be unitary strips of a conductive material, and the anchor ends of the leads may be bonded to the contacts of the first microelectronic element by processes such as thermosonic or ultrasonic bonding. Alternatively, stub leads may be provided on a separate carrier sheet or formed in situ on the front surface of the first microelectronic element, and these stub leads may be connected by wire bonds to the contacts of the first microelectronic element so as to form composite leads. The tip ends of the leads are joined to a second microelectronic element that is moved away from the first microelectronic element so as to deform the leads.

Abstract: An apparatus including a substrate, and a surface mount component coupled with a top surface of the substrate, where the component includes side surfaces and a bottom surface, and the bottom surface is disposed adjacent to the top surface of the substrate. The side surfaces and the bottom surface of the surface mount component define a lower portion therebetween, the lower portion recessed away from the bottom component surface to allow solder to flow freely around a mounting lead of the surface mount component, for example, during the reflow process.

Abstract: An interconnect component comprises a compliant layer having a first surface and a plurality of electrically conductive leads having first ends and extending through the compliant layer. The first ends extend generally parallel to said first surface.

Abstract: A first interconnection pattern having a comb shape is formed around a semiconductor chip on a package body. A second interconnection pattern having a comb shape is formed around the first interconnection pattern. The projections of the first interconnection pattern are engaged with the projections of the second interconnection pattern. The distances between those two groups of projections and the bonding pads of the semiconductor chip are set nearly equal to each other.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A microelectronic component is fabricated by bonding a flexible sheet in tension on a rigid frame so that the sheet spans an aperture in the frame, and performing one or more operations on features on the flexible sheet which will be incorporated into the finished component. The frame maintains dimensional stability of the sheet and aids in regsitration of the sheet with external elements such as processing tools or other parts which are to be assembled with the sheet. Desirably, the frame has a coefficient of thermal expansion different from that of the sheet so that when the sheet is brought from the bonding temperature to the temperature used in processing, differential thermal expansion or contraction will cause increased tension in the sheet.

Abstract: A method and apparatus for increasing integrated circuit density in a semiconductor die assembly, and specifically, a dual LOC semiconductor die assembly. A first and a second die are substantially symmetrically back bonded to a die attach site on a opposing sides of a base lead frame. A first and a second offset lead frame, each having a plurality of lead fingers, are then attached to the base lead frame on opposing sides thereof so that their lead fingers respectively extend over the first and second dice in a cantilevered manner. Wire bonds are formed between lead ends of each of the lead fingers to corresponding bond pads on the first and second dice for electrical connection therebetween. The assembly is then encapsulated in a transfer molding process, after which the stacked dual LOC semiconductor assembly is subjected to a trim and form operation.

Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device includes a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along lateral of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.

Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

Abstract: A lead frame for an integrated circuit includes a ground for the integrated circuit to ground the integrated circuit, the lead frame having at least one corner connected to the ground; and a connector between the corner of the lead frame and the ground located on the integrated circuit.

Abstract: An integrated circuit device comprising a semiconductor connection component attached to a semiconductor die with an electrically conductive adhesive material. The integrated circuit device is structured with a semiconductor connection component having a first portion horizontally offset from a second portion, the first portion of the semiconductor connection component carrying the adhesive material. The semiconductor connection component may be a lead frame element having a lead finger. The semiconductor connection component with the electrically conductive adhesive material attached to the first portion thereof is a terminal such as a bond pad on a surface of a semiconductor die. The electrically conductive adhesive material is precisely applied in a simple manner, little adhesive material is wasted, and a one-step electrical/mechanical connection to bond pads of the die is provided.

Abstract: A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around the semiconductor pellet and upper parts of the lead terminals. The plurality of lead terminals are shaped to be elongated strips and are arranged to extend out of the molding member toward the substrate.

Abstract: A natural-resource-conservative, environmentally-friendly, cost-effective, leadless semiconductor packaging apparatus, having superior mechanical and electrical properties, and having an optional windowed housing which uniquely seals and provides a mechanism for viewing the internally packaged integrated semiconductor circuits (chips/die). A uniquely stamped and/or bent lead-frame is packaged by a polymeric material during a unique compression-molding process using a mold, specially contoured to avoid the common “over-packaging” problem in related art techniques. The specially contoured mold facilitates delineation of the internal portions from the external portions of the lead-frame, as the external portions are the effective solderable areas that contact pads on a printed circuit board, thereby avoiding a laborious environmentally-unfriendly masking step and de-flashing step, streamlining the device packaging process.

Abstract: A package for an integrated circuit device, having a die, a die pad, leads, bond wire, and an encapsulant. The lower surfaces of the die pad and the leads are provided with stepped profiles. Structures extending from lateral sides of the leads are formed to prevent the leads from being pulled horizontally from the package. Encapsulant material fills beneath the recessed, substantially horizontal surfaces of the die pad and the leads, and thereby prevents the die pad and the leads from being pulled vertically from the package body. Other portions of the die pad and the leads are exposed within the package for connecting the package externally.

Abstract: The invention provides a method and apparatus for electrically connecting the die of a high power semiconductor device to a substrate with a conductive strap such that the connection is resistant to the shear stresses resulting with changes in temperature. In one embodiment, the method includes providing a substrate having first and second portions that are electrically isolated from each other. A semiconductor die having top and bottom surfaces and one or more active electronic devices formed therein is also provided. The device has a first terminal connected to a first conductive layer on the bottom surface of the die, and a second terminal connected to a second conductive layer on the top surface of the die. The first conductive layer is electrically coupled to a top surface of the first portion of the substrate. The second conductive layer is electrically coupled to the second portion of the substrate with a metal strap.

Abstract: A leadframe for use with integrated circuit chips, comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.

Abstract: A semiconductor module of the type having a number of semiconductor chips disposed on a chip carrier has at least a second subset of the semiconductor chips disposed above a first subset and conductive connections between the semiconductor chips disposed one above another. The improvement includes flexible tapes forming conductive connections between the first subset of semiconductor chips and the second subset of semiconductor chips. Two of the flexible tapes originate from the first subset and lead to the second subset. The two flexible tapes respectively extend from a contact-making side of the first subset around respectively mutually opposite side faces of the first subset to the second subset.

Abstract: A packaging substrate is formed with electrically non-functional areas of Cu on the upper surface and/or lower surface for improved strength and rigidity and reduced warpage and bending. Embodiments of the present invention include substrates containing electrically non-functional grid-like Cu areas on the upper and lower surface such that the ratio of the total Cu area on one surface is about 55% to about 100% of the total Cu area on the other surface.

Abstract: A semiconductor device includes a resin sealing portion which has a plurality of side surfaces and a back surface which is formed between the side surfaces, a semiconductor chip which has a plurality of pads on a main surface thereof, a plurality of leads which are formed of conductor and each of which has a bonding portion, an external connection terminal portion and a cut portion, a plurality of wires which connect a plurality of leads and a plurality of pads of the semiconductor chip to each other, and a tab on which the semiconductor chip is mounted. By making the thickness of the cut portion of the lead smaller than the thickness of the external connection terminal portion, a lead sagging which is generated on the side surfaces of the resin sealing portion when the lead is cut by dicing after molding can be reduced.

Abstract: A lead frame includes a die pad including a die pad main portion having a large thickness and a die pad peripheral portion having an intermediate thickness smaller than that of the die pad main portion, provided on at least one side of the die pad main portion, at least one support lead connected to the die pad, and at least two first inner leads having a small thickness smaller than that of the die pad peripheral portion, arranged such that end portions thereof are opposed to the die pad peripheral portion. The thick die pad provides good heat release properties, and reducing the thickness of the leads allows fine pitched leads to be produced. Such a lead frame can be manufactured easily by press stamping after belt-shaped regions having different thickness are formed by rolling.

Abstract: An ultra-thin semiconductor package device comprises a heat-resistant film-type adhesive support tape which connects a semiconductor chip to a plurality of individual lead frames, wherein each lead frame is connected to an associated one of a plurality of electrode pads of the semiconductor chip by a plurality of bonding wires. An encapsulating molding material provides environmental protection for the completed package. Within the encapsulating molding, the semiconductor chip is mounted on a same underside of the support tape as the plurality of lead frames, such that the bottom of the semiconductor chip is aligned with the bottom of an encapsulating molding, and the height of a loop in each bonding wire is minimized.

Abstract: A semiconductor module includes a chip formed with an integrated circuit, a first external connecting terminal electrically connected to the integrated circuit, a printed wiring board having a second external connecting terminal, and a conductive material electrically connecting the first external connecting terminal with the second external connecting terminal, wherein the conductive material is formed so as to cover a sidewall of the second external connecting terminal. Accordingly, a semiconductor module is provided that can avoid an inferior connection caused by a crack between the lead and the pad.

Abstract: A semiconductor chip package comprising a semiconductor chip having peripheral arranged electrode pads, a lead frame comprising a plurality of lead-on-chip leads, standard normal leads and outer leads respectively coupled to the peripheral electrode pads of the semiconductor chip, and a package covering the semiconductor chip and the lead frame.

Abstract: A method for bonding inner leads of lead frame to substrate includes the steps of: (a) providing a substrate, the substrate having a plurality of connection pads formed on the electrical bonding surface of the substrate; (b) providing a lead frame with a dam tape adhered on of the inner leads of the lead frame; (c) thermally compressing the inner leads of lead frame onto the substrate, wherein a solder material is formed between the inner end and the corresponding connection pad of the substrate and the solder material is limited by the dam tape during inner lead bonding, so that there is stable electrical and mechanical connection between inner leads and the substrate.

Abstract: The invention is based on an electronic control circuit (10) having a printed circuit board (12) on which multiple electronic components (14, 16, 18, 20, 22) are arranged, in at least one (18) of which a Hall-effect sensor (20, 22) having a circuit part (18) belonging to the control electronics is assembled.

Abstract: A semiconductor module in which a lead electrode is integrally formed with or pressed into resin separated from a resin case, and a connector securing a pad for bonding a metal wire to the lead electrode is bonded to a substrate with a power semiconductor element mounted thereon by an adhesive, and the like in a similar manner as the module case. According to the present invention, an electrode can be disposed in an appropriate position in the semiconductor module, and the scope of the free layout is enhanced.

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate.

Abstract: An electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages. For adhesively bonding the semiconductor chip to a circuitized carrier or substrate on which the chip is positioned, and to concurrently form an encapsulating structure protecting the semiconductor chip, there is provided a mold compound, such as a thermosetting plastic resin or epoxy to not only extend between the surface of the circuitized substrate or carrier facing the semiconductor chip, and possibly about the peripheral sides of the carrier, but to also at least extend over and encompass the peripheral edge portions of the opposite surface of the carrier or circuitized substrate distal to or facing away from the chip.

Abstract: A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead being divided into an inner portion and an outer connecting portion. A first tape adhering under the inner portions of the leads fastens the first chip and the first bonding wires electrically connect the first chip with the inner portions. A second tape adhering upon the inner portions of the leads fastens the second chip and the second bonding wires electrically connect the second chip with the inner portions. The second tape has a thickness so as to avoid the first bonding wires touching the second chip. The multi-chip package enables to package at least two chips by a LOC lead frame without turnover action during wire-bonding.

Abstract: A semiconductor device exhibiting a lower incidence of burrs forming on its contacts during the singulation process. The semiconductor device includes a die which is electrically connected to a set of contacts wherein each contact has a contact surface and a non-contact surface. Each contact surface of the contacts contains a recessed region filled with a first deposit of molding material. The die and the non-contact surfaces of the contacts are encapsulated with a second deposit of molding material. The semiconductor device is singulated from a molded lead frame by guiding a saw blade through recessed regions formed on the contact surface of the contacts. The molding material in the recessed regions creates a “buffer zone” which separates the path of the saw blade from the contact surface of the contacts.

Abstract: A semiconductor component, which functions according to the principle of charge carrier compensation, has incompletely ionized dopants that are additionally provided in a semiconductor body of the semiconductor component. When a reverse voltage is applied, the degree of compensation changes as a function of time and the breakdown voltage of the semiconductor component increases in a manner governed by the degree of compensation. The invention furthermore relates to a circuit configuration and to a method for doping a compensation layer according to the invention.

Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.

Abstract: A lead frame for a high power semiconductor device die has three external lead conductors, the outer two of which are reentrantly bent outwardly from the center of the lead frame. When the lead frame is overmolded, the outer conductors are spaced from a central conductor by an increased creepage distance along the plastic surface of the housing. Further, the lead sequence of the exterior leads is gate, source, drain for a power MOSFET. The post area for wire bonding to the source post is enlarged to permit wire bonding with at least three bond wires. The external conductors can be downwardly bent to form a surface mount device. The cross-sectional area of the external conductors is substantially enlarged, although only a small enlargement of the circuit board hole is needed. The package outline has a long flat area centered over the main die area, with a tapered end surface which allows the package to pry open a mounting spring for surface mounting of the package.

Abstract: A method of producing a contact structure for electrical communication with a contact target. The method includes the steps of providing a silicon substrate cut in a (100) crystal plane, applying a first photolithography process on an upper surface of the silicon substrate for forming an etch stop layer, forming a first insulation layer on the etch stop layer, forming a second insulation layer on a bottom surface of the silicon substrate, applying a second photolithography process on the second insulation layer for forming an etch window, performing an anisotropic etch on the silicon substrate through the etch window for forming a base portion of a contactor, depositing conductive material on the first insulation layer for forming a conductive layer in a beam shape projected from the base portion, and mounting a plurality of contactors produced in the foregoing steps on a contact substrate in predetermined diagonal directions.

Abstract: A laminate-type semiconductor apparatus utilizing a flexible substrate being mounted with a plurality of semiconductor devices, in which the laminate-type semiconductor apparatus is free from incurring heat-radiation problem and has a fully leveled connection parts with sufficiently durable strength whereby distinctively compatible with high-density mounting thereof. More particularly, the present invention provides a laminate-type semiconductor apparatus which comprises a foldable flexible substrate mounted with a plurality of laminated semiconductor devices thereon, in which the foldable flexible substrate is folded so that plurality of semiconductor-device mounting areas of the substrate are mutually superposed whereby forming a laminate structure of semiconductor-device mounting areas thereon. An externally connected terminal disposing area disposed with a plurality of externally connected terminals is formed on one surface thereof.

Abstract: A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules.

Abstract: A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. The traces or leads are routed under the die such that proper connections are established from the topside of the die to the appropriate mount locations of the printed circuit board. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.

Abstract: A probe contactor is formed on a planar surface of a substrate by a photolithography technology. The probe contactor is configured by a substrate having an interconnect trace thereon which is an electric conductive path, and a contactor formed on the substrate through a photolithography process. The contactor has a base portion vertically formed on the substrate, a horizontal portion, one end of which is formed on the base portion, and a contact portion formed on another end of the horizontal portion. A spring force of the horizontal portion of the contactor provides a contact force when the probe contactor is pressed against a contact target. The contact portion of the contactor is sharpened so that when the contactor is pressed against the contact target, it scrubs a surface of the contact target.

Abstract: A semiconductor device includes a semiconductor element having a circuit surface on which a projection electrode is formed, a seal resin which seals the circuit surface of the semiconductor element while exposing at least an end part of the projection electrode, a connect surface that is to face a board when the semiconductor device is implemented on the board, a back surface which is opposite to the connect surface, a side surface arranged between the connect surface and the back surface, and an organic material layer formed on the side surface.

Abstract: The present invention relates to chip assembly with a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, than around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: A substrate includes a flip chip bond pad and a first bond pad on a dielectric substrate layer. First and second organic solderability protectant (OSP) layers are on the flip chip bond and first bond pad, respectively. A solder paste is on the first OSP layer. The solder paste is reflowed in an inert atmosphere to form a solder-on-pad (SOP) directly on and in contact with the flip chip bond pad. A sufficient thickness of the second OSP layer remains after reflow to inhibit oxidation of the first bond pad.

Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device includes a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.

Abstract: In an integrated circuit package, a deformed IC lead is reliably connected with a land for mounting. Such reliable connection between the deformed IC lead and a land is realized by a method for mounting an integrated circuit package wherein a non deformed first lead and a deformed second lead in the integrated circuit package are connected to a first land and a second land on a substrate, respectively.

Abstract: A lead frame for a semiconductor package including a rectangular lead frame body having a central opening, a plurality of leads arranged at and along each of two or four facing sides of the lead frame body, the leads extending in flush with the lead frame body, and a semiconductor chip mounting plate positioned on a plane not flush with a plane, where the leads are positioned, the semiconductor chip mounting plate being supported by down-set tie bars and provided with at least one groove having a rectangular ring shape while serving to prevent a penetration of moisture and to provide an increased coupling strength for the semiconductor chip mounting plate, the semiconductor chip mounting plate also serving as a heat sink. A ground bridge bar having a rectangular ring shape is arranged between the semiconductor chip mounting plate and the leads and supported by another tie bars.

Abstract: An integrated electronic device has at least two semiconductor devices built up in a multi-layer construction on a wiring substrate in which a die pad and a plurality of electrode pads are formed, the semiconductor device having a plurality of electrodes formed thereon. The semiconductor device for a first stage is disposed on the die pad. The semiconductor device for a second stage is disposed on the top of the first stage semiconductor device with having an electrically insulating resin layer in between the first and second stage semiconductor devices. The electrodes of the semiconductor devices are wire-bonded with corresponding electrode pads, and all of the build-up semiconductor devices and their wires are sealed with insulating seal resin.

Abstract: An area array type semiconductor device employing a single side wiring board in which a signal waveform is not likely to be disturbed even if a higher speed signal is applied includes more ground pads than the number of ground external terminals (ground wire land). The ground wire is formed in a larger width than the other wires on a single side of a substrate so as to form a plane, and gaps between the ground wire and the signal wire or the power wire are set to be substantially equal.

Abstract: A semiconductor device includes a resin package in which a semiconductor chip is sealed, the resin package having a first surface and a second surface opposite to the first surface; a plurality of leads having inner lead parts connected to the semiconductor chip and outer lead parts extending outside the resin package, the outer lead parts being bent along the shape of the resin package so as to form first terminal parts on the second surface and second terminal parts on the first surface; connection means electrically connecting the semiconductor chip and the leads; and a positioning mechanism provided either on the leads or on the resin package, which positions the outer lead parts by engaging a part of the outer lead parts to the resin package. Further, at least one of the leads and/or connection means is cut so as to electrically disconnect the semiconductor chip and the one of the leads and/or connection elements.