Abstract: An electronic component including an element main body section for performing an electrical function and a terminal section for electrically connecting the element main body section to a conductive member of an external device, the electronic component comprises a pair of sections arranged above the terminal section and opposite to each other in a stacking direction of the electronic component and a distance between the sections corresponding to a maximum thickness of the electronic component.

Abstract: A laminated ceramic electronic component includes an embedded portion formed in the periphery of an external terminal electrode so as to extend and be embedded in a component main member defined by ceramic layers, whereby affects of a small edge angle are eliminated.

Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.

Abstract: The present invention provides a semiconductor device whose reliability is improved by improving the adhesion strength of a metal plate or connecting chip, said plurality of electrodes and a lead frame with a molding resin. Further, the semiconductor device of the present invention prevents flow out of a conductive joining material to be employed for joining a lead terminal and the metal plate other than the joining range of the metal plate and the lead terminal, and mounts the metal plate at high precision. In a semiconductor device (a plastic package) in which a source electrode of a semiconductor chip and source terminal of a lead frame are electrically connected by a copper plate and sealed by a resin, the surface of the copper plate is roughened to improve the adhesion strength to a molding resin. Further, a stepped part is formed in the source terminal to prevent a conductive paste from flowing out. The structure is so formed as to fit claw parts in the lead frame.

Abstract: A semiconductor device that has a semiconductor die having at least two opposing major electrodes and a control electrode. Conductive clips, each having a base portion and a contact portion, are connected to respective electrodes at their bases by a respective layer of conductive material. A passivation layer is disposed on at least one of the electrodes and surrounds the layers of conductive material. The base portion and the contact portion of one of the clips are connected by an extension, which extends between the major surfaces of the semiconductor die.

Abstract: A semiconductor device including a semiconductor chip having an electric circuit on a surface thereof, and an electrode pad formed on the surface of the semiconductor chip and which is electrically connected to the electric circuit. A conductive pattern is electrically connected to the pad, and a sealing resin covers the electric circuit and the conductive pattern. A part of the conductive pattern is exposed from the sealing resin, and a plurality of grooves are formed on the part of the conductive pattern. The plurality of grooves are disposed apart from each other and along a direction of stress of the expanding semiconductor chip. An external electrode is electrically connected to the conductive pattern. Stress of the external electrodes is thus relieved and as a result, reliability of the semiconductor device can be improved, because deterioration of the connecting quality can be prevented.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: Disclosed is a ball grid array package with stacked center pad chips, which realizes a BGA package with stacked chips using center pad type semiconductor chips, and a method for manufacturing the same. The semiconductor chips are glued on each of upper and lower circuit boards, which have active surfaces facing each other; the chip pads are connected to each of the upper and lower circuit boards with gold wires; the upper and lower circuit boards are joined together with bumps interposed between them for electrical connection; the upper circuit board is included in a package mold; and the opposite ends of the lower circuit board are exposed to the lower portion of the package mold. The lower circuit board can be made of flexible insulation film. The exposed opposite ends of the lower circuit board can have solder balls formed thereon. Also, the opposite ends of the lower circuit board may be joined to a printed circuit board. Solder balls may be formed on the lower surface of the printed circuit board.

Abstract: The semiconductor module includes a substrate, at least one semiconductor, and electrical contacts. The substrate includes a base layer having a substantially planar base layer first surface opposing a substantially planar base layer second surface. The base layer first surface is exposed to atmosphere and where the base layer is electrically conductive. The substrate also includes an insulator layer having a substantially planar insulator layer first surface opposing a substantially planar insulator layer second surface. The base layer second surface and the insulator layer first surface are adjacent and contiguous to one another and where the insulator layer is electrically non-conductive. Finally, the substrate includes a conductive layer having a substantially planar conductive layer first surface opposing a substantially planar conductive layer second surface.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: A lead frame comprises a plurality of frame assemblies. Each framework assembly includes a framework, a suspension lead, a die pad, a plurality of inner leads and outer leads, a first tie bar and a second tie bar, and a lead support. The plurality of framework assemblies are disposed alongside of one another in a direction perpendicular to a direction in which the plurality of outer leads extend. A distance between close-set outer leads in each two neighboring frameworks is substantially n times a pitch of the plurality of outer leads in each framework, wherein n is an integer.

Abstract: An improved lead frame structure for use in a semiconductor package, including: a plurality of leads; a paddle structure electrically isolated from the leads, the paddle structure including at least one lower paddle section having a first top surface to which a die may be attached, at least one mesa section disposed proximate the paddle section and having a second top surface disposed at a different elevation than the first top surface, the lower paddle section and the mesa section being joined by a wall section; and a plurality of tie bars attached to the paddle structure for supporting the paddle structure; whereby contact pads of a die attached to the first top surface may be electrically connected to the second top surface and to the leads prior to encapsulation thereof. A plurality of tie bars extends from opposite edges of the paddle structure, the tie bars providing for stabilizing the paddle structure during package fabrication.

Abstract: A surface mounted electronic component includes a case and a board mounting part. The board mounting part includes a leg bent in parallel with a printed circuit board at its tip, an outer frame soldered to a land of a mounted part on the board, and a projection disposed in the outer frame and inserted into a hole in the mounted part. The electronic component is mounted on a surface of the printed circuit board in various electronic instruments, and can keep to be mounted on the board tightly even when an external force is applied.

Abstract: An interconnect component comprises a compliant layer having a first surface and a plurality of electrically conductive leads having first ends and extending through the compliant layer. The first ends extend generally parallel to said first surface.

Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.

Abstract: A semiconductor package includes a semiconductor chip connected to lead frames by wires and outer leads protruding from the semiconductor package. At this time, the outer leads are connected to the lead frames and grooves into which the outer leads are inserted into are provided in the semiconductor package, wherein the grooves are connected the lead frames. In mounting a first and a second semiconductor package, the outer leads of the first semiconductor package are inserted into the grooves of the second semiconductor pacakage.

Abstract: According to the present invention, when a semiconductor element having protruding electrodes formed thereon is connected to a circuit board via conductive resin, stable connection is made even when an electrode pitch is small on the semiconductor element. On semiconductor element package regions on the circuit board, a paste electrode material containing photopolymerizable materials is printed to form a film having a prescribed thickness, and this electrode material film is baked after exposure and development thereof so as to obtain circuit electrodes having edges warped in a direction of going apart from the circuit board surface. Then, the protruding electrodes and the concave surfaces of the circuit electrodes are brought in abutment with each other and connected via the conductive resin which surrounds the abutments between the respective electrodes and is held on the concave surfaces of the circuit electrodes.

Abstract: An improved bumped chip carrier (BCC) package according to the present invention includes a resin-molded lead frame encapsulating an attached semiconductor integrated circuit (IC) and a plurality of interconnecting wire bonds attaching a plurality of contact pads on the IC to an associated plurality of solder-covered external contact terminals that are integrated in the lead frame. By integrally processing the external contact terminals, bonding wires may be affixed using a single wire bonding process. A method for manufacturing the BCC package preferably includes a dual photoresist patterning process accompanied by a dual wet etching process to create a plurality of highly reliable external contact terminals having improved bonding between the contact terminals and the encapsulating resin mold.

Abstract: A semiconductor device including a package body, a substrate contained within the package body and having a first side and an opposite second side, a first chip mounted on the first side of the substrate and within the package body, a second chip mounted on the second side of the substrate and within the package body and a plurality of leads each including an inner lead portion contained within the package body and an outer lead portion located outside the package body wherein each inner lead portion includes first and second bends to define a step configuration and wherein a distal end of each inner lead portion is mounted to the second side of the substrate.

Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.

Abstract: A memory module has a module board having a main surface. A plurality of memory chips is arranged on the main surface of the module board. Each memory chip has two main surfaces extending between a first end face and a second end face of the memory chip, first mounting sites mounted to the main surface of the module board, and second mounting sites spaced apart from the first mounting sites and mounted to support sites spaced apart from the module board, so that a distance between the first end face and the module board is greater than a distance between the second end face and the module board. A circuit chip suited for such a memory module has terminals for connecting a circuitry of the circuit chip to terminals on the motherboard. Moreover, conductive structures are provided on a surface of the circuit chip for connecting terminals of another circuit chip to terminals on the motherboard.

Abstract: A semiconductor device having electrodes formed along a peripheral part thereof in a staggered arrangement of lines including inside-line, central-line and outside-line electrodes. The inside-line electrodes are octagonal shaped with hypotenuses on the central-line electrode and the pellet sides thereof. The central-line electrodes are octagonal shaped with hypotenuses on the inside-line and outside-line electrode sides thereof. The maximum width of outside-line electrode wires between the hypotenuses of adjacent inside-line and central-line electrodes depends on the distance between centers of the inside-line and central-line electrodes, minimum lengths of the inside-line and central-line electrodes and electrode protective film, and the necessary minimum conductor interval between the central-line and inside-line electrodes. The position and form of the central-line and inside-line electrodes are determinable based on the given relationship and the necessary value of current.

Abstract: A semiconductor package includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads. Each lead includes an inner end and an opposing distal end. Each inner end is disposed adjacent the peripheral edge in spaced relation thereto and vertically downset with respect to each respective distal end. The package further includes at least one isolated ring structure disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto. The ring structure is electrically connected to the semiconductor chip and an inner end of at least one of the leads.

Abstract: A module for optical communications includes a light receiving element which converts the light signal to an electric signal and an insulating substrate including first and second surfaces opposite to each other. An output section is provided on the first surface and extracts the electric signal as reverse and non-reverse signals. First and second connection terminals are connected to the output section and output the reverse and non-reverse signals. First and second wiring patterns are provided on the first surface. The first and second wiring patterns are electrically connected to one of the first and second wiring patterns and the other one thereof. The first and second wiring patterns have first and second ends, respectively. The first and second ends are provided in order in a direction intersecting with a line connecting the first and second connection terminals.

Abstract: An LOC type semiconductor package has a lead frame with leads divided into general leads and stable leads. The ends of the general leads are at the periphery of the semiconductor chip and separated from the semiconductor chip, such that the general leads do not come into contact with the semiconductor chip. The ends of the stable leads attach to a central portion of the surface of the semiconductor chip. Accordingly, since all the inner leads are not collectively arranged on the surface of the semiconductor chip but only the stable inner leads are located thereon, semiconductor chips in a variety of sizes can be mounted on the lead frame. Thus, there is no need for a new lead frame design whenever the semiconductor chip size is changed and a single lead frame design can be mass produced for use in several different products.

Abstract: A stress-balancing layer formed over portions of a spring metal finger that remain attached to an underlying substrate to counter internal stresses inherently formed in the spring metal finger. The (e.g., positive) internal stress of the spring metal causes the claw (tip) of the spring metal finger to bend away from the substrate when an underlying release material is removed. The stress-balancing pad is formed on an anchor portion of the spring metal finger, and includes an opposite (e.g., negative) internal stress that counters the positive stress of the spring metal finger. A stress-balancing layer is either initially formed over the entire spring metal finger and then partially removed (etched) from the claw portion, or selectively deposited only on the anchor portion of the spring metal finger. An interposing etch stop layer is used when the same material composition is used to form both the spring metal and stress-balancing layers.

Abstract: There is provided a high performance onboard semiconductor device with low manufacturing costs and low repair costs. The onboard semiconductor device includes a power chip substrate on which a power chip is mounted, a control substrate provided with an electrical part in relation to the power chip, and an outer enclosing case in which the power chip substrate and the control substrate are contained, and is characterized in that the control substrate and the outer enclosing case are removably fixed to each other.

Abstract: A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging, circuit card, electronic device, and a computer system. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

Abstract: A semiconductor device is produced using a lead frame whose size is smaller than a prescribed center area of a semiconductor chip surrounded by its bonding pads, which are connected with electrodes supported by electrode supports and interconnected with outer frames and an intermediate frame of the lead frame via bonding wires. A series of projections and hollows are formed on the outer frames, wherein the electrode supports are interconnected with the hollows of the outer frames respectively. The semiconductor chip combined with the lead frame, is integrally enclosed in a resin under the condition where only the electrode surfaces are exposed to the exterior, thus forming a resin package. Then, the electrode supports locating the electrodes are cut out and partially removed, so that the electrodes are made electrically independent from each other.

Abstract: This semiconductor device comprises a semiconductor chip, a signal lead connected to a signal electrode of the semiconductor chip, an external signal electrode connected with the signal lead, a ground lead extending along the signal lead, and a sealing resin sealing these elements. The external signal electrode is formed as a protruding electrode protruding from an undersurface of the sealing resin. One surface of the signal lead is exposed on the undersurface of the sealing resin.

Abstract: A method for manufacturing an electronic device by placing within a die a first lead with an element placement pad, a second lead, and an electronic element placed on the element placement pad. The electronic element, the element placement pad, a part of the first lead, and a part of the second lead are sealed in a package by injecting a sealing resin in the die from a position on a longer side of the package, with the position being offset toward one shorter side thereof. The first lead is bent in an S shape, with a bending depth being at least as large as the thickness of the first lead. A thickness of the resin on a non-device side of the element placement pad is smaller than the bending depth.

Abstract: An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are connected to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.

Abstract: A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the semiconductor chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: An electronic device is provided which includes a substrate of insulating resin having at least a pair of interior terminal portions on an upper surface thereof, an electronic element mounted on the terminal portions, having at least a pair of electrode terminals thereof, and a member of insulating resin, bonded on the upper surface of said substrate. The frame includes a cavity to store the electronic element. A cover member of insulating material hermetically seals over the cavity. Electrodes are formed at or in vicinity of positions of the terminals of said electronic element to electrically conduct the interior terminal portions for connection outside the device. Alternatively, roughened surfaces can be formed on metal electrode portions, which are formed on the upper surface of substrate for electrically conducting said interior terminal portions to exterior terminal portions.

Abstract: In a semiconductor device (1), semiconductor elements (2) and (3) are mounted on a lead frame (5) having leads (4). The semiconductor elements (2) and (3) are connected with the leads (4) by metallic wires (6) and (7). The semiconductor device (1) also has a heat sink (8). The members (2) to (8) are sealed with a plastic package (10). The leads (4) are exposed outward. Each of the end leads (4a) to (4d) has a wide first lead portion, a narrow second lead portion, a third lead portion to be inserted into an external substrate, and a protruding gap-controlling portion (9) for keeping the gap between the semiconductor device (1) and the external substrate constant. Because the heat resistance from the leads (4) to the plastic package (10) increases, the temperature-rise property of the lead is improved so that the solderability is improved.

Abstract: A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduce capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Abstract: A power module includes a substrate with a power semiconductor device mounted thereon, a case having an interior in which the substrate is disposed, a cooling fin having a surface on which the substrate and the case are placed, and a smoothing capacitor disposed on an opposite surface of the cooling fin from the surface on which the substrate is placed, the smoothing capacitor being electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device.

Abstract: A leadframe includes at least one peripheral lead secured to a paddle. A paddle solder bump pad and a peripheral solder bump pad are respectively situated on the at least one peripheral lead and the paddle. A first recess is adjacent to the paddle solder bump pad and a second recess is adjacent to the peripheral solder bump pad. A semiconductor die having at least first and second solder bumps is situated on the leadframe such that the first solder bump is soldered to the paddle solder bump pad while the second solder bump is soldered to the peripheral solder bump pad. The first and second recesses adjacent to respectively the paddle solder bump pad and the peripheral solder bump pad prevent solder from flowing out of the solder bump pad areas during solder reflow process. In this manner, the potential shorting of adjacent solder bump pads is prevented.

Abstract: A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: A semiconductor die assembly employing a voltage reference plane structure electrically isolated from, but in immediate proximity to, leads of a lead frame to which the die is electrically connected. A non-conductive adhesive or an adhesively-coated dielectric film is used to position the voltage reference plane on the leads. The voltage reference plane is electrically connected to a ground or other reference potential pin of the die through a connection to one of the leads. The assembly is encapsulated, preferably by transfer-molding of a filled polymer. More than one discrete voltage reference plane structure may be employed, for example, when the package is of an LOC configuration with two rows of leads, each having a voltage reference plane secured thereto, or a single voltage reference plane including major portions adhered to leads and interposed connection portions may be applied to all of the leads of an assembly.

Abstract: An adhesive film for semiconductor comprises a support film, and adhesive layers formed on both surfaces of the support film, in which each adhesive layer comprises an adhesive having a glass transition temperature of 200° C. or less, a coefficient of linear expansion of 70 ppm or less, and a storage elastic modulus of 3 GPa or less, and the adhesive film has a total thickness of between 43 and 57 &mgr;m. A lead frame for semiconductor comprises a lead frame and an adhesive film for semiconductor according to the present invention. A semiconductor device comprises a lead frame and a semiconductor element, in which the lead frame and the semiconductor element are adhered to each other via an adhesive film for semiconductor according to the present invention.

Abstract: A flexible interconnect substrate (1) comprises a tape-shaped base substrate (10) and a plurality of interconnect patterns (20) formed on the base substrate (10). The base substrate (10) bas a plurality of first regions (44) met to be punched out, and second regions (45) between those first regions (44). Each of the second regions (45) has the material that forms the base substrate (10) is present in a central portion in the widthwise direction of the base substrate (10), and a low-bending-resistance portion (40) for ensuring that the second region (45) bends more readily than the adjacent first regions (44) in a direction in which the longitudinal axis of the base substrate (10) bends.

Abstract: A semiconductor device that has a semiconductor die having at least two opposing major electrodes and a control electrode. Conductive clips, each having a base portion and a contact portion, are connected to respective electrodes at their bases by a respective layer of conductive material. A passivation layer is disposed on at least one of the electrodes and surrounds the layers of conductive material. The base portion and the contact portion of one of the clips are connected by an extension, which extends between the major surfaces of the semiconductor die.

Abstract: An electronic device having a first semiconductor device for powering MOSFET and a second semiconductor device for controlling on a principal surface and sealed by a resin body. The first semiconductor device has a semiconductor chip with a first and a second electrodes formed on a first principal surface and also with a third electrode formed on a second principal surface, and an insulative or dielectric sheet laid out between a first lead and the first principal surface of the semiconductor chip and between a second lead and the semiconductor ship for covering a specified area of the first principal surface of the semiconductor chip other than a region in which a plurality of projected electrodes are disposed. An upper surface of the first and second leads of the first semiconductor device is positioned under an upper surface of the resin body of the second semiconductor device in a thickness direction of a wiring substrate.

Abstract: In an LOC semiconductor device, a semiconductor chip is fixed on a die pad through a die pad material. A lead including an internal lead extending to the vicinity of a pad provided to the semiconductor chip is put in place. A tape member is placed at positions corresponding to four corners of the semiconductor chip between the internal lead and the semiconductor chip. The tape member is bonded and fixed only to the internal lead but it is not bonded or fixed to the semiconductor chip and merely contacts the surface of the semiconductor chip.

Abstract: A semiconductor device X1 comprises: a first conductor 110 including a first terminal surface 113a; a second conductor 120 placed by the first conductor 110 and including a second terminal surface 123a facing a same direction as does the first terminal surface 113a; a third conductor 130 connected with the first conductor 110; a semiconductor chip 140 including a first surface 141 and a second surface 142 away from the first surface, and bonded to the first conductor 110 and to the second conductor 120 via the second surface 142; and a resin package 150. The first surface 141 of the semiconductor chip 140 is provided with a first electrode electrically connected with the first conductor 110 via the third conductor 130. The second surface 142 is provided with a second electrode electrically connected directly with the second conductor 120.

Abstract: A semiconductor device including a semiconductor chip having first and second principal surfaces is disclosed. The semiconductor chip includes a first electrode formed on the first principal surface and a second electrode formed on the second principal surface. A first lead frame includes a first connecting portion connected to the first electrode and a first terminal portion. A second lead frame includes a second connecting portion connected to the second electrode and a second terminal portion. The semiconductor chip is sealed by a housing. The housing is formed so as not to cover part of surfaces of the first and second connecting portions.

Abstract: A lead frame including a first set of leads in a first plane and a second set of leads in a second plane offset vertically from the second plane. The leads in the first and second planes are offset from each other by a lead width.

Abstract: To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone.