Abstract: Electrodes of the electronic component chip is electrically connected with the end parts of the leads and the electronic component chip and the end parts of the leads are covered by the package with the leads which are extended out from the package are bent along the outer wall of the package, and a solder bump of low melting point is held in the gap between the leads and the package. By adopting this structure, soldering performance in mounting can be improved by a simple work while securing the moisture resistance between the leads and the package, and without requiring the work of number of steps of solder plating on the exposed leads after molding.

Abstract: A semiconductor device includes a semiconductor chip having a mounting surface with connecting pads mounted thereon, and a film having a gluing surface facing the mounting surface of the chip and a mounting surface for mounting a circuit board on a surface opposite the gluing surface. The circuit board has connecting pads mounted thereon. On the mounting surface of the film, a wiring pattern is formed with connecting terminals connected to the connecting pads of the circuit board. The film is an anisotropically conductive film and exhibits conductivity at local areas when subjected to pressure between the wiring pattern and the connecting pads of the semiconductor chip. The gluing surface of the film is attached solidly to the semiconductor chip, wherein the film maintains conductivity in view of a cooling process after heating.

Abstract: Disclosed is a semiconductor package and method of fabricating the same. According to the package of the present invention, a semiconductor chip 20 is disposed such that its bonding pad 21 is disposed upwardly. Metal lines 30,31 are deposited along a surface, both sides and a bottom face of the semiconductor chip 20 thereby electrically connecting its upper end 30 to the bonding pad 21 of the semiconductor chip 20. An entire resultant is encapsulated with molding compounds 50,51 such that a lower end of the metal line 31 is exposed thereby forming a ball land. A solder ball 60 is mounted on a portion of the metal line 31 exposed from the molding compound 51.

Abstract: A transceiver, especially an infrared transceiver, has a flat surface section and at least one or two lens forming housing sections integrally formed with the flat housing section. The lens housing sections are positioned so that one flat surface of the flat housing extends tangentially to the lens housing section or sections while the latter project outside the opposite flat housing surface. The lens housing section or sections are positioned along an edge of the flat housing section. For this purpose the lens forming housing section or sections have a substantially larger diameter (D) than the thickness (d) of the flat housing section. The respective lenses thus may have a substantially larger aperture, thereby increasing the wireless transmission and reception range of optical data transmission signals, in accordance with IRDA standards.

Abstract: There is provided a ball-grid-array semiconductor device. The semiconductor device has a semiconductor element sealed with a resin material. In addition, a lead frame is connected to the semiconductor element in the resin material. The lead frame is provided with terminal portions that protrude through the surface of the resin material.

Abstract: An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package outline. The package includes a package body and outer leads along the outline of the package body. The package body outline has concave portions to increase the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with concave portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.

Abstract: A method of manufacturing a semiconductor component includes coupling a clip bond (230) from a semiconductor chip (120) to a lead frame (110) and dividing the clip bond into at least first and second portions separated from each other.

Abstract: BLP stack is disclosed which has a higher reliability and a less area of mounting for providing a denser package, including a first package having external power connection leads each started to be exposed through a bottom thereof and extended to a top surface through a side surface inclusive of bottom lead portions on a bottom surface, side lead portions on a side surface, and upper lead portions on a top surface, and a second package having external power connection leads started to be exposed through a bottom thereof and brought into contact with the external power connection leads on the first package to be electrically connected thereto.

Abstract: A leaded semiconductor device package for nonsoldering assembling is disclosed. In the package of the invention, both leads of a semiconductor device package are flattened, cut and bent by automatic machines on the bais of conventional packaging process. Unlike a conventional semiconductor device package which is electrically connected to a circuit by soldering, the flattened and bent parts of both leads of the semiconductor device package can be electrically connected to a circuit by elastically contacting and directly assembling without soldering.

Abstract: A semiconductor package structure with exposed die pad is proposed. The proposed package structure comprises a lead frame having a die pad and a plurality of leads, with the bottom surface being formed with a cutaway portion at the peripheral edge thereof; a semiconductor chip mounted on the front surface of the die pad and electrically coupled to the leads; and an encapsulation body for encapsulating the semiconductor chip and part of the leads, with the bottom surface of the die pad being exposed to the outside of the encapsulation body.

Abstract: A semiconductor package includes a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a copper plate coupled to and spanning a substantial part of the first metalized region defining the source connection, the copper plate including at least one chamfered edge extending upward and away from the first metalized region; and at least one beam portion being sized and shaped to couple the copper plate portion to the at least one second terminal such that it is electrically coupled to the source.

Abstract: Outer leads extend outward from within a package that seals a semiconductor chip, and they are connected to the semiconductor chip inside the package. Depressions are formed at the distal end portions of the outer leads. The depressions are coated with a material which is one of: Sn—Pb, Sn—Ag, Sn—Bi, Sn—Zn, Sn—Cu, Pd, Au and Ag. The depressions are V-shaped, U-shaped, or rectangular. Each depression has a depth which is 30% to 75% with respect to the thickness which the outer lead has at the cut end face of distal end thereof. The outer leads are either a gull-wing type or a straight type.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A semiconductor device comprises a plurality of substrates (10) disposed to be stacked one another and having interconnect patterns (12) formed on the substrates, and semiconductor chips (20) mounted on the substrates (10). The interconnect pattern (12) has a bent portion (16) projecting from a surface of the substrate (10). The bent portions (16) are stacked one another and electrically connected.

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component. The packaging and interconnection includes a contact structure made of conductive material and formed on a contact substrate, a contact trace formed on the contact substrate and connected to the contact structure, a contact pad formed on a bottom surface of the contact substrate and connected to the contact structure through a via hole and the contact trace, a contact target provided at an outer periphery of the contact structure to be electrically connected with the contact pad, and a conductive member for connecting the contact pad and the contact target.

Abstract: A semiconductor device includes a semiconductor element, a holding substrate holding the semiconductor element, a frame body provided on the holding substrate so as to surround the semiconductor element and having a hole which communicates to a space formed between the holding substrate and the frame body and the frame body and the holding substrate form a housing, a plurality of leads having inner lead portions connected to the semiconductor element and outer lead portions extending outside the frame body, and a resin filling the space and encapsulating the semiconductor element and the inner lead portions. All of the outer lead portions extend outside the housing from one side of the housing.

Abstract: On the leads of an integrated semiconductor chip which establish a connection to external terminals of a supply voltage, highly clocked current pulses may result in the excitation of potential fluctuations through to resonance oscillations at an internal terminal of the respective lead. In order to attenuate these potential fluctuations, a resistance is prescribed for one or more leads, which resistance is large enough to attenuate the potential fluctuations but is small enough to cause only a predetermined maximum permissible voltage drop on the respective lead. The respective resistance can be obtained by using a material having a corresponding resistivity or by reducing the conductor cross section with a notch along the lead.

Abstract: A header containing a semiconductor die, method of manufacture thereof and electronic device employing the same. In one embodiment, the header includes first and second contacts, and an intermediate body. The intermediate body includes an insulated section interposed between the first and second contacts and has a cavity therein. The intermediate body also includes a semiconductor die, located within the cavity, adapted to condition a signal passing through at least a portion of the header.

Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.

Abstract: This invention prevents deterioration in characteristics of a semiconductor device having a lead frame that is thin and uniform in thickness. More specifically, this invention relieves resin distortion caused by a difference in thermal expansion coefficients between the lead frame and the sealing resin in order to prevent the characteristic deterioration caused by some factors such as moisture invasion from outside and mechanical pressure. A lead frame for a resin-sealed semiconductor device of this invention is composed of an element-mount part, a horizontal part for fixing the lead frame for resin sealing, and a central lead having side leads formed in parallel on both sides thereof. The element-mount part, the horizontal part and the central lead are formed integrally. In the lead frame, at least one pair of resin-anchoring parts are formed on two opposing sides on the periphery of the element-mount part.

Abstract: A microelectronic assembly includes a first microelectronic element including contacts on a contact-bearing face and a second microelectronic element confronting the first microelectronic element. The assembly also has a plurality of vertically extended signal leads electrically interconnecting the first and second microelectronic elements, and a plurality of vertically extended straps attached to the first and second microelectronic elements, whereby the straps are shorter than the signal leads for limiting vertical movement of the first and second microelectronic elements away from one another.

Abstract: A power switching module includes a substrate having at least one silicon die forming at least one power switching element and having leadframe terminal posts extending away therefrom. A planar negative rail layer providing a negative power supply and including a non-inductive current shunt resistor formed therein and a planar positive rail layer providing a positive power supply are positioned at the substrate so that the negative rail layer and the positive rail layer are coplanar with respect to each other. A phase output layer providing a phase output signal is also positioned at the substrate. Each of the layers are electrically isolated from each of the other layers and are electrically connected to the substrate.

Abstract: The semiconductor package including a semiconductor element 11 having a first face 21a and a second face 21b which is opposite to the first face 21a, an electrode 22 provided on the first face 21a, and a conductive lead 23 connected to the electrode 22 comprises an insulating film member 24 provided on the second face 21b for connecting the other end of the lead, the lead 23 is bent as oppose to a side face of the semiconductor element 11, and is connected each other with an elastic force between the electrode 22 and the film member 24, a bent part of the lead between the electrode 22 and the film member 24 turns to be a terminal part 23a. The circuit board has a connection means, connecting to the terminal unit 23a, and having an adequate size for placing the semiconductor package 11. The connection means is constituted of an accommodation groove part 46 or a frame part 50, and a plurality of pattern electrodes 47a, 47b, and the terminal part 23a is connected between the pattern electrodes 47a, 47b.

Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.

Abstract: The present invention relates to a packaged semiconductor comprising:

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component. The packaging and interconnection includes a contact structure made of conductive material and formed on a contact substrate, a contact trace horizontally extended on the contact substrate and connected to the contact structure, a contact pad formed on a bottom surface of the contact substrate remote from the contact structure, a contact target provided at an outer periphery of the contact structure in a side-by-side fashion to be electrically connected with the contact pad, a conductive lead for electrically connecting the contact pad and the contact target, an elastomer for achieving flexibility, and a support structure for supporting the contact structure, contact substrate and elastomer.

Abstract: There is provided a semiconductor device composed of lead frame in which the possibility of a complicated manufacturing process is prevented and a reduction in manufacturing cost can be satisfactorily achieved.

Abstract: In an integrated circuit package, a deformed IC lead is reliably connected with a land for mounting.

Abstract: A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: Outer leads extend outward from within a package that seals a semiconductor chip, and they are connected to the semiconductor chip inside the package. Depressions are formed at the distal end portions of the outer leads. The depressions are coated with a material which is one of: Sn—Pb, Sn—Ag, Sn—Bi, Sn—Zn, Sn—Cu, Pd, Au and Ag. The depressions are V-shaped, U-shaped, or rectangular. Each depression has a depth which is 30% to 75% with respect to the thickness which the outer lead has at the cut end face of distal end thereof. The outer leads are either a gull-wing type or a straight type.

Abstract: A semiconductor device is provided with a semiconductor chip and a connection lead connected to a pad of the semiconductor chip. The connection lead has a tip part which is bent up to a surface of the semiconductor chip on the opposite side of the pad. The semiconductor device is further provided a resin sealed part covering the semiconductor chip and a solder ball provided on the tip part of the connection lead.

Abstract: A leadframe including offsets extending from a major plane thereof. The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high Temperatures or changes in temperature.

Abstract: The semiconductor device includes a semiconductor chip and tapes. The tape includes insulating layers with the conductive layers which are sandwiched between the insulating layers. The tapes extend from the front surface to the back surface of the semiconductor chip and are fixed to the chip. Each of the conductive layers is exposed at the front and the back sides of the chip, respectively.

Abstract: A semiconductor device includes a first transistor chip, a first base lead, collector lead, and emitter lead, a second transistor chip, and a second base lead, collector lead, and emitter lead. The first base lead, collector lead, and emitter lead respectively have inner lead portions connected to the first transistor chip. The second base lead, collector lead, and emitter lead respectively have inner lead portions connected to the second transistor chip. The inner lead portion of the first emitter lead is arranged between the inner lead portion of the first base lead and the inner lead portion of the first collector lead. The inner lead portion of the second emitter lead is arranged between the inner lead portion of the second base lead and the inner lead portion of the second collector lead.

Abstract: The present invention provides a resin-sealed semiconductor IC package of a large integration size having a size substantially equal to that of its component semiconductor IC chip. The resin-sealed semiconductor IC package comprises a semiconductor IC chip, a plurality of leads arranged on the semiconductor IC chip and having end portions bent so as to extend perpendicularly to the major surface of the semiconductor IC chip, a resin molding sealing the semiconductor IC chip and the leads therein so that the tips of the end portions of the leads are exposed on one surface thereof, and conductive elements connected respectively to the exposed tips of the leads.

Abstract: A semiconductor element has electrodes on its periphery, leads for making external connections respectively in correspondence with the electrodes and connected to the electrodes through wires, and a package body in which a semiconductor element and leads are encapsulated with a resin material. The leads extend toward the bottom side of the package body for insertion into a socket and are bent alternately in a raised shape and a recessed shape, with the tops of the raised parts and the bottoms of the recessed parts exposed at side surfaces of the package body. The parts serving as the external connection electrodes (i.e., the tops of the raised parts and the bottoms of the recessed parts) are arranged at a large pitch, so that the area of the external connection electrodes can be enlarged to enhance the reliability of the contact.

Abstract: There is provided a technique of connecting easily the lead terminal to the board of the module. A plurality of clip lead terminals each has at one end thereof clip portions which are connected electrically to connecting terminals by sandwiching an end portion of a board of a module and the connecting terminals formed thereon between clip members of said clip portions and has a lead portion at the other end thereof. The clip lead terminals are arranged so as to be spaced from one another in parallel with one another with the leading edges of the respective clip portions aligned on a straight line. The clip lead terminals are connected to one another through a tie bar and a guide as a connecting portion, respectively, whereby the connecting clip lead terminal 18 is formed as one-body. The lead portions are bent on every other one, leading end portions of the bent lead portions and leading end portions of the non-bent lead portions are in parallel with each other viewing from a side of the board.

Abstract: A semiconductor device having lead terminals bent in a J-shape is disclosed. A radiating plate having a recess formed on an outer peripheral portion thereof is exposed to a lower face of a resin member and free ends of outer portions of the lead terminals are positioned in the recess of the radiating plate. The free ends of the outer portions of the lead terminals and the recess of the radiating plate are isolated from each other by projections of the resin member. Since the radiating plate is exposed to the lower face of the resin member, the heat radiating property is high whereas the radiating plate and the lead terminals are not short-circuited to each other at all.

Abstract: A package for semiconductor devices is encapsulated in an insulating resin. Multiple conductive leads project from one side of the package. Alternating leads are provided with an insulating coating which projects along a portion of their length. Leads which are not insulated are bent so as to displace them from the plane of the coated leads and space them further away from the coated leads. The bent leads are displaced a sufficient distance to provide a separation in air consistent with spacing standards for high voltage devices.

Abstract: A surface mount component includes a substrate having two main faces, and first electrodes made of a metal, such as zinc, which is unlikely to cause migration. The first electrodes are formed on most of the entire face of both main faces of the substrate. Second electrodes made of a superior bonding material, such as copper, are disposed on the first electrodes. Lead terminals are bonded to the second electrodes by a bonding material, and an external packaging material covers the surface mount component. This configuration suppresses the occurrence of migration and improves resistance to electrical breakdown.

Abstract: A flip chip assembly, and methods of making the same, including a substrate having a plurality of via holes, wherein pre-formed strips or leads hanging in the via holes and conductive material filled in the via holes together serve as the electrical connection between a semiconductor device and substrate circuitry. The method of manufacturing the flip chip assembly includes attaching an integrated circuit (IC) chip having a plurality of input/output terminal pads to a rigid or flexible substrate having a plurality of leads extending from patterned circuitry traces and hanging inside a plurality of via holes. The via holes are aligned with and expose the terminal pads. After attachment, an electrically conductive material, for example adhesive or solder, is filled into the via holes thereby connecting the leads to the terminal pads. The conductive material not only provides mechanical support but also electrical continuity between the IC chip and the circuitry of the substrate.

Abstract: A chip module has a contact area disposed on its outer side formed of a plurality of essentially flat contact elements of electrically conductive material insulated from one another. At least one semiconductor chip having one or more integrated semiconductor circuits that are electrically connected to the contact elements of the contact area via bonding wires. The contact elements of the chip module are formed by a prefabricated lead frame for supporting the at least one semiconductor chip and have on two opposing sides of the chip module outwardly offset terminals arranged in rows next to one another. The outwardly offset terminals are provided for surface mounting the chip module on the mounting surface of an external printed circuit board or an external circuit board substrate.

Abstract: A semiconductor device assembly according to the present invention may comprise a semiconductor die having at least one contact pad thereon and a package substrate having at least one lead pad thereon. The package substrate is sized to receive the semiconductor die so that the contact pad on the semiconductor die is substantially aligned with the lead pad on the package substrate when the semiconductor die is positioned on the package substrate. A coil spring is positioned between the contact pad on the semiconductor die and the lead pad on the package substrate so that the axis of the coil spring is substantially parallel to the contact pad contained on the semiconductor die and the lead pad contained on the package substrate.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

Abstract: A lead frame and a semiconductor device fabricated by using the same. The lead frame comprises: first and second band shaped members disposed parallel to each other; a plurality of island portions for mounting semiconductor pellets thereon having first end portions connected to the first band shaped member; coupling strip each provided for one of the island portions whose first end portion connects to a second end portion of each of the island portions and whose second end portion connects to the second band shaped member. The lead frame further comprises at least one electrode portion for each of the island portions and electrically coupled with a corresponding electrode of the semiconductor pellet. The at least one electrode portion is disposed between each of the island portions and the second band shaped member, a first end portion thereof is connected to the second band shaped member, and a second end portion thereof is opposed to the second end portion of each of the island portions.

Abstract: The present invention relates to chip assembly with a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, than around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: A lead frame (1) is provided which includes elongated side frames (2, 3) extending in parallel to each other, and section bars (4) connecting the side frames in a manner allowing the side frames to be shifted longitudinally. The side frame (2) is integrally formed with first lead terminals (6), whereas the side frame (3) is integrally formed with second lead terminals (7). Extremities of the first and the second lead terminals are overlapped after the side frames (2, 3) are shifted. At least either one of the first lead terminal (6) and the second lead terminal (7) is formed with a weaker portion having reduced bending strength. The extremities of the first and the second lead terminals is bonded to a semiconductor element (T) after the side frames (2, 3) are shifted. Thereafter, restoring force due to the spring-back action of the section bars (4) acts on the lead terminals (6, 7) and the semiconductor element (T). However, the restoring force is used to deform the weaker portion.

Abstract: A structure including a conductive, preferably metallic conductive layer is provided with leads on a bottom surface. The leads have fixed ends permanently attached to the structure and free ends detachable from the structure. The structure is engaged with a microelectronic element such as a semiconductor chip or wafer, the free ends of the leads are bonded to the microelectronic element, and the leads are bent by moving the structure relative to the microelectronic element. Portions of the conductive layer are removed, leaving residual portions of the conductive layer as separate electrical terminals connected to at least some of the leads. The conductive layer mechanically stabilizes the structure before bonding, and facilitates precise registration of the leads with the microelectronic element. After the conductive layer is converted to separate terminals, it does not impair free movement of the terminals relative to the microelectronic element.

Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.