Abstract: A semiconductor device is disclosed that includes a semiconductor die, a metal leadframe, and a metal strap. A bottom surface of the semiconductor device is on and electrically coupled to a first portion of the leadframe. A first end portion of the metal strap is on and electrically coupled to a top surface of the semiconductor die. An opposite, second end portion of the metal strap is on and electrically coupled to a second portion of the leadframe within a recess of the second portion of the leadframe.

Abstract: A semiconductor device in which a lead frame having inner connecting portions and outer connecting portions, a semiconductor chip having electrodes on the surface thereof, and metal wires for electrically connecting electrodes on the semiconductor chip and the inner connecting portions of the lead frame are sealed with a sealing resin. The bottom side of the sealing resin of the inner connecting portion is covered with an inner connecting portion sealing resin.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Abstract: A multi chip package includes a first semiconductor chip, a second semiconductor chip and a spacer. The spacer is formed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chips is fixed on the first semiconductor chip by an adhesive material that is formed on the first semiconductor chip. Since the spacer is formed between the first semiconductor chip and the second semiconductor chip, the space between the first semiconductor chip and the second semiconductor chip is evenly.

Abstract: Methods for forming substantially chip scale packages and the resulting structures are disclosed. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

Abstract: A stack of integrated circuits in thin small outline packages (TSOP's) is constructed with an air space in between adjacent packages. The TSOP's have a plurality of connection terminals extending therefrom. A lead frame is disposed adjacent to the packages, positioned medially of the air space and having a plurality of connection terminals in registration with and in electric contact with the plurality of TSOP connection terminals. The TSOP's have a chip select terminal and several unused terminals. The lead frame has a strain-relieved conductor extending between the chip select terminal on a TSOP higher in the stack to the adjacent TSOP lower in the stack. Moreover, TSOP locating surfaces are included on the lead frame in the finished stack.

Abstract: A semiconductor device includes a semiconductor chip with a functional surface, a substrate opposing the functional surface of the semiconductor chip at a space formed between the substrate and the functional surface, a power supplying device electrically connected to a part of the functional surface of the semiconductor chip and separated by a slight gap from the substrate, a fixing member that fixes the semiconductor chip to the substrate, and a sealing member that seals the space formed between the substrate and the functional surface of the semiconductor chip other than a space formed between the substrate and the functional surface of the semiconductor chip that are fixed to each other through the fixing member and other than the gap formed between the power supplying device and the substrate. The sealing member has greater elasticity than the fixing member.

Abstract: Semiconductor devices and methods of forming semiconductor devices are described. In one embodiment, at least one conductive structure is formed within a plurality of semiconductor substrates. At least portions of one of the conductive structures have oppositely facing, exposed outer surfaces. Individual substrates are stacked together in a die stack such that individual conductive structures on each substrate are in electrical contact with the conductive structures on a next adjacent substrate. In a preferred embodiment, the conductive structures comprise multi-layered, conductive pad structures.

Abstract: A packaged electronic device includes connection contacts that are formed on the contact pads on the second surface of the substrate. In contrast to the prior art, the connection contacts are not solder contacts but are formed of nickel/aluminum plated copper and are therefore harder and less malleable and subject to deformation than prior art solder balls. The connection contacts are formed to align with, and contact, attachment pads formed on the motherboard or other system component. A tension device is then used to mechanically attach the packaged electronic device of the invention to the motherboard.

Abstract: A device (1,21,28, 36, 37, 86, 103, 121, 128) for electronic packaging, the device including a discrete solid body having a pair of opposing generally parallel major surfaces, the solid body having a body portion of a porous valve metal oxide based material with a pair of exterior surfaces respectively constituting portions of the major surfaces and extending inward from one major surface towards the other major surface, the body portion having one or more electrically insulated valve metal conductive traces of from about 10 &mgr;m to about 400 &mgr;m thickness in a direction from one major surface to the other major surface embedded therein, one or more of said traces having a trace portion divergingly extending inward from an exterior surface constituting a portion of one of said major surfaces.

Abstract: A lead frame for a high power semiconductor device die has three external lead conductors, the outer two of which are reentrantly bent outwardly from the center of the lead frame. When the lead frame is overmolded, the outer conductors are spaced from a central conductor by an increased creepage distance along the plastic surface of the housing. Further, the lead sequence of the exterior leads is gate, source, drain for a power MOSFET. The post area for wire bonding to the source post is enlarged to permit wire bonding with at least three bond wires. The external conductors can be downwardly bent to form a surface mount device. The cross-sectional area of the external conductors is substantially enlarged, although only a small enlargement of the circuit board hole is needed. The package outline has a long flat area centered over the main die area, with a tapered end surface which allows the package to pry open a mounting spring for surface mounting of the package.

Abstract: A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

Abstract: A tape carrier in which a plurality of semiconductor elements can be mounted. The tape carrier includes a base tape on which device holes are formed and a plurality of leads provided on the base tape, wherein inner lead portions, which extend from the periphery of the device hole toward the center of the device hole, are of different lengths.

Abstract: A structure includes holes formed in a layer of tape. The holes are aligned over active areas on chips formed in a wafer. A custom vacuum chuck with a plurality of suction ports is aligned on the tape such that the suction ports contact only the tape and not the hole portions. Flats of the custom vacuum chuck are formed so that a perimeter of the flats contacts, and rests on, the tape. In addition, the flats of the custom vacuum chuck are formed so that the flats cover the entire active area on the first surface of each of the chips. Consequently, the combination of the custom vacuum chuck and the single layer of tape form a protective cavity over the active areas of the chips during singulation from the wafer.

Abstract: A circuit arrangement includes a base body, with one or more substrates, an intermediate-circuit board, a compression device and a driver circuit. Each substrate includes a positive-pole conductive strip, a negative-pole conductive strip, and auxiliary connections. Components such as power transistors, are in contact with the conductive strips and the auxiliary connections. The intermediate-circuit board includes a positive-pole DC connection and negative-pole DC connection and electrical capacitors connected between them. An AC connection element that must be cooled is assigned to each substrate. The positive-pole DC connection and the negative-pole DC connection include contacts for direct low-inductance connection with the corresponding conductive strips of the one or more substrates. The equivalent applies to the one or more AC connection elements.

Abstract: An injection molded image sensor includes metal sheets arranged in a matrix, an injection molded structure, a photosensitive chip, bonding pads, wires, and a transparent layer. Each metal sheet has a first board, a second board and a third board to form a -shaped structure. The injection molded structure encapsulates the metal sheets by way of injection molding and has a first molded body and a second molded body. The injection molded structure has a U-shaped structure and is formed with a cavity. The first, second, and third boards are exposed from top, bottom, side surfaces of the first molded body. The photosensitive chip is mounted within the cavity. The bonding pads are formed on the photosensitive chip. The wires electrically connect the bonding pads to signal input terminals of the first boards. The transparent layer covers over the first molded body to encapsulate the photosensitive chip.

Abstract: The package for mounting a solid state image sensor is a box-type resin package having in its bottom surface an opening for allowing light to pass so that a solid state image sensor may be mounted face down there. In the package, a three-dimensional circuit is formed which has a lead comprising a conductive metal plate making electrical conductance possible. The top surface of the inner lead of the lead is exposed on the inside bottom surface in the vicinity of the opening, and the top surface of the outer lead and the edge of the lead, following a bent section of the lead, are exposed on the side wall top surface of and the top edges of the side wall side surface of the aforesaid box-type resin package, respectively, with all the parts of the lead other than the exposed parts of both ends being embedded in the resin. Because of this, a small, thin package for mounting a solid state image sensor can be manufactured at low cost by using a simple process.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: A microelectronic connection component includes a support such as a dielectric sheet having elongated leads extending along a surface. The leads have terminal ends permanently connected to the support and tip ends releasably connected to the support. The support is juxtaposed with a further element such as a semiconductor chip or wafer, and tip ends of the leads are bonded to contacts on the wafer using a bonding tool advanced through holes in the support. After bonding, the support and the further element are moved away from one another so as to deform the leads.

Abstract: A molded electronic component has numerous connection pins protruding on a single plane from a side surface area of an essentially cuboid housing, and a circumferential ridge of molded housing material protrudes from the other side area surfaces on the plane of the connection pins. The thickness of this ridge essentially corresponds to the thickness of the connection pins. On the side surface area located opposite the side surface area from which the connection pins protrude, in the plane of the connection pins, the ridge passes or transitions into a groove such that there is no ridge protruding outwardly beyond the side surface in this area. Thus, the component can be better placed by a tool such as a suction needle onto a printed circuit board without interference from such a ridge. The invention is particularly suitable for the production of molded electronic components whose separation plane runs through that housing surface which serves as a docking surface for a suction needle.

Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.

Abstract: Surface mount diodes are mass produced by first cutting a metal plate to form a plurality of vertical slits within metal plate. Parallel lines are cut midway between the slits to form wings for the slits. The wings are folded to form the bottoms for surface mounting. Glue is applied over the metal plate to form focusing cups.

Abstract: A flip-chip with a solder pre-plated leadframe that includes locating holes. The leadframe does not include a die attach pad. Two of the leads include a locating or alignment hole for receiving a solder bump of the bumped die. The remaining leads include die contact areas for placement of the die thereon with the solder bumps contacting the die contact areas. The leads with the die contact areas are downset. The downset is approximately 4 mm.

Abstract: A light-emitting diode with which the LED chip will not be destroyed comprises an LED chip 40 mounted on plate-shaped wiring means 60 inside a light-emitting diode. Wiring means 60 comprises conductive paths 61 and 62 that electrically lead to a pair of opposing surfaces. The top surface is used for mounting the LED chip. Part of the conductive paths 61, 62 are connected electrically to LED chip 40, extending from the position where the LED is mounted to leads 21 and 22, to which they are connected by soldering. LED chip 40 is supported by being held inside concave part 23 in one lead 21 at this time.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: The lead frame has a spring element, which can be compressed during the injection molding of the package by an injection mold. The resultant resilience has the effect that a contact surface of the lead is pressed against an inside wall of the injection mold. The biasing of the contact surface against the inside wall prevents polymer flash from forming on the contact surface. Also, the spring element fixes the lead during the injection operation and anchors the lead in the completed package. Hold-down pins within the injection mold are thus obviated.

Abstract: A semiconductor chip provided, at a lateral face thereof, with an electrode for external electric connection. Where a semiconductor chip has a plurality of electrodes, all the electrodes are preferably formed at one or more lateral faces of the semiconductor chip. Each electrode is preferably embedded in a groove which is formed in a lateral face of the semiconductor chip and which is opened laterally of the semiconductor chip. The semiconductor chip may be a discrete bipolar transistor element. In this case, each of the base electrode, the emitter electrode and the collector electrode is preferably formed at a lateral face of the semiconductor chip.

Abstract: According to one embodiment, a leadframe having at least one tab is placed inside a mold cavity. During the molding process, the ceiling of the mold cavity is pressed against the at least one tab, which in turn causes a bottom surface of the leadframe to be pressed firmly against a floor of the mold cavity. When a mold compound is injected into the mold cavity, the mold compound is prevented from reaching under the bottom surface of the leadframe. In one embodiment, the tabs are etched into one of the tie bars in the leadframe. The tabs are then mechanically formed at a nonzero angle with respect to a plane of a frame of the leadframe.

Abstract: To eliminate variations in measurement of the chip characteristics an MMIC chip has a pad main portion having the same width as a main line at an end of the main line The main line is located on a GaAs substrate. Pad auxiliary islands are adjacent to the pad main portion on one or both sides. A grounding wiring layer is on at least one side of the pad main portion with the pad auxiliary island interposed in between. The pad main portion and the pad auxiliary portions secure a sufficient bonding area. The electrical characteristics are measured by bringing probes into contact with the pad main portion and the grounding wiring layer(s). The electrical characteristics of the MMIC chip can be evaluated without an increase in bonding pad capacitance.

Abstract: A semiconductor module includes a semiconductor chip, a lead frame having lead fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.

Abstract: A multi-chip module (MCM) having a substrate including a first surface, a second surface and a multi-layer interconnection arrangement disposed between the two surfaces. A high-density thin-film circuit region is provided on the substrate first surface to interconnect a plurality of integrated circuit chips and the multi-layer interconnection arrangement. The integrated circuit chips are powered through the high-density thin-film circuit region, which receives power from the multi-layer interconnection arrangement. A plurality of discrete on-board voltage converter devices, mounted on at least one substrate surface, provide uniform power supply distribution to multi-layer interconnection arrangement power planes, converting an MCM input voltage and current to a relatively lower output voltage and a relatively higher output current.

Abstract: A semiconductor device includes a passivation film (19) having opening portions through which an electrode pads (18) formed on a semiconductor chip (21) are exposed, projecting electrode portions (20) whose one end faces are connected to the electrode pads (18) through the opening portions, post electrode portions (16A) through which the other end faces of the projecting electrode portions (20) and the metal bumps (26) are connected to each other, and an insulating resin layer (13) having elasticity which covers the post electrode portions (16A), the projecting electrode portions (20) and the passivation film (19) with the exception of the end faces of the post electrode portions (16A).

Abstract: In a lead frame which has second tie bars 4a2, 4b2 in the vicinity of plastic packages 15, first notches 1 are formed along first edges of the second tie bars 4a2, 4b2 (in areas defined on both sides of the inner leads 12a, 12b and to come into contact with a punch during the tie bar cutting step). The first notches 1 prevent troubles associated with close arrangement of the second tie bars 4a2, 4b2 and the plastic packages 15. In addition, second notches 2 are provided along second edges of the second tie bars 4a2, 4b2. These second notches 2 are designed to receive the tips of outer leads 13a, 13b which extend from neighboring plastic packages 15 of the lead frames 100a, 100b.

Abstract: A method of manufacturing a semiconductor device includes a step of providing a semiconductor chip having electrodes to face a tape having a plurality of first holes, a support member surrounded by the first holes, and leads extending across the first holes to the support member; a step of bonding the electrodes to the leads; a step of cutting the leads in the first holes; and a step of bending the leads to go around a lateral portion of the support member.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A configuration of at least two TSOP memory chip housings stacked one on another, is described. Each of the TSOP memory chip housings has at least one memory chip with a number of pins disposed in an interior of the TSOP memory chip housing. The pins leading out of a respective TSOP memory chip housing and, via a rewiring configuration, are connected to pins leading out of a respectively directly adjacent TSOP memory chip housing of the same TSOP memory chip housing stack. In order to be able to produce such a housing stack as cost-effectively and simply as possible by an automated mounting method, the rewiring configuration is implemented in the form of leadframes respectively disposed between or at the side between the individual TSOP memory chip housings.

Abstract: A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.

Abstract: A semiconductor device having electrodes formed along a peripheral part thereof in a staggered arrangement of lines including inside-line electrodes, central-line electrodes and outside-line electrodes. The inside-line electrodes are hexagonal shaped with hypotenuses on the central-line electrodes sides thereof. The central-line electrodes are hexagonal shaped with hypotenuses on the inside-line electrode sides thereof. The maximum width of the outside-line electrode wires immediately between the hypotenuses of adjacent inside-line and central-line electrodes depends on the distance between the centers of the inside-line and central-line electrodes, the minimum lengths of the inside-line and central-line electrodes and the electrode protective film, and the minimum length of the corresponding wire. The position and form of the central line electrodes are thus determinable based on the given relationship and the necessary value of current.

Abstract: Devices and methods of fabrication thereof are disclosed. A representative device includes a complaint wafer-level package having one or more lead packages. A representative lead package includes a substrate having a plurality of die pads disposed thereon and a plurality of leads attached to the plurality of die pads. In addition, the lead package includes a plurality of pillars made of a low modulus material. Each pillar is disposed between the substrate and at least one lead, and each lead is disposed upon one of the pillars that compliantly support the lead.

Abstract: A lead frame of a plastic integrated circuit package is fabricated in two steps. First, from a rectangular sheet of metal, lead fingers of the lead frame are formed. Second, the die pad of the lead frame is clamped and is simultaneously separated and downset from the lead fingers of the lead frame by shearing the lead frame with a mated punch die pair. Performing the separation and downset of the die pad from the lead fingers results in essentially no horizontal gap between the lead fingers and the die pad. The downset of the die pad with respect to the lead fingers results in a vertical separation between the die pad and the lead fingers.

Abstract: A flip-chip with a solder pre-plated leadframe that includes locating holes. The leadframe does not include a die attach pad. Two of the leads include a locating or alignment hole for receiving a solder bump of the bumped die. The remaining leads include die contact areas for placement of the die thereon with the solder bumps contacting the die contact areas. The leads with the die contact areas are downset. The downset is approximately 4 mm.

Abstract: Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A connection component is provided. The connection component includes (1) a first interposer having a first surface to which a microelectronic may be mounted and a second surface opposite from the first surface, (2) a second interposer that is more flexible than the first interposer and that is disposed under the second surface of the rigid interposer, and (3) a plurality of conductive parts that may be positioned in the first and second interposers and that may be exposed at the first surface of the first interposer, a bottom surface of the second interposer, or both the first and bottom surfaces. The electrically conductive parts may include leads. A socket assembly or a microelectronic element such as semiconductor chip may be mounted onto the first surface of the rigid interposer. The connection component may be mounted onto a support substrate.

Abstract: A lead frame set includes a plurality of lead frames disposed in parallel and each lead frame includes a plurality of leads. Each of the leads includes an inner lead, an intermediate portion, and an outer lead, the intermediate portions are embedded in a resin molding base, and connect the inner leads at a higher level to the outer leads at a lower level, and at least one of widths and pitches of the inner leads and the outer leads are different values.

Abstract: The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, /TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.

Abstract: Apparatus and methods of testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components. In one embodiment, a circuit-bearing interconnect component includes a substrate having a plurality of first conductive members disposed therethrough, a plurality of conductive traces coupled to the first conductive members and extending away from the first conductive members to a distal portion of the substrate, and a plurality of second conductive members disposed on the distal portion and coupled to the conductive traces. The substrate may be rigid or flexible. The first conducting members are located within an engagement area that is adapted to be engageable with a semiconductor component having a plurality of conductive bumps wherein each conductive bump engages one of the first conductive members. The first conductive members may include conductively-plated via or conductive pins.

Abstract: A system substrate for a semiconductor chip has a conductor frame (1); many small-area signal flat conductors (4) extend from webs (2, 3) of the conductor frame and on their free ends have contact terminal faces (5). Remaining faces (6) between the webs (2, 3) and the many signal flat conductors (4) are occupied by large-area flat conductors (7). Between the large-area flat conductors (7) and the webs (2, 3), there are connecting webs (9) with bent areas (8) at various spacings from the webs (2, 3).