Abstract: A semiconductor device having electrodes formed along a peripheral part thereof in a staggered arrangement of lines including inside-line, central-line and outside-line electrodes. The inside-line electrodes are octagonal or hexagonal shaped with hypotenuses on the central-line electrode and the pellet sides thereof. The central-line electrodes are octagonal or correspondingly hexagonal shaped with hypotenuses on the inside-line and outside-line electrode sides thereof. The maximum width of outside-line electrode wires between the hypotenuses of adjacent inside-line and central-line electrodes depends on the distance between centers of the inside-line and central-line electrodes, minimum lengths of the inside-line and central-line electrodes and electrode protective film, and the necessary minimum conductor interval between the central-line and inside-line electrodes.

Abstract: A connection structure including an IC chip, a substrate disposed with a conductive layer, and a heat-radiating mechanism that is mounted on the substrate, disposed between the IC chip and the substrate, and dissipates heat of the IC chip, wherein terminals of the IC chip are electrically connected to the conductive layer via the heat-radiating mechanism.

Abstract: A tape carrier in which a plurality of semiconductor elements can be mounted. The tape carrier includes a base tape on which device holes are formed and a plurality of leads provided on the base tape, wherein inner lead portions, which extend from the periphery of the device hole toward the center of the device hole, are of different lengths.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: A heat spreader and stiffener device has a stiffener portion extending towards a center of the heat spreader and stiffener device and mountable to a die-side surface of a substrate.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: A multi-connect substrate, module including the substrate and an Integrated Circuit (IC) chip packaged in the module. The multi-connect substrate includes a multilayered substrate with at least one edge terminal array and one inboard terminal array on one face. An exterior terminal array is located on an opposite face. Signal wires pass through the multilayered substrate, connecting edge terminals to inboard terminals and inboard terminals with a exterior array terminals.

Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30–50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires.

Abstract: An IC package includes a leadframe disposed within a mold body. A paddle is situated substantially on a first mold body surface. An outer paddle surface is substantially exposed for dissipating heat. A semiconductor die is coupled onto an inner paddle surface. A first portion of leads is formed against a side surface of the mold body for coupling to a PCB placed against a second mold body surface opposite to the first mold body surface. The footprint of the IC package is substantially coextensive with the footprint of the mold body. In another embodiment, an IC package includes a heat spreader having a semiconductor die attach area on an inner heat spreader surface between a first heat spreader end and a second heat spreader end. The heat spreader has insulator elements coupled to the ends of the heat spreader. The insulator elements can have bonding areas thereon.

Abstract: An electronic package of the kind having a folded substrate is provided. The substrate is configured so that a stress concentration is created where folding is desired. In the present example, the stress concentration is created with first a resilient metal ground layer that resists bending and has an edge that promotes the creation of a stress concentration in a flexible layer at or near the edge. A second metal ground layer resists bending in another portion of the substrate, and also has an edge creating a stress concentration in a different area of the flexible layer. The portions of the substrate having the first and second resilient metal ground layers can be folded over one another with substantially no bending in these portions, while a fold portion between the edges bends to allow for folding of the substrate.

Abstract: Disclosed is a semiconductor device constructed such that a lead wire extending from an interposer is connected to a pad of a chip, wherein the chip is bonded to a resin molding with a high mechanical strength. In the semiconductor device of the present invention, the lead wires extending from the interposer formed of a polyimide film are connected to the pad of the chip, and the lead wires are arranged sparse. Dummy lead wires irrelevant to the electrical connection are also arranged in addition to the lead wires extending from the interposer so as to increase the total number of lead wires supporting the chip so as to permit the chip 11 to be bonded to the resin molding 15 with a high mechanical strength. The dummy lead wires mounted to the interposer together with the lead wires serve to improve the bonding strength between the resin molding and the chip.

Abstract: In a semiconductor chip having electrodes formed on the top surface, and electrodes or an insulation layer formed on the back surface, the top-surface electrodes are loop-connected with the back-surface electrodes by wire bonding, or, the top-surface electrodes are connected with the back-surface electrodes or an insulation layer by conductive clip, or by deposited conductive materials. The semiconductor chips thus produced are stacked, and wires, conductive clips, or conductive materials are connected and fixed to each other to produce a stacked semiconductor device in which semiconductor chips of the same size are densely packaged. Thus, a semiconductor device is provided which enables high-density packaging of semiconductor chips even of the same size.

Abstract: A main lead (2) is a single body comprised of an inner lead (2a) and an outer lead (2b) which are integrally formed, the bonding wires are arranged in parallel and fixed onto the inner lead (2a) by the wire bonding portions (3b), and the outer lead are exposed from the mold resin to the outside for electrical connection, and a plurality of through holes (8) penetrating the main terminal lead are formed in the outer vicinity of the wire bonding portions (3b) within the inner lead (2a), and the through holes are arranged substantially in parallel to the arrangement direction of the wire bonding portions (3b) so as to correspond to the entire wire bonding portions (3b).

Abstract: An electronic package and packaging method in which integral convective fins are formed of portions of a leadframe from which electrical leads are also formed. The leadframe comprises a base and first and second sets of leads extending from the base. The first set of leads is separated from the base and from the second set of leads, such that each lead of the first set has an interior end adjacent but separate from the base, and each lead of the second set has an interior portion that remains attached to the base. A circuit device is mounted to the base and electrically connected to the interior ends of the first set of leads. The device, base, and interior ends and portions of the leads are then encased within a housing. Exterior ends of the leads remain outside the housing as package terminals and thermal dissipaters.

Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.

Abstract: A stackable semiconductor package is disclosed that includes a semiconductor die coupled to a metal leadframe. The semiconductor die is coupled to a die pad and is electrically coupled to leads of the leadframe. The semiconductor die, the die pad, and an inner lead portion of each of the leads is embedded in an encapsulant, and an outer lead portion of each of the leads is free of the encapsulant. A surface of the die pad and of the inner lead portion of each of the leads is exposed in a plane with an exterior first surface of the encapsulant. The outer lead portion is vertically such that a mounting surface of the outer lead portion is provided below an opposite second surface of the encapsulant. Other semiconductor packages or electronic devices may be stacked on and electrically coupled to the exposed surface of the inner lead portions.

Abstract: An electronic component has a chip stack with a first semiconductor chip, a second semiconductor chip, and a large number of flat conductors configured in between the first semiconductor chip and the a second semiconductor chip. The flat conductors have a central section on which the semiconductor chips are mounted. First bonding connections connect the first semiconductor chip to inner sections of the flat conductors. Second bonding connections connect the second semiconductor chip to transitional sections of the flat conductors. The outer sections of the flat conductors project out of a package.

Abstract: A wiring board includes a substrate, and an interconnect pattern which is formed on the substrate and includes a land. A penetration hole, which exposes the substrate, is formed in the land. The penetration hole is formed in a region along a periphery of the land.

Abstract: A rectification chip terminal structure for soldering a rectification chip on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a helical buffer portion, a spacer zone containing a space, a tapered section inclining towards the center of the terminal, a bend spot having latch rings to provide coupling, and a deck having a bulged ring. The structure can prevent bending and deformation under external forces, and form a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Abstract: An integrated circuit package comprises a set of bond fingers for connecting wire bonds from the chip, the bond fingers being placed overlapping on a transverse axis from the chip and extending inwardly and outwardly from vias positioned at different positions along the transverse axis, so that wire bonds connected to adjacent fingers have the same length.

Abstract: A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.

Abstract: A semiconductor component for electrical coupling to a substrate (230) includes: a semiconductor chip (110); a non-leaded leadframe (120) including a plurality of electrical contacts (130) located around a periphery (111) of the semiconductor chip; a first electrical conductor (140) electrically coupling together the semiconductor chip and the non-leaded leadframe; and a mold compound (210) disposed around the semiconductor chip, the first electrical conductor, and the plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts includes: a first surface (310) having a first surface area for electrically coupling to the semiconductor chip; and a second surface (320) opposite the first surface and having a second surface area for electrically coupling to the substrate, where the second surface area is larger than the first surface area.

Abstract: A technique is provided for dissipating heat from an integrated circuit within a package. A thermally conductive strip may be installed between an integrated circuit and a substrate before packaging. The package is formed from molded epoxy formed around the integrated circuit and substrate with a portion of the thermally conductive strip extending beyond the confines of the package. Heat is conducted from the integrated circuit through the thermally conductive strip to the environment surrounding the package. A thermally conductive strip may be installed within a package by an adhesive or other mechanically means. A thermally conductive strip may be comprised of a metallic foil or other thermally conductive material.

Abstract: A leadframe of a conductive material includes a central region to accommodate a chip and a plurality of connecting fingers extending at least from one side in the direction of the central region, a contact region being provided adjacent to the central region on at least some of the connecting fingers. The course of the connecting fingers is such that a sectional face in an arbitrary imaginary cross-section at right angles to the main face of the leadframe has leadframe material. In such a case, it is attempted to keep cross-sections in a component without leadframe material as small as possible.

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

Abstract: A method and apparatus for supporting a microelectronic substrate. The apparatus can include a microelectronic substrate and a support member carrying the microelectronic substrate. The apparatus can further include a first connection structure carried by the support member. The first connection structure can have a first bond site configured to receive a flowable conductive material, and can further have at least two first elongated members connected and extending outwardly from the first bond site. Each first elongated member can be configured to receive at least a portion of the flowable conductive material from the first bond site, with none of the first elongated members being electrically coupled to the microelectronic substrate. The assembly can further include a second connection structure that is electrically coupled to the microelectronic substrate and that can include second elongated members extending away from a second bond site.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate includes at least one electrical ground plane and includes a plurality solder balls formed on a surface thereof. The solder balls include a set of “thermal” solder balls that are positioned near the perimeter of the package and electrically connected with a ground plane of the package. The IC die is electrically connected with the ground plane that is connected with the “thermal” solder balls. A heat spreader is mounted on the package with conductive mounting pegs that are electrically connected with the ground plane. The heat spreader is in thermal communication with the die and also in thermal communication with the set of “thermal” solder balls. This configuration enables a portion of the heat generated by the die to be dissipated from the die through the heat spreader into the set of “thermal” solder balls.

Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.

Abstract: A semiconductor device (700) having a leadframe with a first plurality of segments (110) having a narrow end portion (111) in a first horizontal plane (211) and a wide end portion (112) in a second horizontal plane (212). The leadframe further includes a second plurality of segments (120) having a narrow center portion (121) in the first horizontal plane, at least one wide center portion (122) in the second horizontal plane, and narrow end portions (123) in a third horizontal plane (213), which is located between the first and second planes.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A semiconductor device includes a base substrate provided with a base wiring. A first substrate includes a first wiring to be electrically connected to the base wiring and is provided above the base substrate. A first semiconductor element includes a first electrode to be electrically connected to the first wiring and is provided between the base substrate and the first substrate. A second substrate includes a second wiring to be electrically connected to the base wiring and is provided above the first substrate. A second semiconductor element includes a second electrode to be electrically connected to the second wiring and is provided between the first substrate and the second substrate and above the first semiconductor element. The first substrate has a first region where the first semiconductor element is provided below, a second region where a portion of the first wiring that connects to the base wiring is located, and a first bent section between the first region and the second region.

Abstract: A method for manufacturing and packaging an integrated circuit includes following steps: pressure a continuous pin material and a base board area at first; then cut off pin material into several pin units, accommodate each pin units into respective position in a mould, and ejecting plastic into the mould gap to shape a pin unit, then remove waste part of the pin material after removing down the mould parts; put four pin units and a base board into a rectangle mould, then eject plastic again into mould gap, after that cut off waste part of the base board to attain an IC socket; stick an IC chip on top of the base board of the IC socket and wire it. Finally, cover and stick a panel on the IC socket to finish the whole IC packaging procedures.

Abstract: A stacked IC includes a first IC package unit, a second IC package unit and an interface layer. The first IC package unit includes an IC chip, an encapsulant resin and a plurality of lead wires. The IC chip is encapsulated by the encapsulant resin. Each of the lead wires includes a first end connected to the IC chip and encapsulated by the encapsulant resin, a second end extending outside the encapsulant resin, and a bend portion arranged between the first end and the second end and having at least one surface exposed outside of the encapsulant resin. The second IC package unit has the same structure as the first IC package unit. The interface layer is sandwiched between the first IC package unit and the second IC package unit, and has a first side connected to the bend portion of the first IC package unit and a second side connected to the second end of the second IC package unit.

Abstract: An electrical connector is formed from a sheet of electrically conductive material that lies in between the two layers of nonconducting material that comprise the casing of an electrical chip. The connector is electrically connected to an electrical element embedded within the chip. An opening in the sheet is concentrically aligned with a pair of larger holes respectively bored through the nonconducting layers. The opening is also smaller than the diameter of an electrically conductive contact pin. However, the sheet is composed flexible material so that the opening adapts to the diameter of the pin when the pin is inserted therethrough. The periphery of the opening applies force to the sides of the pin when the pin is inserted, and thus holds the pin within the opening and in contact with the sheet, by friction. The pin can be withdrawn from the connector by applying sufficient axial force.

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.

Abstract: Arrangements and methods of packaging integrated circuits in leadless leadframe packages configured for maximizing a die size are disclosed. The package is described having an exposed die attach pad and a plurality of exposed contacts formed from a common substrate material. The contacts, however, are thinned relative to the die attach pad. In one embodiment, an inner region of the contacts is thinned. In another embodiment, an outer region of the contacts is also thinned. A die is mounted on the die attach pad and wire bonded to the contacts. Since the inner region and sometimes together with the outer region of the contact are lower than the die attach pad being wire bonded to, the size of the die can be relatively increased to overhang over the contact, thereby maximizing the die size in the package. A plastic cap is molded over the die, contacts, and bonding wires while leaving the bottom surface of the contacts exposed.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: A method for producing a die package is disclosed. A bumped die comprises solder bumps mounted to a leadframe including a first lead comprising a first locating hole and a second lead comprising a second locating hole. The solder bumps are present in the first and second locating holes, and a molding material is formed around the die.

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices. The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general. For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with. For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

Abstract: A folded flex circuit interconnect increases a number of interconnection pads of a grid array interface available to accommodate high count outputs from distinct circuit elements. The circuit interconnect includes a substrate capable of being folded, a conductor layer adjacent to a surface of the substrate, and a pad array having an interconnection pad connected to the conductor layer at a first end of the circuit interconnect. The pad array is part of the grid array interface. An optics module includes the folded flex circuit interconnect and an optical unit. The folded flex circuit interconnect further includes an electrical interface at a second end that is connected to the conductor layer. The folded flex circuit interconnect connects to the optical unit using the electrical interface. The circuit interconnect connects the optical unit to a motherboard using the pad array at the first end.

Abstract: In a chip scale package, a chip is mounted in a cavity formed in a leadframe. The leadframe includes a plurality of leads that radiate from a heat dissipating part located in the cavity. Each lead extends from a thinner portion of inner lead in the cavity to a thicker portion of outer lead outside the cavity. The chip includes a plurality of bonding pads on which is respectively formed a layer of connecting material. The chip is attached on the heat dissipating material, and via the layer of connecting material, is electrically connected to the inner leads by thermal pressing. Via molding, the chip is encapsulated in the leadframe. The achieved package has a dimensional size that is approximately equal to that of the leadframe with an improved thermal dissipation.

Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.

Abstract: 058804113 A method and apparatus for supporting a microelectronic substrate. The apparatus can include a microelectronic substrate and a support member carrying the microelectronic substrate. The apparatus can further include a first connection structure carried by the support member. The first connection structure can have a first bond site configured to receive a flowable conductive material, and can further have at least two first elongated members connected and extending outwardly from the first bond site. Each first elongated member can be configured to receive at least a portion of the flowable conductive material from the first bond site, with none of the first elongated members being electrically coupled to the microelectronic substrate. The assembly can further include a second connection structure that is electrically coupled to the microelectronic substrate and that can include second elongated members extending away from a second bond site.

Abstract: A semiconductor device of the present invention has two inner inner leads to be bonded with inner-side bump electrodes each placed at a position which is a relatively large distance apart from the edge of a semiconductor chip, between outer-side bump electrodes each placed at a position which is a relatively small distance apart from the edge of the semiconductor chip. At least one of the inner inner leads is bent in accordance with a bonding position with the inner-side bump electrode.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: An improved dual die package is disclosed. The dual die package includes a first lead frame connected to a first semiconductor chip and a second lead frame connected to a second semiconductor chip. The first leads and the second leads are electrically connected to one another using a wirebonding process rather than a thermocompression process thereby allowing conventional packaging equipment to be used when manufacturing a dual die package.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.