Abstract: In the power semiconductor module, a wiring metal plate electrically connects between power semiconductor elements joined to the circuit pattern, and between the power semiconductor elements and the circuit pattern. Cylindrical main terminals are joined, substantially perpendicularly, to the wiring metal plate and the circuit pattern, respectively. A cylindrical control terminal is joined, substantially perpendicularly, to one of the power semiconductor elements.

Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.

Abstract: A power semiconductor device in which transfer molding resin seals: a metallic circuit substrate; a power semiconductor element joined to a wiring pattern; and a side surface of a cylindrical external terminal communication section provided on the wiring pattern and to which an external terminal can be inserted and connected. The cylindrical external terminal communication section is substantially perpendicular to a surface on which the wiring pattern is formed. An outer surface of a metal plate of the metallic circuit substrate and a top portion of the cylindrical external terminal communication section are exposed from the transfer molding resin. The transfer molding resin is not present within the cylindrical external terminal communication section.

Abstract: In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package.

Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract: A multilayer semiconductor device includes an interconnect substrate provided with first electrode lands and connection terminals on a top surface; a semiconductor chip mounted on the top surface of the interconnect substrate; first connecting members connecting the first electrode lands to a circuit formation surface of the semiconductor chip; first metal posts provided on the connection terminals; encapsulating resin filling a space between the interconnect substrate and the semiconductor chip; a package provided with second electrode lands on a main surface; and second connecting members electrically connecting the first metal posts to the second electrode lands.

Abstract: The power semiconductor module includes: a circuit substrate; power semiconductor elements joined to element mounting portions of the wiring pattern on the circuit substrate; the cylindrical external terminal communication section joined to the wiring pattern; circuit forming means for connecting between portions that require electrical connection therebetween; and transfer molding resin for sealing these components. The cylindrical external terminal communication section is a metal cylinder, and the cylindrical external terminal communication section has a hole filled with gel.

Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.

Abstract: A module substrate has an interconnection electrode that is exposed at a side end face thereof. A semiconductor component including an IC chip is mounted on the module substrate. A molded part comprising a resin is formed so as to cover at least a part of the semiconductor component. A coating with higher heat conductivity than the molded part is formed on the surface of the molded part by applying a paste made of material with higher heat conductivity than the molded part. This improves heat dissipation. The coating can be formed such that it extends to the surface of the main substrate on which the module substrate with the semiconductor component is mounted and comes into contact with the interconnection electrode on the surface of the main substrate. This further improves heat dissipation.

Abstract: A bump array structure for an integrated circuit is presented. An array of metal alloy bumps is disposed on a surface of the integrated circuit. The array of metal alloy bumps is configured to receive input from a multi-layer substrate package and transmit output to the multi-layer substrate package. The array defines a first portion of metal alloy bumps around the periphery of the surface of the integrated circuit configured to provide power and ground signals for the integrated circuit. The array further defines a second portion of metal alloy bumps providing power and ground for the integrated circuit, located between opposing sides of the periphery of the integrated circuit. Metal alloy bumps not contained in either the first or the second portion of the array are configured for input and output signals between the integrated circuit and the multi-level substrate package.

Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside a conductive pillar location; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond.

Abstract: Methods of manufacturing a honeycomb extrusion die comprise the steps of coating at least a portion of a die body with a layer of conductive material and modifying the die body with an electrical discharge machining technique. The method then further includes the step of chemically removing the layer of conductive material, wherein the residual material from the electrical discharge machining technique is released from the die body.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board.

Abstract: A chip adapter used to install a chip on a first chip arranging area of a circuit board includes a board. The size of the board has the same size as the first chip arranging area of the circuit board. Edges of the chip adapter define a number of gaps corresponding to first pads of the circuit board. A second chip arranging area of the same size as the chip is arranged in a center of the chip adapter. A number of second pads are arranged around the second chip arranging area of the chip adapter corresponding to pins of the chip. Each second pad is electrically connected to a sidewall of the corresponding gap of the chip adapter.

Abstract: A semiconductor product is constructed of a wiring substrate in which pads for pin connection are formed, and a substrate with pins in which pins are disposed. The substrate with the pins is formed so that one end of the pin is exposed to one surface of a resin substrate formed by resin molding and the other end of the pin extends from the other surface of the resin substrate and one end of the pin is bonded to a pad of the wiring substrate through a conductive material.

Abstract: An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.

Abstract: A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes.

Abstract: Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate according to the exemplary embodiment of the present invention includes a head part having one surface opposite to the package substrate and the other surface that is an opposite side to the one surface; and a connection pin having a pin shape bonded to the other surface of the head part, wherein the head part has a concave depression part toward the package substrate.

Abstract: A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.

Abstract: The present invention relates to a semiconductor package transformer. There is provided a semiconductor package transformer including: a case where an opening into which a semiconductor package having a chip mounted on a substrate is inserted is formed on its front surface and an open part exposing is formed on its upper surface; and a plurality of holes that are formed on the bottom surface of the case.

Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.

Abstract: A semiconductor package of the present invention, includes a wiring substrate, a lead pin fixed to a connection pad on one surface side of the wiring substrate by solder, and a reinforcing resin layer formed on a surface of the wiring substrate on which the lead pin is provided and having a projection-shaped resin portion which projects locally around the lead pin and covers a side surface of a base portion side of the lead pin. The projection-shaped resin portion has a top surface extending from an outer peripheral portion of the lead pin to an outside, and a side surface constituting a non-identical surface to the top surface.

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract: Embodiments of the present invention relate to an improved die layout for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: A connection device between two components includes a hollow conductive insert, into which is fitted another conductive insert, the electrical connection between the two inserts being provided by means of a solder element.

Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).

Abstract: A microelectronic connection component includes a substrate having a first surface, a second surface and a peripheral edge. First and second terminals are exposed at the first surface of the substrate. Wire bond pads are exposed proximate the peripheral edge of the substrate at the first surface. First conductive paths couple the first terminals to the wire bond pads. Bonding leads extend beyond the peripheral edge of the substrate. Second conductive paths couple the second terminals to the bonding leads.

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract: A control device has a base plate, a cover plate coupled to the base plate, a cavity formed between the base plate and the cover plate, a circuit carrier disposed in the cavity, and a conducting track carrier electrically coupled to the circuit carrier. The base plate has a continuous recess that is configured and arranged for feeding a casting compound into the cavity between the base plate and the cover plate. The casting compound is embodied to at least partly enclose the circuit carrier and/or the conducting track carrier in a vibration-damping manner.

Abstract: Provided is a substrate processing apparatus comprising: a process chamber for processing a substrate; a heater for heating an interior of the process chamber; a holder for sustaining the substrate in the process chamber; and a substrate transfer plate for transferring the substrate to the holder; wherein the holder has a retainer for sustaining the substrate at its outer periphery and a main body for sustaining the retainer, a portion of the retainer extending at least from a back region thereof with respect to an inserting direction of the substrate transfer plate to a region adjacent thereto and to be sustained by the main body and lying outer than the substrate upon putting the substrate on the retainer being made thicker than other portions of the retainer.

Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.

Abstract: A contact spring applicator is provided which includes an applicator substrate, a removable encapsulating layer and a plurality of contact springs embedded in the removable encapsulating layer. The contact springs are positioned such that a bond pad on each contact spring is adjacent to an upper surface of the removable encapsulating layer. The contact spring applicator may also include an applicator substrate, a release layer, a plurality of unreleased contact springs on the release layer and a bond pad at an anchor end of each contact spring. The contact spring applicators apply contact springs to an integrated circuit chip, die or package or to a probe card by aligning the bond pads with bond pad landings on the receiving device. The bond pads are adhered to the bond pad landings. The encapsulating or release layer is then removed to separate the contact springs from the contact spring applicator substrate.

Abstract: The present disclosure describes a unique pin configuration for mounting of circuit packages to corresponding host circuit boards. For example, an apparatus according to embodiments herein comprises a circuit, a substrate, and multiple conductive leads. The substrate has a surface on which the circuit (e.g., an integrated circuit) is mounted. The multiple conductive leads extend, in an orthogonal manner relative to the surface, through the substrate to electrically connect the circuit to a host circuit board. According to one embodiment, each respective conductive lead of the multiple conductive leads has been altered to produce a contact element (e.g., an L-shaped bend, J-shaped bend, etc.) at an axial end of the respective conductive lead opposite the substrate to solder the axial end of the respective conductive lead (i.e., contact element) to a surface mount pad of the host circuit board.

Abstract: By creating a package (MVLC) that has a redundant set of pins, twice as many points of contact are generated. More contacts create more routing and component placement options. Incorporating slots on the underside of the MVLC will promote radiation under the MVLC. By creating a mating piece (a Saddle) discrete components can be moved to a more desirable area of the main printed circuit board or placed in and on the Saddle itself. A Saddle may or may not require a flex circuit. A Saddle could be no more than a flex circuit. Positioning capacitors in particular on the Saddle makes a supply current become more effective, which improves performance. All of the Saddle layers are designed to enhance performance and/or reduce the member of discrete components required on the main printed circuit board near the MVLC. In general, creating more usable room on the main printed circuit board promotes a better design and invites circuit expansion.

Abstract: An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first substrate may hold power-handling devices and may be specially constructed to dissipation heat and to facilitate fast and inexpensive manufacturing. The second substrate may hold packaged components of control circuitry for the power-handling devices, and may be specially constructed to enable fast and inexpensive wiring design and fast and inexpensive component assembly. The first substrate may be used with different designs of the second substrate.

Abstract: An assembly for testing microelectronic devices includes a microelectronic element having faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The assembly also includes a plurality of support elements disposed between the microelectronic element and the substrate for supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements.

Abstract: In a stacked package in which a plurality of packages having semiconductor elements mounted on substrates are stacked, while being electrically connected together, by use of connection sections, wherein the connection sections are formed from pillar-like members and solder joint sections and the upper package is supported on the lower package by pillar-like members.

Abstract: An integrated circuit package includes a cover plate disposed on a substrate mounted with an integrated circuit chip thereon. The chip is formed with first solder pads coupled respectively and wiredly to pin terminals on the substrate, and second solder pads coupled respectively and wiredly to pinhole terminals in the cover plate, and includes a main circuit unit, a pin transmission unit interconnecting electrically first ports of a main circuit unit and the first solder pads, a pinhole transmission unit interconnecting electrically second ports of the main circuit unit, and a control unit coupled to the pin and pinhole transmission units, and operable to control operation of the pin and pinhole transmission units such that each first port is coupled to a selected first solder pad through the pin transmission unit and that each second port is coupled to a selected second solder pad through the pinhole transmission unit.

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.

Abstract: According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface.

Abstract: A multilayer electronic component including a resin layer disposed on a mounting board side is mounted on a mounting board, and has a structure such that, even when deformation, such as deflection and strain, occurs, a stress on the multilayer electronic component is relieved. In the multilayer electronic component, ends of columnar conductors protrude from a main surface of a resin layer facing the outside. The multilayer electronic component is mounted on a mounting board, and the ends of the columnar conductors are electrically connected to conductive lands. In this case, a predetermined gap is formed between the multilayer electronic component and the mounting board.

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract: An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of the board. The land pin may be electrically connected to the integrated circuit chip.

Abstract: An integrated circuit package system comprising: providing a first conductive line adjacent to a second conductive line; forming a first connection stack over the first conductive line with the first connection stack overhanging the second conductive line; connecting an integrated circuit device and the first connection stack; and encapsulating the integrated circuit device and the first connection stack.

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract: A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described.

Abstract: In an example embodiment, there is a package substrate (200) for mounting an integrated circuit (IC) device (205). The package substrate comprises an IC device placement area (290) surrounded by pad landings (215). For placing surface mount devices in vicinity of the pad landings, there is a plurality of component pads (235a, 235b, 235c, 235d). The plurality of component pads surrounds the pad landings (215). A plurality of device pins (225a, 225b, 225c, 225d, 245a, 245b, 245c, 245d) surrounds the component pads. One or more of the plurality of device pins, having fine-pitch conductive paths (270), couple the one or more of the plurality of device pins to a set of corresponding pad landings (215) or to a set of corresponding component pads; the fine-pitch conductive paths (270) traverse regions between the plurality of component pads.