Abstract: Methods for fabricating a coolant-cooled component assembly are provided, which include providing a multi-component assembly and a module lid with openings aligned over respective electronic components. Thermally conductive elements are disposed within the openings, each including opposite coolant-cooled and conduction surfaces, with the conduction surface being thermally coupled to the respective electronic component. A manifold assembly disposed over the module lid includes inner and outer manifold elements, with the inner element configured to facilitate flow of coolant onto the coolant-cooled surfaces. The outer manifold element is disposed over the inner manifold element and coupled to the module lid, with the inner and outer manifold elements defining a coolant supply manifold, and the outer manifold element and module lid defining a coolant return manifold.

Abstract: A smart socket is provided. The smart socket has a set of power sockets, configured for a set of power pins of a smart plug to plug into, a driving pin and a set of detection pins, configured for forming a circuit with a set of feedback pins of a smart plug when the set of power pins is plugged into the power sockets, and an identification code module, configured for obtaining an identification code of an electric appliance, from the circuit, to which the smart plug belongs.

Abstract: In an embodiment, a printed circuit board includes a number of bond pads formed on a surface of the printed circuit board. At least a portion of the number of bond pads is arranged in an array of bond pads that includes a number of rows and a number of columns. A first portion of the number of rows include a number of adjacent rows having a first pitch and a second portion of the number of rows include at least one pair of adjacent rows having a second pitch different from the first pitch. In an embodiment, the second pitch is greater than 0.5 mm and less than 1.5 mm. In some embodiments, the array of bond pads can include at least one row of no-connect bond pads.

Abstract: A chip stack structure taking a wafer as a stacking base and stacking chips thereon is provided. The chip stack structure is capable of achieving high density electrode bonding and breaking the bottleneck of requiring interposer to serve as a transferring interface in three dimensional chip package. The chip stack structure is easily fabricated and compatible with wafer level process, so as to reduce processing time and manufacturing cost. A method for fabricating the chip stack structure is also provided.

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Abstract: A wiring board and a method for manufacturing the wiring board reinforced by means of a resin is provided. Embodiments of the wiring board allow for reliable attachment of a connection member, like a socket, to a terminal member. For example, a base of terminal pins is put on pin grid array (PGA) terminal pads, and a bonding material paste including solder and an electric insulation material made of a resin is placed on each of the PGA terminal pads. The bonding material paste is then heated to fuse the solder and soften the electric insulation material. Subsequently, the bonding material paste is cooled to solidify the solder and bond each of the bases to a corresponding PGA terminal pad and form an electric insulation surface layer on an exposed surface of each of solder junctions to which the respective bases are bonded.

Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.

Abstract: Disclosed is a surface mount device to be mounted on a base member, including plural lead units, each of the plural lead units including, a lead including a body portion and a foot formed at an end of the lead; a solder portion formed at the foot of the lead to protrude toward the direction of the base member to have a summit portion, and a diffusion prevention portion provided on the lead for preventing a diffusion of a solder along the body portion of the lead.

Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.

Abstract: A plastic SON/QFN package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package; each pin has a long axis, the long axes of the pair forming a non-orthogonal angle.

Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.

Abstract: The invention relates to a method for fabricating a bond by providing a body including a metallic surface provided with an inorganic, dielectric protective layer. The protective layer covers at least one surface zone of the metallic surface in which the metallic surface is to be electrically conductive bonded to a contact conductor. To fabricate the bond, a portion of a provided contact conductor above the surface zone is pressed on to the protective layer and the body so that the protective layer is destroyed above the surface zone in achieving an electrically conductive bond between the metallic surface and the contact conductor.

Abstract: A power semiconductor device with improved productivity, reduced size and reduction of amounting area therefore is provided. In the provided power semiconductor device, an external terminal does not limit an increase in current. The power semiconductor device is sealed with transfer molding resin. In the power semiconductor device, a cylindrical external terminal communication section is arranged on a wiring pattern so as to be substantially perpendicular to the wiring pattern. An external terminal can be inserted and connected to the cylindrical external terminal communication section. The cylindrical external terminal communication section allows the inserted external terminal to be electrically connected to the wiring pattern. A taper is formed at, at least, one end of the cylindrical external terminal communication section, which one end is joined to the wiring pattern.

Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Abstract: To prevent the breakage of the joint between a ceramic substrate and a glass epoxy substrate. The copper column is formed by a wiredrawing step for drawing a copper wire formed linearly to a predetermined diameter; a cutting step for cutting the copper wire, which has been drawn in the wire drawing step, in a predetermined length; a pressing step for pressing one end of the copper wire, which has been cut in the cutting step, in a longitudinal direction to form a copper column member; and an annealing step for annealing the copper column member, which has been formed in the pressing step, by maintaining a heating period of 60 minutes or longer at 600° C. or higher. Thereby, the Vickers hardness of the copper column becomes is 55 HV or less and the copper column is softened.

Abstract: A plastic SON/QFN package (300) for high power has a pair of oblong metal pins (320, 321) exposed from a surface of the plastic (301), the pins straddling a corner (302) of the package; each pin has a long axis (320a, 321a), the long axes of the pair forming a non-orthogonal angle. Package (300) further includes a chip assembly pad (310), acting as a thermal spreader.

Abstract: A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections.

Abstract: A packaging substrate and a semiconductor package each include: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer.

Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.

Abstract: Disclosed herein is a power module package including: a substrate including a metal layer, a first insulation layer formed on the metal layer, a first circuit pattern formed on the first insulation layer and including a first pad and a second pad spaced apart from the first pad, a second insulation layer formed on the first insulation layer to cover the first circuit pattern, and a second circuit pattern formed on the second insulation layer and including a third pad formed on a location corresponding to the first pad and a fourth pad spaced apart from the third pad; a semiconductor chip mounted on the second circuit pattern; one end being electrically connected to the semiconductor chip, and another end protruding from the outside, wherein the first pad and the third pad, and the second pad and the fourth pad have different polarities.

Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.

Abstract: An electronic device is disclosed. The electronic device comprises at least one electronic chip and a package for the electronic chip. The package comprises a laminate substrate, wherein the electronic chip is attached on the laminate substrate. The laminate substrate comprises one or more conduction layers, one or more insulation layers and a plurality of pads formed in a conduction layer on the side of the laminate substrate opposite to the side connected to the electronic chip. Furthermore, the package comprises an insulation body formed around the electronic chip. Moreover, the package comprises a plurality of electrodes that extend through the insulation body. For each pad of the laminate substrate, wiring is formed in the one or more of conduction layers and in one or more vias passing through the one or more insulation layers for electrically connecting the pad with at least one of the electrodes.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: Disclosed herein is a power module package. The power module package includes a substrate having one surface formed with a circuit pattern including a chip mounting pad and an external connection pad and the other surface; a semiconductor chip mounted on the chip mounting pad; and an external connection terminal having one terminal and the other terminal, the one terminal being connected to the external connection pad and the other terminal protruding to the outside, in which the external connection pad and the external connection terminal are bonded to each other by welding.

Abstract: An interconnect assembly that operates in environments well exceeding 200° C. without degradation and/or failure. The interconnect assembly of the present invention eliminates the incompatible metal interfaces of the prior art and relies on aluminum first-metal wire to electrically connect to first-metal pads on a chip and a second-metal wire to electrically connect to second-metal plated contacts on a package. Both wire types are then electrically connected together utilizing a high temperature transition pad disposed between the chip and contacts on the package, therefore eliminating incompatible metal interfaces of the prior art.

Abstract: A semiconductor substrate including a carrier, a first conductive layer and a second conductive layer is disclosed. The carrier has a first surface, a second surface, and a concave portion used for receiving a semiconductor element. The first conductive layer is embedded in the first surface and forms a plurality of electric-isolated package traces. The second conductive layer is embedded in the second surface and electrically connected to the first conductive layer. The semiconductor substrate can be applied to a semiconductor package for carrying a semiconductor chip, and combined with a filling structure for fixing the chip. Furthermore, a plurality of the semiconductor substrates can be stacked and connected via adhesive layers, so as to form a semiconductor device with a complicated structure.

Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region.

Abstract: A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element.

Abstract: A semiconductor package includes a plurality of electrical connectors, a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads, and a plurality of input/output signal pads that carry signals to and from the core logic. Each pad of the semiconductor die has an electrical connector of the plurality of electrical connectors extending therefrom. The semiconductor package also includes a package substrate having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer. The first metal redistribution layer provides a first electrical potential to each of the input-power contact pads, and the second metal redistribution layer provides a second electrical potential to each of the output-power contact pads. Each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract: A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A power semiconductor device includes a power semiconductor module having cylindrical conductors which are joined to a wiring pattern so as to be substantially perpendicular to the wiring pattern and whose openings are exposed at a surface of transfer molding resin, and an insert case having a ceiling portion and peripheral walls, the ceiling portion being provided with external terminals that are fitted into, and passed through, the ceiling portion, the external terminals having outer-surface-side connecting portions at the outer surface side of the ceiling portion and inner-surface-side connecting portions at the inner surface side of the ceiling portion. The power semiconductor module is set within the insert case such that the inner-surface-side connecting portions of the external terminals are inserted into the cylindrical conductors.

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract: A power semiconductor device includes a conductive insertion member as an external terminal projecting from a surface of the power semiconductor device facing a printed wiring board. The printed wiring board includes a conductive fitting member mounted on a pad part of the printed wiring board. The fitting member receives the insertion member therein when the power semiconductor device is connected to the printed wiring board. The insertion member has a recessed portion formed on a side surface of the insertion member. The fitting member has a projecting portion with elasticity formed on an inner side surface of the fitting member. The elasticity causes the projecting portion of the fitting member to contact the recessed portion of the insertion member under pressure when the insertion member is inserted into the fitting member.

Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.

Abstract: A method of manufacturing an interconnect structure for a semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity.

Abstract: A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.

Abstract: A method of manufacture of a semiconductor packaging system includes: providing a base substrate having edges; mounting an electrical interconnect on the base substrate; and applying an encapsulant having a reference marker and an opening over the electrical interconnect, the reference marker around the electrical interconnect based on physical locations of the edges.

Abstract: A lead pin for a package substrate includes a coupling pin, a head portion, and a flowing prevention portion. The coupling pin is to be inserted into a hole which is formed in an external substrate. The head portion is formed at one end of the coupling pin. The flowing prevention portion is formed on the top surface of the head portion and prevents a solder paste from flowing toward the coupling pin on the top surface of the head portion when the head portion is mounted on the package substrate.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: The present disclosure relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking.

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.