Abstract: Solder balls may be arranged in hexagonal array on an integrated circuit package. The hexagonal array may increase the solder ball density, reducing solder ball fatigue. In some embodiments, the hexagonal array may be utilized under the die shadow and an orthogonal array may be used outbound thereof.

Abstract: A packaging substrate is formed of an array of packaging units. Each packaging unit has a chip pad carrying a chip, a plurality of pins arranged around the chip pad and spaced from one another and the chip pad by an open space, an insulative member formed of a plurality of insulative member layers and filled up the open space, and a set of electrical elements, which includes a plurality of plated through holes cut through the insulative member layers, first lead wires embedded in the insulative member to electrically connect the plated through holes to one another, and second lead wires that connect the plated through holes to a respective adjacent pin.

Abstract: A semiconductor package is disclosed with a recess (51) for an integrated circuit die (52). The recess is made by bending or deforming all layers of a package substrate, and therefore the recess contains circuitry to connect to the integrated circuit die. The integrated circuit die is electrically connected to the package substrate by either wirebonds (53a), TAB or die solder balls (53b). The package substrate (50), a single sided printed wiring board, has a thick metal core (100) and one or more thin build up layers.

Abstract: A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to attach the substrate to the package substrate.

Abstract: A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin.

Abstract: Solder joints coupling pins to a microelectronic package substrate are enshrouded with an encapsulation material. In this manner, pin movement is limited even if the pin solder subsequently melts.

Abstract: The present invention relates to a three-dimensional multichip stack electronic package structure and method for making the same, including a main substrate having at least a pin-hole set and at least a flexible substrate having at least a pin terminal. At least an electronic device including an active component and a passive component is attached to the flexible substrate by adhesion. In the flexible substrate, electric signals of the electronic device are delivered to the pin terminal through at least a conductive wire for transmitting electric signals. In assembly, the pin terminal of the flexible substrate is inserted into the pin hole of the main substrate. Then, the flexible substrate is folded so as to package the electronic device in a three-dimensional multichip stack manner.

Abstract: A memory card comprising a leadframe having a die pad, and an insert having a plurality of contacts. Attached to the die pad is a semiconductor die which is electrically connected to the contacts of the insert. A body covers the die pad and the semiconductor die and partially covers the insert such that the contacts are exposed in an exterior surface of the body.

Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

Abstract: Methods and structures to reduce in semiconductor packages the length of critical electrical connections between bond pads on one or multiple semiconductor chips and wire landing pads on a substrate have been achieved. An electrical connection becomes critical if high current, high speed or radio frequency signals have to be transported. Moving the wire landing pads of critical connections on the substrate closer to the semiconductor chip utilizing unpopulated spaces of an array grid design reduces the length of said wires. This could be a ball grid array (BGA) or any other kind of grid array. Said methods and structures invented are applicable to single-chip modules and to multi-chip modules. The design of the grid array has to be modified to provide free spaces for the wire landing pads of critical electrical connections within the grid array close to the semiconductor chip as required by the design rules. The design change can be done without increasing the number of solder balls or solder pins, etc.

Abstract: A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to attach the substrate to the package substrate.

Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

Abstract: A method for providing main power inductance to a switching power supply using bond wires of an integrated circuit packaging. A predetermined number of bond wires are connected serially between standalone die bond pads and no-connect pins of the packaging. An output of the switching power supply is connected to a first bond wire, and an output pin of the integrated circuit is connected to a last bond wire. A number of the bond wires, a length and a diameter of each bond wire, and a distance of the bond wires from a die attach paddle may be pre-selected to determined the main power inductance.

Abstract: A circuit carrier adapted for a pin grid array (PGA) package is disclosed. The circuit carrier comprises a substrate, at least one pin pad, at least one solder mask layer, at least one solder layer, at least one pin and a fixing layer. The pin pad is disposed over the surface of the substrate. The solder mask layer is disposed over the surface of the substrate, and exposing at least a portion of the pin pad. The solder layer is disposed over the pin pad. One end of the pin connects to the pin pad through the solder layer. The fixing layer is disposed over the solder mask layer, and covering the solder layer and a portion of a side surface of the pin. When the solder layer melts due to a high process temperature, the fixing layer helps to fix the pin to the pin pad.

Abstract: The present disclosure is directed to ball assignment schemes for ball grid array packages in integrated circuits with increased signal count. The ball assignment scheme includes an array of electrical contacts. The array has a first diagonal including a pair of signal contacts adjacent to a pair of first-type voltage supply contacts. The array further includes a crossing diagonal having a pair of adjacent second-type voltage supply contacts, which crosses the first diagonal between the pair of signal contacts such that the pair of second-type voltage supply contacts oppose one another relative to the first diagonal.

Abstract: An apparatus for heat dissipation in a chassis housing an electronic system, and a method for implementing the same. The apparatus comprises a heat sink base for collecting thermal heat. The apparatus further comprises a fin thermally coupled to the heat sink base for dissipating the thermal heat. The fin is arranged in the chassis to direct air flow from a first direction, that is originally directed at said fin, to a second direction.

Abstract: A wire bonding package has a housing having a plurality of pins, a circuit board installed inside the housing and having at least a trace connected to a pin of the housing, at least a die installed on the circuit board and having a plurality of bonding pads, and at least a bonding line connected between a bonding pad of the die and the trace of the circuit board so that the bonding pad of the die is electrically connected to the pin of the housing.

Abstract: A method is provided for manufacturing a semiconductor device, a semiconductor device, a circuit board, and an electronic apparatus. In such a semiconductor device, semiconductor chips can be readily aligned when they are stacked and terminals can be prevented from being short-circuited, thereby enhancing the reliability of the connection between electrodes of the semiconductor chips. According to the method, semiconductor chips are perforated, and a conductive material such as copper is filled into each perforation, thereby forming a terminal that contains the conductive material and has a recessed portion, disposed in the upper face thereof.

Abstract: A semiconductor package, containing two or more IC devices. The IC devices are oriented in the same manner and at least two IC devices are separated by a die paddle that is attached to the active face of one of the IC devices, inward of the electrical contact areas.

Abstract: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.

Abstract: A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array land pattern is described. The land pattern includes a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge of a perimeter of the array not fully populated with conductive pads, whereby spaces are created in the at least one edge by the missing conductive pads. The spaces create additional routing channels for signals from conductive pads within the array to be routed externally to the array through the at least one edge.

Abstract: There is a need to provide a semiconductor device in which strain in a bonding member resulting from the difference in thermal deformation between a lead electrode and a semiconductor chip, which are electrically bonded to each other by the bonding member, is reduced for an improved thermal fatigue lifetime and the semiconductor chip has an improved current carrying capacity and enhanced heat dissipation.

Abstract: The invention relates to a method for making an integrated circuit (40) of the surface-mount type the comprising, first of all, manufacture of a package having a rear face and a pin grid array extending under this rear face perpendicular thereto, and a ball (44) of low melting point alloy is then formed at the end of each pin surrounding this end and soldered thereto. The invention also relates to an integrated circuit (40) of the surface-mount type, comprising a package having a rear face and a pin grid array, of a cross section roughly constant along the pin (42), extending under the rear face perpendicular thereto. A ball (44) of low melting point alloy is soldered to the end of each pin (42) surrounding this end.

Abstract: Solder joints coupling pins to a microelectronic package substrate are enshrouded with an encapsulation material. In this manner, pin movement is limited even if the pin solder subsequently melts.

Abstract: An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; and a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit.

Abstract: An integrated circuit package includes EMI containment features. The EMI containment features may include a plurality of pins on a substrate of the integrated circuit package. The pins may be a peripheral row of pins in an array of pins. The pins may couple a lid of the package to at least one ground plane of a circuit board.

Abstract: A connection housing includes a base body with lateral walls, which extend around the base body on top and which enclose the component to be inserted as well as inner contacts that are arranged between the component and at least one lateral wall. Polymer protuberances for forming outer contacts are shaped onto the underside. The connection between the inner contacts of the top and the outer contacts of the underside is effected by micro-boreholes that are located underneath the component in the middle area of the base body. This results in the provision of a housing, which requires little space on a printed circuit board and which can be economically produced preferably while using laser structuring.

Abstract: A high electrical and thermal performance thick film ceramic ball grid array package with a laser cut die cavity is presented. The thick film ceramic ball grid array package may have a thick film ceramic substrate with a first side and a second side with a heat spreader or a heat sink on the second side. An IC die may be attached to the heat spreader or heat sink through the laser cut die cavity and wire bonded to pads on the first side of the ceramic substrate. The thick film ceramic substrate may have one or more integrated passive components.

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

Abstract: An electronic device and a method for producing the electronic device which has at least one microscopically small contact area for an electronic circuit having interconnects that are on a surface of a substrate. A three-dimensionally extending microscopically small contact element is integrally one-piece connected to the contact area.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate includes at least one electrical ground plane and includes a plurality solder balls formed on a surface thereof. The solder balls include a set of “thermal” solder balls that are positioned near the perimeter of the package and electrically connected with a ground plane of the package. The IC die is electrically connected with the ground plane that is connected with the “thermal” solder balls. A heat spreader is mounted on the package with conductive mounting pegs that are electrically connected with the ground plane. The heat spreader is in thermal communication with the die and also in thermal communication with the set of “thermal” solder balls. This configuration enables a portion of the heat generated by the die to be dissipated from the die through the heat spreader into the set of “thermal” solder balls.

Abstract: The device has a package with a base plate, and at least two terminal pins perpendicularly protruding from the base plate of the package. At least one of the terminal pins is a high-frequency terminal pin that transmits a high-frequency signal. The device has a flexible conductor arrangement with a plurality of interconnects. The conductor arrangement provides an electrical connection between the terminal pins of the package and electrical contacts of a printed circuit board. The conductor arrangement has contact regions for electrically connecting the interconnects to a terminal pin and to a contact of a printed circuit board. At least the region of the conductor arrangement that provides a connection to high-frequency terminal pin lies in a plane aligned substantially perpendicular to the plane of the base plate.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: Apparatus and methods are provided wherein the reflowable electrically conductive interconnect material coupling the interconnects and/or land-side components of a microelectronic package is protected from elevated temperatures, such as those associated with reflow processes and environments which exceed the melting temperature of the interconnect material. One embodiment of the method provides covering the interconnect material about the interconnects and/or land-side components with heat-resistant curable material which protects the interconnect material from the elevated temperature and provides structural support to the interconnects and/or land-side components at the elevated temperature.

Abstract: An electrical connector is formed from a sheet of electrically conductive material that lies in between the two layers of nonconducting material that comprise the casing of an electrical chip. The connector is electrically connected to an electrical element embedded within the chip. An opening in the sheet is concentrically aligned with a pair of larger holes respectively bored through the nonconducting layers. The opening is also smaller than the diameter of an electrically conductive contact pin. However, the sheet is composed flexible material so that the opening adapts to the diameter of the pin when the pin is inserted therethrough. The periphery of the opening applies force to the sides of the pin when the pin is inserted, and thus holds the pin within the opening and in contact with the sheet, by friction. The pin can be withdrawn from the connector by applying sufficient axial force.

Abstract: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

Abstract: An electronic package for use with a printed circuit board is provided. The electronic package includes a ground layer having an upper and lower section, a semiconductor chip, a conductive signal layer and a ground plane having a first section electrically connected to the upper section of the ground layer and a second section substantially planar with said lower section of said ground layer, the second section of the ground plane having an additional area to prevent cracking of a solder connection between the ground layer, the ground plane and the printed circuit board.

Abstract: A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. The traces or leads are routed under the die such that proper connections are established from the topside of the die to the appropriate mount locations of the printed circuit board. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.

Abstract: A low cost technique for packaging microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuit using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core assembly before lamination of the interposer.

Abstract: A stacked microelectronic assembly includes a dielectric element and a first and second microelectronic element stacked one atop the other with the first microelectronic element disposed between the second microelectronic element and the dielectric. The dielectric element has opposed first and second surfaces with conductive features exposed at the first surface and terminals exposed on the second surface. Preferably, the contact-bearing face of the first microelectronic element confronts the first surface of the dielectric with at least some of the conductive features being movable with respect to the contacts or terminals. By providing such movable features, joining units have heights of about 300 microns or less may be joined to the terminals thereby reducing the overall height of the microelectronic assembly to 1.2 mm and less.

Abstract: A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.

Abstract: A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

Abstract: 058804113 A method and apparatus for supporting a microelectronic substrate. The apparatus can include a microelectronic substrate and a support member carrying the microelectronic substrate. The apparatus can further include a first connection structure carried by the support member. The first connection structure can have a first bond site configured to receive a flowable conductive material, and can further have at least two first elongated members connected and extending outwardly from the first bond site. Each first elongated member can be configured to receive at least a portion of the flowable conductive material from the first bond site, with none of the first elongated members being electrically coupled to the microelectronic substrate. The assembly can further include a second connection structure that is electrically coupled to the microelectronic substrate and that can include second elongated members extending away from a second bond site.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus comprises an integrated circuit (IC) having a plurality of connection pins, a carrier socket configured to carry the IC. The carrier socket protects the pins of the IC from bending. In addition, the carrier socket straightens pins that have been bent prior to placing the IC into the carrier socket.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: A surface of an external electrode 3 of an electronic part 4 is formed with a coating containing resin ingredient. Thereby, adhesion strength and reliability may be significantly improved in mounting an electronic part onto a circuit board 1 through the medium of a conductive adhesive. Further, it will be able to mount an electronic part to an element to be mounted by utilizing a conductive adhesive forming an external electrode 3 as a connecting element. Further, surface roughness (Ra) of an external electrode 3 of an electronic part is set to 0.1 ?m or more and to 10.0 ?m or less and preferably to 1.0 ?m or more and to 5.0 ?m or less. Thereby, adhesion strength with a conductive adhesive may be significantly enhanced in comparison with a conventional electronic part presented.

Abstract: An area array type semiconductor package suitable for use in the formation of a 3-dimensional stack of the area array type packages. The area array type semiconductor package includes a circuit board, typically a tape circuit board, a semiconductor chip, bonding wires, an encapsulation body, solder posts, and solder balls. A plurality of the area array type semiconductor packages can be electrically connected through the corresponding solder balls and solder posts on adjacent packages to form semiconductor stack packages.

Abstract: A circuit substrate device composed of a circuit unit 2 and a multi-layer wiring substrate 3 in which a pattern conductor of the circuit unit 2 may be prevented from being warped or inundated. The circuit substrate device includes a circuit unit 2 having a pattern conductor formed by a thin film technique, and an insulating layer, and a multi-layer wiring substrate 3 having a connecting terminal portion 14 exposed from its major surface. The circuit unit is formed on a dummy substrate. The circuit unit is connected to the multi-layer wiring substrate 3 so that the pattern conductor is connected to the connecting terminal portion 14. The dummy substrate is then removed to give a structure comprised of the circuit unit 2 formed on the multi-layer wiring substrate 3. The pattern conductor of the circuit unit 2 is freed of warping or inundations along the direction of thickness of the circuit unit 2.

Abstract: A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board.

Abstract: The present invention relates to a carrier module for micro-BGA (&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.