Abstract: According to one embodiment, an electronic apparatus includes a housing, a battery pack, an ODD unit having a thickness smaller than the battery pack, and an additional device contained in the housing. The battery pack is arranged in a back section of the housing. The ODD unit is arranged to be one-sidedly shifted to a front section in the housing, and includes a front end portion opposed to the front section, and a back end portion opposed to the battery pack. The additional device is away from the front end portion of the ODD unit, and overlaps the back end portion of the ODD unit in the vertical direction.

Abstract: A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and arranged in the form of a ball grid array.

Abstract: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

Abstract: An electrically conductive pin comprising a pin stern and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head has an underside surface defining a continuous curve configured to allow gases to escape from a pin-attach solder region adjacent the underside surface.

Abstract: An apparatus, method, and system for providing a stress absorption layer for integrated circuits includes a stiffening layer adapted to limit flexing. A compliance layer is physically associated with the stiffening layer, with the compliance layer adapted to absorb stress caused by mismatched thermal properties between two materials. A thru hole passes through both the stiffening layer and the compliance layer, with the thru hole being adapted to receive a solder joint. The stress absorption layer contacts both a semiconductor package and a substrate. The solder joint disposed in the thru hole connects the semiconductor package to the substrate.

Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.

Abstract: An integrated circuit package includes a cover plate disposed on a substrate mounted with an integrated circuit chip thereon. The chip is formed with first solder pads coupled respectively and wiredly to pin terminals on the substrate, and second solder pads coupled respectively and wiredly to pinhole terminals in the cover plate, and includes a main circuit unit, a pin transmission unit interconnecting electrically first ports of a main circuit unit and the first solder pads, a pinhole transmission unit interconnecting electrically second ports of the main circuit unit, and a control unit coupled to the pin and pinhole transmission units, and operable to control operation of the pin and pinhole transmission units such that each first port is coupled to a selected first solder pad through the pin transmission unit and that each second port is coupled to a selected second solder pad through the pinhole transmission unit.

Abstract: The present invention relates to a semiconductor package transformer. There is provided a semiconductor package transformer including: a case where an opening into which a semiconductor package having a chip mounted on a substrate is inserted is formed on its front surface and an open part exposing is formed on its upper surface; and a plurality of holes that are formed on the bottom surface of the case.

Abstract: A semiconductor package of the present invention, includes a wiring substrate, a lead pin fixed to a connection pad on one surface side of the wiring substrate by solder, and a reinforcing resin layer formed on a surface of the wiring substrate on which the lead pin is provided and having a projection-shaped resin portion which projects locally around the lead pin and covers a side surface of a base portion side of the lead pin. The projection-shaped resin portion has a top surface extending from an outer peripheral portion of the lead pin to an outside, and a side surface constituting a non-identical surface to the top surface.

Abstract: A thin-film device incorporates: a substrate; an insulating layer, a plurality of lower conductor layers, a dielectric film, an insulating layer, a plurality of upper conductor layers and a protection film that are stacked in this order on the substrate; and a plurality of terminal electrodes. One of the terminal electrodes is connected to one of the lower conductor layers. The one of the lower conductor layers has a protruding portion that protrudes to extend more outward in a lateral direction than a side surface of the insulating layer. The one of the terminal electrodes has a concave portion that accommodates and touches at least part of the protruding portion, and touches the side surface of the insulating layer.

Abstract: A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced.

Abstract: A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins.

Abstract: A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

Abstract: A lead pin of a circuit includes a pin, an insulator that surrounds the pin, and a conductor that surrounds the insulator, the conductor including non-uniformity.

Abstract: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

Abstract: A conductive structure configured to connect a contact pad of a semiconductor device with a corresponding contact pad of a substrate. The conductive structure includes two interconnectable members, one securable to each of the corresponding contact pads. Each member includes a dielectric jacket having an aperture that laterally confines conductive material of a conductive center thereof over the contact pad to which the member is secured. The conductive center of a female member of the conductive structure only partially fills the aperture of the jacket thereof so as to form a receptacle for an end of the male member of the conductive structure. One or both of the male and female members may also be configured to limit the insertion of the male member into the receptacle of the female member. The members of the conductive structure may be preformed structures which are attached to a surface of a semiconductor device or other substrate.

Abstract: A micro device that is manufactured by semiconductor process and is electrically connected to outside for its operation. The micro device includes a circuit board, an electrode pad being provided on the circuit board, a lead substrate being provided substantially parallel to the circuit board, and a lead of conductive member being electrically connected to the electrode pad by being bent in a direction away from a surface of the lead substrate, one end of the lead being adhered to the lead substrate and the other end being a free end.

Abstract: A structure of a package on package and a method for fabricating the same are provided. The structure of the package on package includes a first package, a second package and a plurality of pins. The first package includes a first substrate and a first chip disposed thereon. The second package includes a second substrate and a second chip disposed thereon. The second package is disposed under the first package. The second package includes a plurality of holes. The pins are disposed on the first package and inserted to the holes so as to electrically connect the first package and the second package.

Abstract: A substrate pad in a semiconductor package having a geometry and structure that facilitates providing a solder joint to the pad that has enhanced structural integrity and resistance to mechanical impact. The pad may include a plated metal stud that anchors the solder to the pad interface, providing a more compliant solder joint, even when lead-free solder is used.

Abstract: An integrated circuit (IC) package that comprises a lead frame. The lead frame has a downset portion and leads. The downset portion has an exterior surface that is configured to face away from a mounting board, and an interior surface that is configured to face towards the mounting board. The leads are bent away from the exterior surface, and each of the leads have a first end coupled to an IC and a second end configured to pass through one of a plurality of mounting holes extending through the mounting board. The IC is coupled to the interior surface.

Abstract: An apparatus for coupling an integrated circuit (IC) package to a printed circuit board. The apparatus includes an interposer an interposer having a plurality of connections suitable for surface mounting on corresponding pads of a printed circuit board (PCB). The plurality of connections is arranged in a grid array. The interposer further includes a plurality of plated through holes. The apparatus further includes a substrate having a plurality of pins. The substrate is coupled to the interposer by inserting each of the plurality of pins into a corresponding one of the plurality of plated through holes of the interposer. An IC package including an IC is mounted on the substrate.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: An active device array substrate including a substrate, a pixel array, a plurality of first pads and a plurality of second pads is provided. The substrate has a display area and a peripheral area. Additionally, the pixel array is disposed within the display area. The first pads and the second pads are disposed within the peripheral area, and electrically connected to the pixel array respectively. Moreover, the first pads have a plurality of micro cavities.

Abstract: The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.

Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.

Abstract: An electrically conductive pin comprising a pin stern and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem.

Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Abstract: A semiconductor product is constructed of a wiring substrate in which pads for pin connection are formed, and a substrate with pins in which pins are disposed. The substrate with the pins is formed so that one end of the pin is exposed to one surface of a resin substrate formed by resin molding and the other end of the pin extends from the other surface of the resin substrate and one end of the pin is bonded to a pad of the wiring substrate through a conductive material.

Abstract: Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral movement of the conductor pins while leaving second ends of the conductor pins exposed.

Abstract: A chip-type electronic component includes a substrate, a common potential layer formed on an upper side of the substrate, an insulating film formed on the common potential layer, and provided to expose at least part of the common potential layer. At least one common potential electrode is provided on the exposed part of the common potential layer, and a plurality of conductors provided on the insulating film, each of the conductors forming a part of a thin-film circuit element. At least one columnar electrode is electrically connected to at least one of the conductors, and a sealing film is formed around the columnar electrode.

Abstract: An electrically conductive pin comprising a pin stem and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head defines at least one slot therein, the at least one slot being configured to allow gases to escape therethrough from a region at an underside of the pin head.

Abstract: A substrate with pins comprises pins, and a holding substrate in which through holes to which the pins are attached are formed. Head parts of the pins are arranged in the through holes. The pins are attached by pressing the head parts in the through holes.

Abstract: A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the grid array package, and a second group in another region of the grid array package. Most in the first group of conductive pads are apart at a first pitch, most in the second group of conductive pads are apart at a second pitch which is less than the first pitch. According to the shrinking in the conductive trace on a conductive layer and the shrinking in the through hole, the first pitch and the second pitch are optimized for the maximum conductors and the corresponding conductive pads.

Abstract: A chip includes a plurality of pins; and a plurality of symbols defined on a surface of the chip, wherein the symbols are arranged as a graduated scale corresponding with the pins. It becomes very easy to find a initial pin from among the plurality of pins of the chip.

Abstract: A high-density electrical package utilizing an array of high performance demountable electrical contacts such as UEC, T-Spring, F-Spring and their equivalent contained in a carrier in the form of an interposer between one or more components and a substrate. The carrier is made of a thermally conductive metal or contains thermally conductive metal to provide heat-spreading or dissipation functions in addition to the function of the retention and alignment of the electrical contacts. The above interposer is used for chip attach for a single chip or a stack of chips in the package. The interposer provides electrical connections through individual electrical contact to another chip or to the substrate of the package. It provides also the heat spreading or dissipation function to the chips connected thermally to a particular interposer. The interposer can further be connected thermally to an external heat spreader when necessary.

Abstract: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board.

Abstract: A semiconductor device has an improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.

Abstract: A memory module comprises a base plate and one or more IC embedding seats formed thereon to provide IC memory chip being installed in detachable manner taking the advantage of easy installation, convenient maintenance or replacement of IC memory chip, particularly no longer using SMT, soldering paste, or flux for IC maintenance and replacement; the IC embedding seat comprises a mainbody and a sliding cover formed a cover to the mainbody with sliding movement to open or close the mainbody, and the mainbody has one or more IC mounting compartments has a plurality of conducting pin units arrayed in matrix arrangement to form electric connection with the base plate; during IC maintenance and replacement, the defective IC memory chip shall be freely removed from the memory module without de-soldering to prevent other good IC memory chip from damage due to high temperature.

Abstract: The elevated heat dissipating device of the present invention comprises a thermal substrate connecting onto a heat source and at least one heat conductive pipe connecting to the thermal substrate. The heat conductive pipe further comprises a connecting part connected to a top portion of the thermal substrate, and a bending part which is bended and extended upward away from the thermal substrate. A plurality of sets of heat fins connecting to end portions of the bending part of the heat conductive pipe are supported and elevated by the heat conductive pipe so that an air space is formed between the thermal substrate and the sets of heat fins. A fan locating on a top part of the heat fins, wherein a plurality of air passages are formed in between those heat fins so that cool air ventilates from the fan through the air passages of the heat fins to the thermal substrate.

Abstract: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.

Abstract: An integrated packaging assembly for an MMIC that uses the semiconductor wafers on which circuit elements are fabricated as the package. The packaging assembly includes a plurality of semiconductor layers that have been diced from the semiconductor wafers, where the semiconductor layers can be made of different semiconductor material. The semiconductor layers define cavities therebetween in which circuit components are fabricated. A sealing ring seals the semiconductor layers together so as to hermetically seal the circuit components within the cavities.

Abstract: A semiconductor package includes a metal plate in which one or more openings are formed, the metal plate mounting a semiconductor chip and a printed wire pattern substrate, e.g. a PCB, mounting one or more decoupling capacitors. The semiconductor chip is in direct contact with the metal plate to improve thermal characteristics, and the substrate is supported by the metal plate to increase mechanical stability of the package. The one or more openings in the metal plate accommodate the passing therethrough of plural pins electrically connected via the printed wire pattern substrate to the semiconductor chip. The semiconductor package can be usefully applied to a digital micro-mirror device (DMD) semiconductor package for use in a projection display device.

Abstract: The stack type semiconductor package module includes a lower semiconductor package having a main substrate, a chip mounted on the main substrate and electrically connected to the main substrate through a wire. An epoxy molding compound (EMC) is provided on the main substrate to cover the chip and the wire. Contact holes are formed in the EMC. A sub-substrate having protrusions coated with solder is connected to the lower semiconductor package by inserting the solder coated protrusions into the contact holes. Heat is applied to the protrusions, and the molten solder solidifies inside the contact holes. An upper semiconductor package having substantially identical structure as the lower package is then stacked on the sub-substrate.

Abstract: A compliant contact pin contactor card method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract: Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density.

Abstract: A keypad of a portable wireless terminal includes a sheet having a plurality of holes, a plurality of keys inserted into respective ones of the holes, and a silicon adhesive layer on a lower surface of the sheet to fix the keys to the sheet. A protrusion at a lower surface thereof contacts a dome switch. The keys are firmly mounted at a precise position, and more beautiful design can be realized since a decoration line or a decoration shape can be easily formed to set an appearance of the keys.

Abstract: A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

Abstract: A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor device, allowing the original I/O point location to be relocated to a new point of I/O interconnect that may be in the vicinity of the original point of I/O interconnect but can also be located at a distance from this original point of I/O interconnect. Layers of passivation and polyimide are provided for proper creation and protection of the extended and relocated I/O pads. Wire bonding is used to further interconnect the relocated I/O pads.