Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.

Abstract: A test socket for a semiconductor device is provided having a contact member 30, which lies between the external terminals 25, projected from the package 24 of the IC 22 and the contact pads 26 of the test board 23 for making them in conductive with each other. The contact member 30 is made of a metallic contact member 29, which is in contact with the external terminals 25 through blades 32 and a conductive elastic contactor 28. The conductive elastic contactor 28 has an upper contact part 28a and a lower contact part 28b, which are projected from the top and bottom surfaces of the insulating base 27. The lower contact part 28b is in contact with the contact pads 26 of the test board 23.

Abstract: A method and apparatus for testing unpackaged semiconductor dice having raised contact locations are disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

Abstract: The invention disclosed herein is a semiconductor die assembly and method of making the same having a die and insert substrate that are electrically interconnected by diffusing gold bumps attached to the connecting surface of the substrate to aluminum-based bond pads on the die to form a permanent die-to-insert connection. The process for diffusing the gold bumps into the bond pads preferably occurs during a burn-in process wherein pressure and heat are applied to the die/substrate assembly without melting the gold bumps until a permanent die-to-insert substrate connection is properly made.

Abstract: The invention relates to a device and a method for packaging electronic components (11) having semiconductor chips (5) by means of a mounting frame (1), which is additionally provided with a plastic grid (6) that is disposed on a plastic intermediate substrate (2), which surrounds each semiconductor chip (5) in framelike fashion and which for packaging the plurality of semiconductor chips (5) with a plastic casting composition (7) between semiconductor chips (5) and the plastic grid (6).

Abstract: In a semiconductor device manufacturing method, at least a semiconductor element is arranged in a cavity of a resin molding die. A resin is supplied to a resin reservoir in direct contact with the cavity and is then injected in order to substantially fill the cavity. The resin filled in the cavity forms a resin seal for encapsulating the semiconductor element. The resin seal has a recess or a protrusion as a remainder of the resin reservoir.

Abstract: A high density interconnect land grid array package device combines various electronic packaging techniques in a unique way to create a very thin, electrically and thermally high performance package for single or multiple semiconductor devices. A thin and mechanically stable substrate or packaging material (12) is selected that also has high thermal conductivity. Cavities (14) in the substrate or packaging material (12) accommodate one or more semiconductor devices that are attached directly to the substrate or packaging material. At least one of said semiconductor devices includes at least one optical receiver and/or transmitter. A thin film overlay (18) having multiple layers interconnects the one or more semiconductor devices to an array of pads (20) on a surface of the thin film overlay facing away from the substrate or packaging material.

Abstract: A semiconductor device is manufactured in a method including the steps of: abrasing a surface of a wafer opposite that thereof having a solder ball serving as an external connection electrode; and reinforcing the abrased surface with resin serving as a back-surface reinforcement member. More specifically, the resin is resin of rubber type, silicone type, epoxy type, polyimide type or urethane type. Preferably, previously grinding the surface to be abrased is previously ground to produce the device in a reduced process time. The structure can advantageously prevent a solder connection from breaking as an LSI chip fails to bend in response when the entire package receives force and thus bends.

Abstract: An inspection object imaging device, which images a plurality of objects to be inspected that are located at different imaging distances from imaging means, in which a light transmitting optical member which has a predetermined refractive index and a thickness and which absorbs the differences of the imaging distances is provided in an optical path between the objects to be inspected and the imaging means. When the objects whose optical path lengths from the imaging means are different are imaged by one imaging means, all the objects can be focused simultaneously, so that the time required for the imaging can be reduced and, further, a high quality image can be obtained over the whole imaged region.

Abstract: An encapsulated circuit assembly and a method for making an encapsulated circuit assembly are disclosed. The assembly comprises a first printed circuit board, a second printed circuit board, and a heat transfer device. The second printed circuit board comprises a heatsink, and the heat transfer device couples between a device mounted on the first printed circuit board and the second printed circuit board for transferring heat from the device to the heatsink of the second printed circuit board.

Abstract: There is provided an I/O pin by which an MCM is positively prevented from being damaged by solder flowing from the fore end to the base of the I/O pin when the I/O pin is soldered in the case of mounting the MCM. An I/O pin used for an electrical connection is provided, one end of which is perpendicularly fixed to an MCM and the other end of which is soldered to a predetermined position on the mother board in the case of mounting the MCM on the mother board. In an intermediate portion of the I/O pin, there is formed a solder dam composed of a plated layer of Ni of low solder wettability, a layer of highly heat-resistant resin or a layer of high-temperature solder.

Abstract: A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.

Abstract: A tape carrier is constituted comprising land 12 for solder ball, formed in a predetermined pattern on insulating film 7 having device hole 10 formed in the middle, leads 9 to be connected to a semiconductor chip, plating power-feeding lead 13 having one end connected to lead 9 and formed on insulating film 7, and easily-broken part 19 provided in the middle of the power-feeding leads. A semiconductor device is constituted wherein tape carrier 2 is provided with plating power-feeding lead 13 formed on insulating film 7, one end of which is drawn out of insulating film 7, the other end being connected to leads 9, and plating power-feeding lead 13 is disconnected from the leads when semiconductor chip 1 is installed. Thus, a tape carrier for BGA which is manufactured easily, capable of achieving higher density of wiring in the wiring pattern, improved in water-resistance and reliability, and a semiconductor device using the same are provided.

Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips. A path for high thermal conduction (low thermal resistance) from the IC chip to the heat exchanger to the ambient air is provided by an electronic module cover, configured as a cap with a heat exchanger formed or attached as a single construction, and made of the same material as the substrate, or made with materials of compatible thermal coefficients of expansion to mitigate the effects of vertical displacement during thermal cycling.

Abstract: A printed-wiring substrate including a substrate 101 having pin-bonding portions 111 formed on a main surface 104 thereof and lead pins 121. The lead pins 121 each have a flange 123 and a shaft portion 122 and being brazed to corresponding pin-bonding portions 111 via the corresponding flanges 123. A hemispherical convex shape is imparted to a bonding surface 124 of a flange 123. The flange 123 is used for brazing of a lead pin 121, and the bonding surface 124 faces a pin-bonding portion 111 of a substrate 101. A brazing filler metal 131 used for brazing of the lead pin 121 extends by wetting toward the tip end of the lead pin 121 beyond the outermost edge 127 of an opposite surface 126 of the flange 123, which is opposite the bonding surface 124 of the flange 123, such that an extension-by-wetting end of the brazing filler metal 131 is located between the outermost edge 127 and a shaft portion 122 of the lead pin 121. Since the solder 131 has no narrow portion, the bonding strength is not impaired.

Abstract: A flexible substrate based BGA package mainly comprises a semiconductor chip securely attached onto a flexible film substrate through a nonconductive adhesive. The flexible film substrate is formed from a flexible film having a chip attaching area for carrying the semiconductor chip. The upper surface of the flexible film is provided with a plurality of chip connection pads, a plurality of solder pads, and at least a dummy pad which is disposed centrally on the chip attaching area. The purpose of the dummy pad is to increase the rigidity and strength of the central part of the chip attaching area. The chip connection pads are arranged about the periphery of the chip attaching area for electrically connected to the semiconductor chip. The solder pads are disposed about the dummy pad(s) and electrically connected to the corresponding chip connection pads.

Abstract: The electronic device is provide that includes a body having an underside; a plurality of conducting members for transferring electronic signals; and at least two alignment pins mounted perpendicularly on the underside. Each of the alignment pins has a flexible portion that is more easily bendable than the other portions.

Abstract: The present invention relates to a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, that around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: A semiconductor device for surface-mounting that allows of easy mounting. It comprises a semiconductor element 16, an insulating film 12, a wiring pattern 20 formed on a first surface of the insulating film 12 and connected to the semiconductor element 16, bumps 14 formed on the reverse side of the wiring pattern 20 and projecting through holes 12a formed in the insulating film 12 to the second surface of the insulating film 12, and a support plate 24 being electrically conductive and adhered so as to cover the wiring pattern 20 on the first surface of the insulating film 12 and acting as a planarity maintaining member. The support plate 24 is connected to a constant potential portion of the wiring pattern 20.

Abstract: There is provided a technique of connecting easily the lead terminal to the board of the module. A plurality of clip lead terminals each has at one end thereof clip portions which are connected electrically to connecting terminals by sandwiching an end portion of a board of a module and the connecting terminals formed thereon between clip members of said clip portions and has a lead portion at the other end thereof. The clip lead terminals are arranged so as to be spaced from one another in parallel with one another with the leading edges of the respective clip portions aligned on a straight line. The clip lead terminals are connected to one another through a tie bar and a guide as a connecting portion, respectively, whereby the connecting clip lead terminal 18 is formed as one-body. The lead portions are bent on every other one, leading end portions of the bent lead portions and leading end portions of the non-bent lead portions are in parallel with each other viewing from a side of the board.

Abstract: A packaging substrate is provided such that an electronic components having a plurality of connecting terminals at their side edge portions and other kind of electronic component are mounted in high density on the substrate. More specifically, in a packaging substrate having IC packages (electronic components) surface mounted on the substrate, the package body of each IC package having a plurality of outwardly extending lead terminals at their side edge portions, the package body of the IC package includes at its side edge portion a specified length open region with no connecting terminal disposed therein. The IC packages are arranged in such a way that open regions of adjacent IC packages are positioned so as to confront each other and that front ends of individual leads are kept in closely spaced relation within a specified spacing range, a bypass capacitor (other kind of electronic component) being surface mounted between the open regions of the adjacent IC packages.

Abstract: An organic carrier member for mounting a semiconductor device is provided that has a plurality of pin leads joined to conductive pads on the carrier member by a solder fillet having a reflow temperature higher than the temperature necessary to attach the semiconductor device. Embodiments include a bismaleimide-triazine epoxy laminate carrier member having an array of pins joined to the carrier member by a solder fillet having a reflow temperature of no greater than 275° C.

Abstract: An electronic assembly. The electronic assembly includes a first substrate which has a first set of contact pads and a second substrate which has a second set of contact pads. A plurality of elongate, springable interconnection elements are located between the first substrate and the second substrate. Each of the plurality of elongate, springable interconnect elements is free standing and has a portion permanently attached to a respective contact pad of the first set of contact pads and has a second portion contacting a respective contact pad of the second set of contact pads. The first and the second substrates are brought into a fixed relationship relative to one another.

Abstract: An integrated circuit package which has a staggered bond wire pattern that increases the bond finger width to pad pitch ratio of the package. The package includes a first bond shelf, a second bond shelf and a third bond shelf. Mounted to the package is an integrated circuit which has a plurality of die pads. The die pads are arranged in a pattern of groups, wherein each group has a first die pad that is adjacent to a second die pad, and a third die pad that is adjacent to the second die pad and a first die pad of an adjacent group. Bond wires connect the first die pads to the first bond shelf, the second die pads to the second bond shelf and the third die pads to the third bond shelf, so that each adjacent die pad is connected to a different bond shelf. The staggered bond pattern maximizes the bond finger width of the package.

Abstract: An electronic-circuit assembly according to the present invention comprises a first substrate on the upper surface of which a plurality of electrodes are provided. A second substrate is placed on the first substrate. The second substrate comprises a plurality of through-holes on the positions opposing to the plurality of terminals on the first substrate, respectively. The plurality of terminals on the first substrate are connected to the plurality of through-holes on the second substrate via a plurality of connecting members, respectively. A plate is placed on the upper surface of the second substrate. A plurality of pins which are provided on the under surface of the plate are inserted into the plurality of through-holes on the second substrate, respectively.

Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.

Abstract: A method and apparatus is provided for electrically and mechanically interconnecting electronic circuit assemblies or electronic modules. An integrated circuit (300) includes a plurality of leads (302) extending from a surface (305), each of the leads (302) having a seating portion (403) and a stem portion (402). A printed circuit board (400) includes a plurality of plated through holes (401) therein corresponding to the plurality of leads (302) extending from the integrated circuit (300). The steps of the method include positioning the printed circuit board (400) so that a lower surface (404) of the printed circuit board (400) rests on the seating portion (403) of the leads (302) of the integrated circuit (300), and so that the stem portion (302) of each of the leads are positioned within the corresponding plated through holes (401) in the printed circuit board (400).

Abstract: A semiconductor-chip is bonded to a chip-carrier substrate by way of a gold-to-gold bonding interface. A vacuum chuck is provided to physically hold the semiconductor-chip in physical contact with, the chip-carrier substrate as static force, ultrasonic power, and an elevated temperature are applied to two mating gold surfaces that are formed by two continuous and physically mating gold layers. The bonded assembly is encased in a potting ceramic, or the bonded assembly is encased in a housing that includes a transparent cover that enables use as an optoelectronic semiconductor device.

Abstract: A semiconductor device packaged in a plastic package provided with a semiconductor device chip, a plurality of leads each of which is bonded with each of the bonding pads of the semiconductor device chip, and a plastic mold packaging the semiconductor device chip bonded with the leads, allowing the leads to project themselves from the bottom surface thereof and to extend outward along the bottom surface thereof, wherein each of the leads has a horizontal shape in which the surface of the edge thereof is a half circle, a half ellipse or a half polygon convex toward the inward direction.

Abstract: In an LSI package, terminal resistance elements are formed of resistive paste which, consisting of a mixture of fine powder of either oxidized metal or carbon and fine powder of glass, is buried and sintered in a ceramic wiring board in the direction to penetrate it. Front side wiring, connecting the parts of the terminal resistance elements exposed on the front face of the ceramic wiring board to input/output circuits of the LSI chip to be mounted on the front face of the ceramic wiring board, is formed on the front face of the ceramic wiring board and in the top layer of the ceramic wiring board. Back side wiring, connecting the parts of the terminal resistance elements exposed on the back face of the ceramic wiring board to a voltage clamp wiring network, is formed on the back face of the ceramic wiring board.

Abstract: A semiconductor device comprising a plurality of bump electrodes wherein signal pins requiring electrical connection are assigned in sequence from the bump electrodes at the outermost periphery near the edge of the semiconductor device to the bump electrodes in an interior area of the semiconductor device, and no-connection pins requiring no electrical connection are assigned to the remaining bump electrodes, is provided. Circuit board cost is thus reduced, and the ease of mounting the semiconductor device to the circuit board is improved.

Abstract: A method and apparatus are provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided are a method and apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided are a method and apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided are a method and apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Abstract: A semiconductor device includes a semiconductor pellet (1), and a package having a pellet mount portion (21) on which a semiconductor pellet (1) is mounted. The semiconductor pellet (1) is mounted on the pellet mount portion (21) of the package through a joint material (6). The area of the surface of the pellet mount portion (21) on which the semiconductor pellet (1) is mounted is set to be smaller than the area of the surface of the semiconductor pellet (1) which is mounted on the pellet mount portion (21), thereby preventing the climb-up of the joint material (6) along the side surface of the semiconductor pellet (1).

Abstract: A electronic apparatus and a process for its manufacture are disclosed. The apparatus includes a planar card for accommodating an electronics module package having protruding solder columns and solder joints to mechanically mount and electrically connect the solder columns of the module to the planar card. The planar card includes a first side and a second side, a plurality of wiring lines forming a wiring pattern, and a plurality of vias extending at least partially through the card. Each of the vias includes at least one recessed area extending from one or both sides of the card. The recessed areas extending to a depth within the planar card sufficient to wick the solder joints, and the each of the recessed areas are shaped to provide surface tension to mechanically retain the solder joints.

Abstract: The present invention relates to a ball grid array (BGA) semiconductor package member and its manufacturing method employing a carrier frame and a substrate, and to a method of manufacturing a BGA semiconductor package using the BGA semiconductor package member. In manufacturing the conventional BGA semiconductor package, conventional package manufacturing equipment cannot be employed because a boat is used during processing which requires additional equipment, and thus increases the costs of production. However, a BGA semiconductor package manufacturing method employing a carrier frame and substrate according to the present invention is compatible with conventional semiconductor package manufacturing equipment.

Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate, a stiffener, a heat spreader, and an optional heat sink. The chip includes multiple I/O pads arranged upon an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The stiffener, a rigid member able to retain its shape during C4 heating, may be attached to the upper surface of the substrate prior to the C4 process, helping the substrate maintain its planarity during and after the C4 process. The stiffener has an opening dimensioned to receive the chip and exposing the first set of bonding pads. Following the C4 process, a first space between the underside surface of the chip and the upper surface of the substrate is filled with an underfill material.

Abstract: A structure for mounting a device on a circuit board, comprising two relay substrates provided parallel to each other between the circuit board and the device, one of the relay substrates being constituted by a relay socket substrate with an array of socket pins being inserted into and supported by the relay socket substrate, each of the socket pins being soldered to a corresponding one of solder pads in the circuit board, the other relay substrate being constituted by a relay pin substrate with an array of relay pins, for connection to the device, being inserted into and supported by the relay pin substrate, each of the relay pins being soldered to a corresponding one of solder balls provided in the device, the relay pins, in the relay pin substrate, each in its one end opposite to the soldered end being detachably fitted in the socket pins each in its one end on the socket side. This construction enables repair and replacement of the device and the evaluation and tests of the performance of the device.

Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts. A semiconductor die carrier may also include an insulative substrate; a plurality of leads each having an external portion extending out of the semiconductor die.

Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are formed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.

Abstract: Terminal pins with two lateral portions and a bridge-shaped elevated middle portion are provided. The terminal pin and perpendicularly rising hybrid circuit typically together have an inverted T shape. On the one hand, the hybrid circuit stands on its own on the substrate without further means of assistance and can be soldered. On the other hand, the bridge-shaped construction effects a sufficient elasticity and carrying capacity relative to swivellings, or respectively, accelerations, as well as effecting the presence of two defined support surfaces whose co-planarity is guaranteed by the springing configuration of the terminal pins.

Abstract: A method for fabricating a printed-circuit board includes the steps of loading components onto the printed circuit board, and placing a pin array over the components. Each pin is free to move "downward," and each component has at least one pin pressing on it to hold the component in place. Each component also preferably has a pin on each side of it, to hold it against lateral movement. The pin support arrangement is dimensioned so that a gap or space exists between the support and the component side of the board. Heat is applied to the gap, and flows through the interstices between the pins to heat the solder on the upper side of the board to fuse the solder and make the desired connections.

Abstract: Disclosed is a packaged integrated circuit device with high heat dissipation performance and low weight. The packaged integrated circuit device includes an interconnection substrate having at least one layer of conductive trace material and at least one layer of insulating material and also having a first surface and a second surface disposed opposite to the first surface and having a plurality of electrical contacts formed on the second surface. At least one metal thermal conductive layer having a first surface is attached on the first surface of the interconnection substrate and having a second surface exposed to an exterior. A through hole region is formed in the interconnection substrate and the thermal conductive layer. An integrated circuit chip having a first surface exposed to an exterior and having also a second surface with a plurality of bond pads, opposite to the first surface of the integrated circuit chip, is placed within the through hole region.

Abstract: A chip carrier for carrying a chip is disclosed.

Abstract: A ball grid array package provides conductive paths between terminals and a semiconductor chip through via-hole plugs formed in a circuit board, and the via-hole plugs are covered with a rigid plate before sealing the semiconductor chip in synthetic resin so as to prevent the via-hole plugs from penetration of the synthetic resin.

Abstract: The present invention relates to semiconductor devices packaged using overcasting. The overcast devices of the present invention incorporate encapsulative materials, such as ultraviolet-curing material, which are cast in open stencils at approximately ambient pressure (and potentially at approximately ambient temperature) over electronic components mechanically and electrically connected to the substrate. The overcast semiconductor devices of the present invention may incorporate new encapsulative materials, including UV-cured materials and longer shelf life materials, poorly suited for the pressures and temperatures of injection molding. The overcast devices also allow the incorporation of substrate materials which are not feasible for use with a higher pressure, higher temperature forming process.

Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are butted together to save space. The bonding pads for the lower IC chip or chips are placed along the edges not butted with one another. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be placed at the top of the IC chips away from the ball grid array.

Abstract: A high performance IC package provides high density electrical interconnection and packaging for a high speed and high bandwidth IC chip and is easily connected to or disconnected from a printed circuit board. The IC package includes an enclosure; an integrated circuit chip having a front face and a back face wherein the back face is attached to an inner ceiling of the enclosure; contacts formed on die pads on the front face through a photolithography process where each of the contacts has a base portion vertically formed on the die pad, a horizontal portion whose one end is formed on the base portion, and a contact portion vertically formed on another end of the horizontal portion; and an encapsulant provided on the front face of the integrated circuit chip for air tightly sealing. The contacts are projected through the encapsulant, and the horizontal portion of each of the contacts produces a contact force when the contact is pressed against a contact target.

Abstract: A heat sink is constructed in accordance with this invention to increase the spacing surrounding radiating pins which extend outward from a base at the region of highest thermal stress, and to increase the mass of the radiating pins a distance from said region of highest thermal stress to enhance the effects of a thermal differential.

Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device comprises a semiconductor chip having a plurality of pads, a resin portion sealing said semiconductor chip and a terminal portion in which a prescribed number of pole terminals electrically connected to said pads provided in said semiconductor chip are provided, said pole terminals being exposed from said resin portion. According to the invention, a cost for production is reduced and a reliability and electrical characteristics can be improved.

Abstract: Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.