Abstract: A flip chip type semiconductor device is provided with a semiconductor chip with a plurality of pad electrodes on one surface. A solder electrode is connected to each pad electrode and a metallic post is connected to each solder electrode. The surface of the semiconductor chip on a side on which the pad electrodes are provided is coated with an insulating resin layer and whole the pad electrode and solder electrode and part of the metallic post are buried in the insulating resin layer. The remaining portion of the metallic post is projected from the insulating resin layer to form a protrusion. Then, an outer solder electrode is formed so as to cover this protrusion. The outer solder electrodes are arranged in a matrix on the insulating resin layer. The height of the protrusion is made 7 to 50% of the distance between an end of the outer solder electrode and the surface of the insulating resin layer.

Abstract: A pin grid array package comprises a number of signal pins and ground pins. At least one of the signal pins is a controlled impedance signal pin, i.e. a signal pin whose impedance is adjusted and/or reduced according to the present invention. The pin grid array package also includes a number of ground planes and signal planes. A controlled impedance signal pin is coupled to one of the signal planes by means of a signal via. A number of ground pins surround the controlled impedance signal pin. By varying the arrangement, number, and separation distance between the ground pins and the controlled impedance signal pin, the impedance of the signal pin is adjusted and/or reduced. Depending on the particular circuit or logic function assigned to a signal pin and its adjacent signal pin, a different degree of impedance control and/or reduction can be achieved by the present invention.

Abstract: A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), preferably an electromagnet, is disposed at the other one of the opposing surfaces. Solderable magnetic pins (7) are caused to enter the holes by magnetic attraction by positioning the one surface of the mask over the pins with a portion of each of the pins extending out of the hole into which it has entered. A layer of solder (11) is formed on the portion of each of the pins extending out of a hole in the mask and this layer of solder is reflowed over the pins and over a grid of solder adherable elements (13) on the package (15) and then allowed to set. The mask is removed from the pins when the solder is again set.

Abstract: A chip carrier, a semiconductor package and a fabricating method thereof are proposed, in which on one side of the chip carrier finally removed from an engaged surface of a mold in a de-molding process there is formed at least one grounding means corresponding in position to an eject pin of the mold, so as to allow a gear amount of electrical static generated on a surface of the semiconductor package during molding and de-molding to be discharged to the outside, instead of being retained on a semiconductor chip, conductive elements and conductive traces of the semiconductor package. This therefore can prevent electrical leakage and damage to the semiconductor chip from occurrence, and improve the quality and production efficiency for the semiconductor package.

Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.

Abstract: The invention relates to a device and a method for packaging electronic components (11) having semiconductor chips (5) by means of a mounting frame (1), which is additionally provided with a plastic grid (6) that is disposed on a plastic intermediate substrate (2), which surrounds each semiconductor chip (5) in framelike fashion and which for packaging the plurality of semiconductor chips (5) with a plastic casting composition (7) between semiconductor chips (5) and the plastic grid (6).

Abstract: In a package board for a ball grid array package, bypassing wiring is provided for connecting external electrodes (pins) with each other. A ball grid array package is obtained by mounting an electric element on such a package board. Further, such ball grid array package is mounted on a common mounting board together with other electric element or elements. The other electric elements on the mounting board may be connected through the internal wiring in the package board. The wiring density of the mounting board for mounting a multiple-pin ball grid array package (BGA) or other electric elements can be reduced without increasing the number of layers in the entire body of the mounting board.

Abstract: A packaging substrate is formed with electrically non-functional areas of Cu on the upper surface and/or lower surface for improved strength and rigidity and reduced warpage and bending. Embodiments of the present invention include substrates containing electrically non-functional grid-like Cu areas on the upper and lower surface such that the ratio of the total Cu area on one surface is about 55% to about 100% of the total Cu area on the other surface.

Abstract: A electronic assembly is disclosed and claimed. The electronic assembly includes a first substrate and a second substrate. A plurality of power connections are coupled between the first substrate and the second substrate and a multiplicity of signal connections separate from the plurality of power connections are also coupled between the first substrate and the second substrate. Each of the plurality of power connections have a substantially different size and shape compared to each of the multiplicity of signal connections.

Abstract: In a semiconductor device manufacturing method, at least a semiconductor element is arranged in a cavity of a resin molding die. A resin is supplied to a resin reservoir in direct contact with the cavity and is then injected in order to substantially fill the cavity. The resin filled in the cavity forms a resin seal for encapsulating the semiconductor element. The resin seal has a recess or a protrusion as a remainder of the resin reservoir.

Abstract: The present invention is characterized by replacing solder balls with cylindrical terminals in an IC package where at least a chip is located on the same side of the substrate of the IC package as the solder balls are. Due to the larger length of the cylindrical terminals which are located on the same side of the substrate of the IC package as at least a chip is, at least a chip with relatively thick size can be accommodated in the IC package provided by the present invention, without need of increasing terminal pitch (such as the ball pitch in a conventional BGA package).

Abstract: In an integrated circuit carrier having a large number of power pins allocated to an internal power plane, the current flowing through the power pins may divide very unevenly, and result in current flow through some of the power pins which exceeds the maximum specification for either the package pin or for the socket into which the package may be inserted. In such a package, the magnitude of the current flowing through the highest current power pin may be reduced by configuring the resistance of the power plane(s) and vias to provide approximately the same total resistance to every power pin location. Slots may be cut in a package power plane to alter the current path and raise the impedance of the conduction path between some of the package power pins and the internal contact pads otherwise having the lowest impedance.

Abstract: A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.

Abstract: A connector for providing power from a first circuit board to a second circuit board. The apparatus comprises a first conductive member, including a first conductive member first end and a first conductive member second end distal from the first end; a second conductive member disposed within the first conductive member, the second conductive member including a second conductor member first end and a second conductor member second end distal from the second conductor member first end; and one or more first circuit board permanent attachment features for electrical coupling with the first circuit board and second circuit board, and one or more disconnectable conduction features for electrically coupling the connector with the second circuit board.

Abstract: An Integrated Circuit (IC) package is disclosed comprising an IC chip with a microcontroller therein having an n-bit data bus, and up to n pins electrically coupled to the microcontroller. The IC package also includes a control register coupled to the microcontroller for receiving enable and disable signals from the microcontroller. One or more of the pins have one or more functional block associated thereto. Each functional block defines a specified function for its corresponding pin. Thus, each pin having a plurality of corresponding functional blocks has a number of potential functions equal to the number of corresponding functional blocks. The specific function for a given pin is selected by the enable signal from the control register which selects the appropriate functional block appropriate command from the microcontroller. By using pins with multiple functions, the instant invention permits an n-bit architecture microcontroller to use less than or equal to n pins.

Abstract: The present invention relates to a backup module for a standard memory chip, more especially a standard memory chip (for example, DIP, QFJ and PLCC packages) having high-density pins for the backup of a personal computer. If the standard memory chip is out of order, the backup module according to the present invention can take the place of the standard memory chip. By switching between two or more chips, the capacity of the memory can be effectively increased as a whole and the content (program or data) of the memory can be easily optimized.

Abstract: An integrated circuit package such as a BGA package for use with an integrated circuit chip. The integrated circuit package has substrate with a cavity that exposes a lower conductive level in the package so that connections between the integrated circuit chip and the lower conductive level may be formed to reduce the through holes formed in the substrate. As a result, additional signal line interconnections may be included in the substrate circuit package and/or the size of the integrated circuit chip may be decreased. Each of these may be implemented for enhanced electrical performance. The multiple wire bonding tiers in the substrate may also provide greater wire separation that eases wire bonding and subsequent encapsulation processes.

Abstract: A semiconductor device has a circuit board, a main chip mounted on a first surface of the circuit board, a subchip mounted on a second surface of the circuit board, interface circuits distributed in the main chip along four sides of the main chip, respectively, to interface the main chip and the subchip with each other, subchip connecting terminals for connecting the interface circuits and the subchip to each other through the circuit board, main-chip connecting terminals for connecting the main chip and the outside to each other, subchip bonding terminals connected to the subchip, a first wiring area for connecting the subchip bonding terminals and the subchip connecting terminals to each other, package terminals for connecting the main chip and the outside to each other, and a second wiring area for connecting the package terminals and the main-chip connecting terminals to each other.

Abstract: A semiconductor integrated circuit according to the present invention comprises a memory array, an input circuit for writing data in the memory array and reading data from the memory array, an output circuit and a package, including 100 pins, storing the memory array, the input circuit and the output circuit. A fourth pin, an eleventh pin, a twentieth pin, a twenty-seventh pin, a fifty-fourth pin, a sixty-first pin, a seventieth pin and a seventy-seventh pin are supplied with the same voltage. The input circuit and the output circuit receive a power supply voltage from different ones of these pins. Thus, a semiconductor integrated circuit resistant against noise and capable of responding to a high operating frequency is provided.

Abstract: The present invention relates to chip assembly with a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, than around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: A substrate for use in packaging of a semiconductor chip is disclosed. The upper surface of the substrate comprises a die covering area adapted for receiving the chip, a ground ring and a power ring. The lower surface of the substrate comprises a plurality of first contact pads right under the vicinity of the ground ring and the power ring, and a plurality of second contact pads surrounding the first contact pads. It is noted that the first contact pads are divided into a two groups electrically connected to the ground ring and the power ring, respectively. Preferably, the lower surface of the substrate is further provided with a plurality of dummy pads at a position right under the periphery of the die covering area and a plurality of third contact pads located right under the die covering area.

Abstract: A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping old or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

Abstract: An apparatus and a method for providing a fully protective package for a flip chip with a protective shield plate and an underfill encapsulant material. The apparatus comprises a semiconductor chip electrically connected by flip chip attachment to a substrate. A shield plate is placed in contact with a back surface of the semiconductor chip. An underfill encapsulant is disposed between the semiconductor chip and the shield plate, and the substrate. A glob top encapsulant may be applied about the periphery of the upper surface of the shield plate that extends to the substrate for additional protection and/or adherence.

Abstract: Disclosed is a substrate used in performing a burn-in test of the integrated circuit chip prior to packaging the chip and a method for manufacturing a known good die using the same. The substrate includes a body having a plurality of through holes; a plurality of metal lines formed on one surface of the body and electrically connected to a plurality of bonding pads of the integrated circuit chip; and a plurality of pins each inserted into the respective corresponding holes and electrically connected to the respective corresponding metal lines and also projected from a surface opposite to the surface on which the metal lines of the substrate are formed. Moreover, the method of manufacturing a known good die includes performing a burn-in test in a state in which the integrated circuit chip is adhered to the substrate such that the bonding pads of integrated circuit chip are electrically connected to the metal lines of the substrate.

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract: The present invention relates to a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, that around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.

Abstract: A semiconductor package with a heat dissipating element is proposed, in which the contact area between a semiconductor chip and the heat dissipating element is significantly reduced as the chip merely has its edge portion attached to the dissipating element. This makes an effect of a thermal stress on the chip reduced so as to prevent cracking and delamination for the chip. Moreover, the chip is partially exposed to the atmosphere, which allows the efficiency of heat dissipation and moisture escapement to be improved, so as to prevent a popcorn effect from occurrence and make the semiconductor package assured in reliability and quality.

Abstract: A semiconductor package including a universal substrate with interior pads, peripheral pads, and substrate traces positioned between the interior pads and the peripheral pads. The interior pads are configured for electrical interface with a first semiconductor chip. The peripheral pads are configured for electrical interface with a second semiconductor chip that is larger than the first semiconductor chip. By providing a universal substrate that can accommodate multiple die sizes, package design time and costs can thus be reduced.

Abstract: A semiconductor device includes a semiconductor chip and a printed circuit board. Metal electrodes of the semiconductor chip and the internal connection terminals of the printed circuit board are electrically connected through the metallic joining via precious metal bumps. A melting point of a metal material constituting each of the metallic joining parts is equal to or higher than 275 degrees, and a space defined between the chip and the board is filled with resin (under fill) containing 50 vol % or more inorganic fillers.

Abstract: In a differential low-noise amplifier built in a semiconductor integrated circuit for a dual-band wireless transceiver, impedance components of wire bonding and package that occur in emitters are reduced and a gain is improved. Ground pins of amplifiers of the differential amplifier forming a pair are arranged adjacent to each other. Input pins and ground pins of the same amplifier are arranged adjacent to each other. Signals of the adjacent pins are allowed to have inverse phases, and trans-coupling between the pins is utilized so as to reduce impedance of the transistor emitters.

Abstract: A multiple line grid array package comprising a package body having a first surface and a second surface opposite to the first surface; a first pattern formed on the first surface of the package body and including a number of input/output nodes; a second pattern formed on the second surface of the package body; and a multiple line grid having a nonconductive grid body and a number of conductors formed parallel to a longitudinal axis of the nonconductive grid body on the outer peripheral portion and/or within an inner portion of the multiple line grid and bonded to the package body; wherein each of the conductors is electrically isolated from each other and matches the corresponding one of the number of input/output nodes of the first pattern. A number of such multiple line grids are arranged in a grid pattern to form the multiple line grid array.

Abstract: When a semiconductor integrated circuit having a plurality of electrode pads disposed in an array-like form on the bottom surface thereof is mounted on a printed wiring substrate, a plurality of ground electrode pads and a plurality of power supply electrode pads are concentratedly arranged on the central portion of the semiconductor integrated circuit mounted on the printed wiring substrate so as to constitute groups so as to be opposed to each other, and a decoupling capacitor is mounted on the opposite surface of the printed wiring substrate through a through-hole, whereby the creation of radiation noise is suppressed and the higher density of the printed wiring substrate is achieved.

Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.

Abstract: The present invention compactly fabricates integrated circuits of an electronic system on a semiconductor wafer by fabricating the integrated circuits of the electronic system on both sides of a semiconductor wafer. A first face of an area of the semiconductor wafer is processed with an integrated circuit fabrication process step to fabricate part of a first integrated circuit thereon. In addition, a second face of the area of the semiconductor wafer is processed with the integrated circuit fabrication process step to fabricate part of a second integrated circuit thereon. The first face and the second face are processed for a plurality of integrated circuit fabrication process steps until the first integrated circuit is completely fabricated on the first face and the second integrated circuit is completely fabricated on the second face.

Abstract: A premold type semiconductor package includes a plurality of leads arranged side by side and having upper and lower common surfaces, a mold resin integrally molded with the leads for securing them from the upper and lower surfaces thereof. The mold resin defines a chip mounting recess at an upper side on the first surfaces of the leads, so that a semiconductor chip is to be mounted in the recess. The upper surfaces of the leads are partially exposed in the recess so as to define internal connecting terminals to which the semiconductor chip is to be electrically connected. The mold resin is provided with a plurality of holes by which the lower surfaces of the leads are partially exposed to define external connecting terminals.

Abstract: A semiconductor device which ensures high packaging reliability and maintains high power/ground plane characteristics and can be embodied inexpensively even when the device has a large number of terminals, as well as to provide a method of manufacturing the semiconductor device. Since the reliability of mounting of the solder balls 9 can be improved even when the system board 16 is of great size, there can be embodied a BGA-type semiconductor device having terminals in the number of 700 to 1000 pins or more, thus eliminating a necessity for mounting sockets, which would be required in the case of a PGA-type semiconductor device and contributing to a decrease in costs. Further, even when the number of terminal pins is increased further, since the signal terminals can be arranged in a full-matrix pattern with a high degree of freedom, the semiconductor chip 2 can be made compact.

Abstract: A printed-wiring substrate including a substrate 101 having pin-bonding portions 111 formed on a main surface 104 thereof and lead pins 121. The lead pins 121 each have a flange 123 and a shaft portion 122 and being brazed to corresponding pin-bonding portions 111 via the corresponding flanges 123. A hemispherical convex shape is imparted to a bonding surface 124 of a flange 123. The flange 123 is used for brazing of a lead pin 121, and the bonding surface 124 faces a pin-bonding portion 111 of a substrate 101. A brazing filler metal 131 used for brazing of the lead pin 121 extends by wetting toward the tip end of the lead pin 121 beyond the outermost edge 127 of an opposite surface 126 of the flange 123, which is opposite the bonding surface 124 of the flange 123, such that an extension-by-wetting end of the brazing filler metal 131 is located between the outermost edge 127 and a shaft portion 122 of the lead pin 121. Since the solder 131 has no narrow portion, the bonding strength is not impaired.

Abstract: The present invention provides a small adapter apparatus useable for high density integrated circuit packages, e.g., ball grid array packages. The adapter apparatus includes an adapter body member having a length along an adapter axis between a first adapter end and a second adapter end of the adapter body member. An array of contact elements, e.g., solder spheres, are disposed on the first adapter end of the adapter body member. Further, the adapter apparatus includes an array of elongated pin elements. Each elongated pin element corresponds to one of the array of contact elements and extends parallel to the adapter axis from a corresponding contact element through the adapter body member and the second adapter end thereof. One or more of the elongated pin elements of the array is of a different length than one or more other elongated pin elements. Various socket devices for receiving and retaining the elongated pins are also provided.

Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.

Abstract: Several electronic parts are mounted on several ceramic substrates in a semiconductor device, and are wire bonded to the respective ceramic substrates through bonding wires. The electronic parts and the bonding wires are covered with an enclosing member on every ceramic substrate, and an inside of the enclosing member is filled with silicone gel for sealing. The ceramic substrates are bonded to a radiation fin together, and are mounted on a motherboard perpendicularly to the motherboard.

Abstract: A substrate for use in a semiconductor package is fabricated by preparing a composite metal laminate consisting of a first metal layer, a second metal layer, and a carrier layer positioned in this order. The first metal layer has etching characteristics different to those of the second metal layer with respect to the same etchant. The first metal layer is selectively etched until the second metal layer is exposed, thereby forming pillar-like interconnections. The gap between the interconnections is then filled with a resin so as to form a resin base with interconnections. The carrier layer is removed from the second metal layer, and the second metal layer is selectively etched until the first metal layer or the resin base is exposed, thereby forming a conductive pattern on the resin base.

Abstract: A multiple line grid array package comprising a package body having a first surface and a second surface opposite to the first surface; a first pattern formed on the first surface of the package body and including a number of input/output nodes; a second pattern formed on the second surface of the package body; and a lead frame having a nonconductive grid body and a number of conductors formed parallel to a longitudinal axis of the nonconductive grid body on the outer peripheral portion and/or within the inner portion of the lead frame and bonded to the package body; wherein each of conductors is electrically isolated from each other and matches the corresponding one of the number of input/output nodes of the first pattern.

Abstract: A multi-layered pin grid array interposer used in a test socket for testing and converting a package having a non-pin grid array footprint to a pin grid array footprint. The multi-layered pin grid array interposer test socket includes a multi-layered pin grid array interposer, a semiconductor device mounted on a package having a non-grid array footprint and a fastener. The multi-layered pin grid array interposer includes a top signal layer having bonding pads on an upper surface, a bottom signal layer having a pin grid array footprint on a bottom surface, at least one power layer between ground layers, the ground layers being between the top signal layer and bottom signal layer, and a links for connecting the plurality of bonding pads to the pins of the pin grid array footprint. The fastener presses the package against the multi-layered pin grid array interposer connecting the leads of the package with the bonding pads.

Abstract: An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD processing: a thin film of silicon dioxide, a layer of silicon nitride, oxy-nitride or silicon carbide, and a very thin topmost layer of silicon oxide.

Abstract: A novel approach to detection of leakage site detection for BGA chips. The invention prevents damaging the semiconductor circuit that is a problem during conventional preparation for backside leakage detection for BGA chips. The invention teaches removing the backside from the BGA device and separating the BGA device into two parts. The back surface of the molded part within which the BGA chip is embedded remains undamaged within the scope of the present invention and can be electrically accessed to perform BGA die analysis.

Abstract: When a semiconductor integrated circuit having a plurality of electrode pads disposed in an array-like form on the bottom surface thereof is mounted on a printed wiring substrate, a plurality of ground electrode pads and a plurality of power supply electrode pads are concentratedly arranged on the central portion of the semiconductor integrated circuit mounted on the printed wiring substrate so as to constitute groups so as to be opposed to each other, and a decoupling capacitor is mounted on the opposite surface of the printed wiring substrate through a through-hole, whereby the creation of radiation noise is suppressed and the higher density of the printed wiring substrate is achieved.

Abstract: A semiconductor package including a semiconductor chip having bonding pads respectively arranged in a line adjacent to four sides of the upper surface; gold bumps formed on each bonding pad; a glass substrate which is made by forming metal patterns, the metal pattern including an inner pattern electrically connected to the bonding pad of the semiconductor chip through the gold bumps, an outer pattern, and a connecting pattern between the inner pattern and the outer pattern: a Dam having a frame-shape on the connecting pattern and surrounding the inner patterns; sealing material sealing the space between the glass substrate around the semiconductor chip and solder balls attached on the outer patterns of each metal pattern.

Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash.

Abstract: There is provided a semiconductor device including (a) a semiconductor chip, (b) a wiring making electrical connection with the semiconductor chip and containing copper (Cu) therein, (c) a solder ball making contact with the wiring and containing tin (Sn) therein, and (d) a layer made of copper-tin (Cu—Sn) alloy, sandwiched between the wiring and the solder ball, and having a thickness equal to or greater than about 1.87 micrometers. The copper-tin alloy layer strengthens connection between the wiring and the solder ball, and hence, ensures reduction in occurrence of breakage and/or cracking in the wiring and the solder ball. As a result, it would be possible to avoid the solder ball from being separated from the wiring due to the breakage and cracking. Accordingly, a fabrication yield of the semiconductor device can be enhanced.