Abstract: A semiconductor package includes a semiconductor chip connected to lead frames by wires and outer leads protruding from the semiconductor package. At this time, the outer leads are connected to the lead frames and grooves into which the outer leads are inserted into are provided in the semiconductor package, wherein the grooves are connected the lead frames. In mounting a first and a second semiconductor package, the outer leads of the first semiconductor package are inserted into the grooves of the second semiconductor pacakage.

Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.

Abstract: An electro-optical device preferably includes a printed circuit board (PCB) having a cutout region or a rigid region. A leadframe having an electro-optical semiconductor device arranged thereon can be arranged in proximity to the cutout region of the PCB. Alternatively, the electro-optical device can be arranged on the rigid region of the PCB. A lens is preferably arranged over the electro-optical semiconductor device. A connector array can also be arranged on the PCB to communicate electrical signals with an external device. An interface circuit, such as a driver circuit or an amplifier circuit, can also be arranged in close proximity to the electro-optical semiconductor devices on the leadframe or the PCB.

Abstract: A press-fit integrated chip package is provided comprising a laminate base structure having plated through holes for introducing press-fit elements, and a laminate cover structure providing very fine conducting paths and having a top mounting plane for mounting chips.

Abstract: An electronic module that includes a plurality of electrically conductive leads, an electrically conductive base plate, a first integrated circuit (IC) die, at least one material block and an electrically non-conductive overmold. The at least one material block functions to more closely match coefficient of thermal expansion (CTE) differences between components of the electronic module.

Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.

Abstract: FileNameFileName-33-Integrated circuit packages including interconnection posts with multiple metal terminals are disclosed. An exemplary package includes a molded plastic body with integral plastic posts extending from the body. Each post is coated with a plurality of electrically separate metal terminals. The metal terminals extend from a surface of the body, along a sidewall of a respective post, to an end of the post. An integrated circuit is mounted on the body. Conductive paths, which may include vias through the body, electrically couple different bond pads of the integrated circuit to the metal terminals of the posts. In some embodiments, posts on opposing sides of the plastic body enable stacking, and electrical coupling, of two or more packages. The metal terminals of posts of the lower package may be engaged with the metal terminals of corresponding posts on a mounting substrate.

Abstract: Apparatus and method for assembling a semiconductor device on a wiring substrate is disclosed, wherein Pb (lead) is not used and the chance of generation of defects is reduced. Semiconductor package (100) has solder balls (114) containing Sn (tin), Ag (silver) and Cu (copper). Wiring substrate 200 has connecting terminals 208 for connecting solder balls (114). The connecting terminals (208) have an Au (gold) layer (212) and a Ni layer (210). In the operation for assembling semiconductor package (100) onto wiring substrate (200), because solder balls (114) are heated and fixed on connecting terminals (208), Au in Au layer (212) diffuses into balls (114). Because Au is contained in solder balls (114), a high bonding strength is obtained, and the chance of generation of defects is reduced.

Abstract: An area area package includes a plurality of solder balls not used as electrical connectors. These non-connected solder balls, or “dummy balls,” provide protection to solder balls connected to live pins and therefore increase reliability of the area array package. The dummy balls may be placed in the corners, along the diagonals or in other high stress location on the area array package. To further increase reliability, a continuous copper ball land pad may be used to connect each group of corner dummy balls. Continuous copper pads help to reduce stress on the dummy balls. For center-depopulated BGA packages, an array of dummy balls may be used in the center of the package to prevent substrate bending and improve drop test reliability.

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

Abstract: A system for providing electrical contacts between a die and an electrical device includes a package having a first major surface, a second major surface, a first scalloped edge, a second scalloped edge, and a solid end adapted for insertion into a slot. The solid end for carries power to the die or input/output signals. The scalloped edges also carry power. The package includes a plurality of electrical pins which carry input/output signals as well as power. The socket of the system includes a base having an opening therein adapted to receive the package. A cover with openings for receiving the pins covers the base. A power contact unit includes a pair of scalloped edges and a slot. The power contact unit and the cover moves with respect to the base of the socket.

Abstract: Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed.

Abstract: An integrated circuit package is provided with alignment pads which are solid or annular ring shaped. Alignment members such as balls or bullets are attached to the alignment pads via a wetting media. When heated, the wetting media serves to center and seat the alignment members on the alignment pads. When cooled, the wetting media serves to bond the alignment members to the alignment pads.

Abstract: A plug-in type electronic control unit is comprised of a wiring board, a plurality of electronic parts mounted on one surface of the wiring board by utilizing a wireless bonding process, and a plug member mounted on the other surface of the wiring board by utilizing a wireless bonding process. It is possible to suppress the planar extent of the unit by such a laminated structure, and to suppress the extent of the unit in a laminating direction by the employment of the wireless bonding process. Thus, it is possible to achieve a reduction in size of the plug-in type electronic control unit.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus comprises an integrated circuit (IC) having a plurality of connection pins, a carrier socket configured to carry the IC. The carrier socket protects the pins of the IC from bending. In addition, the carrier socket straightens pins that have been bent prior to placing the IC into the carrier socket.

Abstract: A package stacked semiconductor device includes a plurality of pin linking means for electrically connecting at least one of control signal pins of one package to its neighbor NC pin of the same package. Either of the control signal pin or the neighbor NC pin, which are electrically interconnected, is electrically connected to the corresponding pin of the next package.

Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.

Abstract: A mobile telephone device fitted with a transmitter and a receiver each having a high-frequency component with an integrated decoupling capacitor. The high-frequency component includes a substrate with the decoupling capacitor on one surface thereof, first and second current supply terminals for the capacitor on the same surface of the substrate as the capacitor, one capacitor electrode connected to a high frequency circuit and a DC voltage source, also on the one surface of the substrate, and the other capacitor electrode connected to ground.

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: A low-cost header for connecting an electronic components board to a circuit board is disclosed, consisting of side walls made of an unwarpable plastic material and joined together to form a frame around an area substantially the same as the area of the components board. A plurality of metal pins are located in the frame, each having one end extending from said frame such that these ends can be soldered to the components board concurrently with the solder attachment of the components to the board. The other ends of the pins can be formed so that they are adjusted for either through-hole attachment to circuit boards, or for surface mounting.

Abstract: In a package board for a ball grid array package, bypassing wiring is provided for connecting external electrodes (pins) with each other. A ball grid array package is obtained by mounting an electric element on such a package board. Further, such ball grid array package is mounted on a common mounting board together with other electric element or elements. The other electric elements on the mounting board may be connected through the internal wiring in the package board. The wiring density of the mounting board for mounting a multiple-pin ball grid array package (BGA) or other electric elements can be reduced without increasing the number of layers in the entire body of the mounting board.

Abstract: A semiconductor chip package with direction-flexible mountability comprising a switching circuit for switching a pin function according to the mounting direction of a package, a pair of pin-definition pins for defining the pin function and a pair of power supply leads, and a pair of ground leads. One of the power supply lead pair and the ground lead pair is rotation-symmetrical to the other, respectively. The semiconductor chip package with direction-flexible mountability in accordance with the present invention eliminates a process for indicating the mounting direction because the package can be mounted onto a substrate regardless the direction. Accordingly, the ID pin indication and a series of processes for testing the ID pin are eliminated and the malfunction due to the incorrect direction is prevented.

Abstract: A tray for ball grid array (BGA) semiconductor packages is provided, composed of a body, protruding portions and positioning portions. The body is formed with a plurality of recessed cavities, and the protruding portions are formed in the recessed cavities corresponding to area free of solder balls on the semiconductor packages to come into contact with the semiconductor packages; this does not require the use of flanges formed in a conventional tray to support a quite narrow peripheral portion of a semiconductor package, thereby preventing cracks of solder balls and assuring structural integrity and electrical-connection quality of the semiconductor packages. When the trays are vertically stacked, a positioning portion of an upper tray is engaged with a gap between an inner side wall of a recessed cavity and a semiconductor package received in a lower tray, so as to securely position the semiconductor packages accommodated by the lower tray.

Abstract: Disclosed herein is a chip on board lead package for optical mice and lens cover for the same. A semiconductor chip on board package for optical mice has a board, a semiconductor chip, at least one circuit pattern, at least one bonding wire, and a lens cover. The board has top and bottom surfaces, and a pair of via holes. The semiconductor chip is attached to a center portion on the top surface of the board and provided with a plurality of electrode terminals. The circuit pattern is formed on the top surface of the board. The bonding wire electrically connects the electrode terminals of the semiconductor chip with the circuit pattern. The lens cover encloses the top surface of the board and has a lens disposed on the same axis as that of the semiconductor chip, a plurality of electrode pins formed at positions of the lens cover corresponding to the positions of the via holes in the board to be integrated with the lens cover, and an opening formed in a center portion within the lens cover.

Abstract: A pin standing resin substrate including a resin substrate having a substantially plate-shaped main surface and composed of one of a resin and a composite material containing a resin, and having a pin-pad exposed from the main surface; and a pin soldered to the pin-pad, wherein the pin has been thermally treated by heating so as to soften the pin. The pin has a rod-like portion composed of a copper base metal and an enlarged diameter portion made of the same material as the rod-like portion. The enlarged diameter portion has a larger diameter than the rod-like portion and is formed at one end of the rod-like portion. At least the enlarged diameter portion is soldered to the pin-pad. Also disclosed is a method of making the pin standing resin substrate, a pin for bonding with the resin substrate, and a method of making the pin.

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract: A semiconductor module has a plurality of semiconductor chips which are provide on chip carriers in a housing. At least some of the semiconductor chips are disposed one above the other and there are conductive connections between the chip carriers of the semiconductor chips disposed one above the other. The conductive connections are formed by plug-in connections and extend through openings in the chip carriers. The openings may be lined with a conductive layer. In an alternative embodiment intermediate layers are provided between the semiconductor chips disposed one above the other. The intermediate layers have conductive projections which engage in the openings in the chip carriers for forming conductive connections.

Abstract: Disclosed herein is a chip on board lead package for optical mice and lens cover for the same. A semiconductor chip on board package for optical mice has a board, a semiconductor chip, at least one circuit pattern, at least one bonding wire, and a lens cover. The board has top and bottom surfaces, and a pair of via holes. The semiconductor chip is attached to a center portion on the top surface of the board and provided with a plurality of electrode terminals. The circuit pattern is formed on the top surface of the board. The bonding wire electrically connects the electrode terminals of the semiconductor chip with the circuit pattern. The lens cover encloses the top surface of the board and has a lens disposed on the same axis as that of the semiconductor chip, a plurality of electrode pins formed at positions of the lens cover corresponding to the positions of the via holes in the board to be integrated with the lens cover, and an opening formed in a center portion within the lens cover.

Abstract: A semiconductor chip package with direction-flexible mountability comprising a switching circuit for switching a pin function according to the mounting direction of a package, a pair of pin-definition pins for defining the pin function and a pair of power supply leads, and a pair of ground leads. One of the power supply lead pair and the ground lead pair is rotation-symmetrical to the other, respectively. The semiconductor chip package with direction-flexible mountability in accordance with the present invention eliminates a process for indicating the mounting direction because the package can be mounted onto a substrate regardless the direction. Accordingly, the ID pin indication and a series of processes for testing the ID pin are eliminated and the malfunction due to the incorrect direction is prevented.

Abstract: A low-cost header for connecting an electronic components board to a circuit board is disclosed, consisting of side walls made of an unwarpable plastic material and joined together to form a frame around an area substantially the same as the area of the components board. A plurality of metal pins are located in the frame, each having one end extending from said frame such that these ends can be soldered to the components board concurrently with the solder attachment of the components to the board. The other ends of the pins can be formed so that they are adjusted for either through-hole attachment to circuit boards, or for surface mounting.

Abstract: A molded electronic component has numerous connection pins protruding on a single plane from a side surface area of an essentially cuboid housing, and a circumferential ridge of molded housing material protrudes from the other side area surfaces on the plane of the connection pins. The thickness of this ridge essentially corresponds to the thickness of the connection pins. On the side surface area located opposite the side surface area from which the connection pins protrude, in the plane of the connection pins, the ridge passes or transitions into a groove such that there is no ridge protruding outwardly beyond the side surface in this area. Thus, the component can be better placed by a tool such as a suction needle onto a printed circuit board without interference from such a ridge. The invention is particularly suitable for the production of molded electronic components whose separation plane runs through that housing surface which serves as a docking surface for a suction needle.

Abstract: In a differential low-noise amplifier built in a semiconductor integrated circuit for a dual-band wireless transceiver, impedance components of wire bonding and package that occur in emitters are reduced and a gain is improved. Ground pins of amplifiers of the differential amplifier forming a pair are arranged adjacent to each other. Input pins and ground pins of the same amplifier are arranged adjacent to each other. Signals of the adjacent pins are allowed to have inverse phases, and trans-coupling between the pins is utilized so as to reduce impedance of the transistor emitters.

Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.

Abstract: An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; and a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit.

Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.

Abstract: An integrated circuit package fabricated by attaching a surface mount pin to a pin pad on a substrate using a Sn—Sb solder composition, where the quantity of Sb is in a range from 4 percent to 10 percent by weight. The Sn—Sb composition has a melting point above the melting point of commonly-used Sn—Pb solders. Thus, after the pins are surface mounted to the substrate, the pin integrity is not later compromised by assembly steps that reheat the substrate to a temperature sufficient to reflow the Sn—Pb solder. In one embodiment, the surface mount pins are attached to the bottom surface of an organic substrate using the Sn—Sb composition, and a flip-chip is attached to the top surface using Sn—Pb solder bumps. An integrated circuit package includes the substrate, the surface mount pins, and the Sn—Sb solder composition on the bonding surfaces of the pins.

Abstract: An integrated circuit package for electrically interconnecting a first bus signal path disposed on a printed circuit board and a second bus signal path disposed on the printed circuit board. The integrated circuit package may have a substrate, an integrated circuit chip die supported by the substrate. The interconnection network may be for electrically connecting the first bus signal path and the second bus signal path to a chip pad on the chip die. Thus, the first bus signal path and the second bus signal path may be electrically interconnected by only the interconnection circuit.

Abstract: A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor device, allowing the original I/O point location to be relocated to a new point of I/O interconnect that may be in the vicinity of the original point of I/O interconnect but can also be located at a distance from this original point of I/O interconnect. Layers of passivation and polyimide are provided for proper creation and protection of the extended and relocated I/O pads. Wire bonding is used to further interconnect the relocated I/O pads.

Abstract: A CPU and circuit board mounting arrangement in which a CPU connector is installed in a circuit board for top loading of a CPU to electrically connect respective bottom pads of the CPU to respective contacts of the circuit board by respective sloping terminals in the CPU connector, and a pressure member is pivoted to the CPU connector and locked to hold down the CPU in positive contact with the terminals of the CPU connector.

Abstract: A semiconductor package substrate has top and bottom surface buildup layers disposed on a thermally conductive substrate core. A portion of the substrate core may be exposed at a top surface of the package substrate to allow a heat spreader to be thermally coupled to the substrate core. An integrated circuit may be mounted on a top surface of the package substrate, with a top surface of the integrated circuit facing down. A heat spreader may be attached to the package substrate. The heat spreader may be thermally coupled to the substrate core and to a backside surface of the integrated circuit.

Abstract: An improved semiconductor chip interconnection advantageously employs a thin conductive layer that is used to form conductive members located between two nonconductive layers. The upper nonconductive layer has openings formed therein through which electrical connections are made between contacts in the chip member and the conductive members. The conductive members preferably have portions which are substantially parallel to a bottom surface of the semiconductor chip located between nonconductive layers and an upper nonconductive layer has openings formed therein through which electrical connections are made with the semiconductor chip. The conductive members have portions that extend downward away from the bottom surface of the chip.

Abstract: A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the substrate and wire bonded to terminals on the opposing substrate surface through an opening in the substrate. Two interposer substrates are placed together with die carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.

Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

Abstract: The present invention relates to a carrier module for micro-BGA(&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.

Abstract: An embodiment of an inventive semiconductor device comprises an unpackaged semiconductor wafer section having a major surface with a plurality of bond pads thereon. A plurality of conductors each comprise a lead member and at least a portion formed within a matrix. The conductors are attached to the major surface of the wafer section. An electrical connection electrically couples each of the bond pads with at least one of the lead members. Sealing material is then formed to contact at least the bond pads and the lead members.

Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.

Abstract: A column grid array integrated circuit package has a substrate. The substrate has a solder column array having a plurality of solder columns and a plurality of rigid columns interspersed with the solder columns at no-connect locations. The rigid columns contact a circuit board to which the column grid array integrated circuit package is mounted and support the column grid array integrated circuit package against compressive force.