Abstract: A package structure of a power converter, can include: a die pad; an insulation adhesive layer and a conductive adhesive layer on the die pad; a control circuit die on the insulation adhesive layer, where the insulation adhesive layer comprises a first insulation adhesive layer on a back surface of the control circuit die, and a second insulation adhesive on a surface of the die pad, where the first insulation adhesive layer is connected to the second insulation adhesive layer; and a power device die on the conductive adhesive layer, where the insulation adhesive layer is separated from the conductive adhesive layer.

Abstract: An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided on the substrate 1 and spaced apart from each other in a direction x, a light-transmitting resin 4 covering the light-receiving element 3, a light-transmitting resin 5 covering the light-emitting element 2, and a light-shielding resin 6 covering the light-transmitting resin 4 and the light-transmitting resin 5. The wiring pattern 8 includes a first light-blocking portion 83 interposed between the light-shielding resin 6 and the substrate 1 and positioned between the light-receiving element 3 and the light-emitting element 2 as viewed in x-y plane. The first light-blocking portion 83 extends across the light-emitting element 2 as viewed in the direction x.

Abstract: A method for mounting an electrical component to a substrate may include mounting the component onto the substrate, forming a cover including a thermally softenable or hardenable material and a contacting structure defined by integrated conductor paths, mounting the cover onto a mounting side of the substrate and onto the component mounted on the substrate, such that (a) the cover laterally traverses the component, (b) first contact surfaces of the contacting structure engage with the substrate at a first joining level defined at the mounting side of the substrate, and (c) second contact surfaces of the contacting structure engage with the component at a second joining level at the top side of the component, the second joining level being different than the first joining level. After assembling the components, joining connections at the first and second joining levels may be completed by a temperature or pressure based joining process.

Abstract: An electrical module contains at least one electrical component which is accommodated in a module housing. The module housing has at least two housing parts which lie one on the other and, on their own or together with one or more further housing parts of the module housing, delimit the interior of the module housing. There is at least one adhesive layer between the two housing parts, the adhesive layer adhesively bonding the two housing parts to one another.

Abstract: Provided is a heating wire arrangement for a ceramic heater, which is an arrangement of a heating wire on a ceramic substrate in a ceramic heater and emits heat. The heating wire arrangement for the ceramic heater includes a heating wire that is a metal wire member extending in a longitudinal direction and is two-dimensionally arranged on a virtual two-dimensional (2D) plane that is substantially parallel to a top surface of the ceramic substrate. Thus, a uniform heat density may be maintained and a rapid temperature ramp-up may be enabled, unlike a conventional heating wire of a three-dimensional (3D) type.

Abstract: In a resin structure including a resin molded body and a plurality of electronic components embedded in the resin molded body, (i) the resin molded body has a plurality of exposed surfaces on which electrodes of the plurality of electronic components are exposed, (ii) the resin molded body has a recess formed therein, and (iii) the recess has a bottom surface which is at least one of the plurality of exposed surfaces.

Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.

Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.

Abstract: A flexible integrated circuit that includes a first dielectric layer having a first section at one polarity and a second section at an opposing polarity, wherein the first section and the second section are separated by dielectric material within first dielectric layer; a second dielectric layer having a first side wall that is electrically connected to the first section and a second side wall that is electrically connected to the second section; and a third dielectric layer having a base that is electrically connected to the first side wall and the second side wall, wherein the second dielectric layer is between the first dielectric layer and the third dielectric layer, wherein the base, the first and second side walls and the first and second sections form an antenna that is configured to send or receive wireless signals.

Abstract: A multilayer ceramic capacitor may include a ceramic body including a plurality of dielectric layers; a first internal electrode disposed in the ceramic body and exposed to a first side surface in a width direction of the ceramic body and a second internal electrode disposed in the ceramic body and exposed to the first side surface in the width direction of the ceramic body; and first to third external electrodes disposed on the first side surface in the width direction of the ceramic body.

Abstract: There are provided an electronic device mounting board and an electronic apparatus that can be made lower in profile. An electronic device mounting board includes an insulating substrate having an opening in which an electronic device is disposed so as to lie over the opening as seen in a transparent plan view, and a reinforcement portion disposed on a surface or in an interior of the insulating substrate so as to lie around the opening of the insulating substrate as seen in a transparent plan view.

Abstract: A method includes applying solder pastes separately to first and second portions of the first member; bringing the solder paste applied to the first portion of the first member and a first portion of the second member into contact with each other, and bringing the solder paste applied to the second portion of the first member and a second portion of the second member into contact with other; and causing the solder paste brought into contact with the first portion of the second member and the solder paste brought into contact with the second portion of the second member to melt. In the melting, molten solder formed by melting the solder paste brought into contact with the first portion of the second member and molten solder formed by melting the solder paste brought into contact with the second portion of the second member are joined to each other.

Abstract: Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Abstract: An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.

Abstract: A process for preparing a prosthetic element comprising a glass-ceramic body. including the steps of a) providing a basic body comprising an amorphous glass phase and containing the components of the glass-ceramic body to be prepared, and b) transferring energy to the basic body to induce conversion of a starting phase of the material of the basic body into at least one crystalline phase in a confined region. According to the invention, energy is transferred to the confined region of the basic body by laser irradiating said region with a laser beam having a wavelength of at least 500 nm.

Abstract: Lithium silicate glass ceramics and glasses containing specific oxides of tetravalent elements are described which crystallize at low temperatures and are suitable in particular as dental materials.

Abstract: The circuit board assembly includes a first circuit board having a first plurality of electronic components attached to a major surface of the first circuit board. The first plurality of electronic components is electrically interconnected to a first plurality of conductive pads defined on the major surface of the first circuit board. A second circuit board has a second plurality of electronic components attached to a first major surface of the second circuit board. The second plurality of electronic components is electrically interconnected to a second plurality of conductive pads defined on a second major surface of the second circuit board. The first and second circuit board are attached by coupling the first and second plurality of conductive pads. A portion of the first plurality of electronic components on the first circuit board are disposed within a cavity defined by the second major surface of the second circuit board.

Abstract: A process for preparing glass-ceramic body including the steps of providing a basic glass body and subjecting the basic glass body to a thermal treatment whereby a crystalline phase embedded in a glass matrix is formed. The basic glass body is made of a composition comprising 65 to 72 wt-% SiO2, at least 10.1 wt-% Li2O and at least 10.1 wt-% Al2O3 based on the total weight of the composition, the proportion of Li2O to Al2O3 being from 1:1 to 1.5:1. The thermal treatment involves a nucleation step followed by several crystallization steps at different temperatures, whereby at least two different crystalline phases are formed.

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

Abstract: Embodiments of the present disclosure generally provide apparatus and method for cooling a substrate support in a uniform manner. One embodiment of the present disclosure provides a cooling assembly for a substrate support. The cooling assembly includes a cooling base having a first side for contacting the substrate support and providing cooling to the substrate support, a diffuser disposed on a second side of the cooling base, wherein the diffuser defines a plurality of cooling paths for delivering a cooling fluid towards the cooling base in a parallel manner, and an inlet/outlet plate disposed under the diffuser, wherein the inlet/outlet plate is provides an interface between the diffuser and an inlet and outlet of a cooling fluid.

Abstract: In at least one embodiment, the semiconductor component includes at least one optoelectronic semiconductor chip having a radiation exit side. The surface-mountable semiconductor component comprises a shaped body that covers side surfaces of the semiconductor chip directly and in a positively locking manner. The shaped body and the semiconductor chip do not overlap, as seen in a plan view of the radiation exit side.

Abstract: A stacked semiconductor device is provided in the present invention. The stacked semiconductor device includes a first substrate and a second substrate. A first conductive pad is disposed on the first substrate. A conductive pillar contacts the first conductive pad. At least one first barrier layer is disposed inside the conductive pillar. The conductive pillar encapsulates the first barrier layer. The elastic modulus of the first barrier layer is different from the elastic modulus of conductive pillar. A second conductive pad is disposed on the second substrate. A solder bump is disposed between the first substrate and the second substrate. The solder bump electrically connects to the conductive pillar. The conductive pillar can optionally include a truncated cone.

Abstract: A multilayer ceramic capacitor may include a ceramic body including a plurality of dielectric layers; a first internal electrode disposed in the ceramic body and exposed to a first side surface in a width direction of the ceramic body and a second internal electrode disposed in the ceramic body and exposed to the first side surface in the width direction of the ceramic body; and first to third external electrodes disposed on the first side surface in the width direction of the ceramic body.

Abstract: A method includes embedding high-z oxide nanoparticles in a semiconductor package of a semiconductor packaged assembly, wherein the high-z nanoparticles are operative to emit electron radiation when exposed to a radiation source to render a semiconductor device in the semiconductor package inoperable.

Abstract: A multilayer ceramic capacitor includes first through fourth internal electrodes. The first and second internal electrodes are connected to first and second external electrodes, respectively, and disposed to face each other. The third and fourth internal electrodes are connected to the first and second external electrodes, respectively, and disposed to face each other, with a connection area of the third and fourth internal electrodes with the first and second external electrodes being different from the connection area where the first and second internal electrodes connect with the first and second external electrodes. The first and second external electrodes include first and second conductive layers disposed in inner portions thereof, and first and second conductive resin layers disposed in outer portions thereof, respectively.

Abstract: There are provided an electronic component metal material which has low insertability/extractability, low whisker formability, and high durability, and a method for manufacturing the metal material. The electronic component metal material 10 includes a base material 11 , an A layer 14 constituting an outermost surface layer on the base material 11 and formed of Sn, In or an alloy thereof, and a B layer 13 constituting a middle layer provided between the base material 11 and the A layer 14 and formed of Ag, Au, Pt, Pd, Ru, Rh, Os, Ir or an alloy thereof, wherein the outermost surface layer (A layer) 14 has a thickness of 0.002 to 0.2 ?m, and the middle layer (B layer) 13 has a thickness larger than 0.3 ?m.

Abstract: There are provided a metal material for electronic component which has low insertability/extractability, low whisker formability, and high durability, and a method for manufacturing the metal material. The metal material 10 for electronic components has a base material 11, an A layer 14 constituting a surface layer on the base material 11 and formed of Sn, In or an alloy thereof, and a B layer 13 constituting a middle layer provided between the base material 11 and the A layer 14 and formed of Ag, Au, Pt, Pd, Ru, Rh, Os, Ir or an alloy thereof, wherein the surface layer (A layer) 14 has a thickness of 0.002 to 0.2 ?m, and the middle layer (B layer) 13 has a thickness of 0.001 to 0.3 ?m.

Abstract: A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

Abstract: A semiconductor device includes a plurality of semiconductor chips connected through a scribe lane; a plurality of through electrodes formed in each of the plurality of semiconductor chips; a heat dissipation member formed in the scribe lane; and heat transfer members connecting the through electrodes with the heat dissipation member.

Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink.

Abstract: A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.

Abstract: A resin composition for printed circuit board contains a thermosetting resin and an inorganic filler containing magnesium oxide. A volume average particle size of the magnesium oxide is from 2 ?m to 10 ?m, inclusive. In a distribution of a particle size of the magnesium oxide, the particle size has maximal frequencies in a first range of from 0.3 ?m to 1 ?m, inclusive, and in a second range of from 2 ?m to 10 ?m, inclusive, a maximal volume frequency in the first range is 5% or less, and a maximal volume frequency in the second range is 12% or more. A ratio of 50% accumulated particle size D50 with respect to specific surface area diameter of the magnesium oxide is 4 or less, and a ratio of 90% accumulated particle size D90 with respect to 10% accumulated particle size D10 of the magnesium oxide is 10 or less.

Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract: An RF package including: an RF circuit; a non-gaseous dielectric material coupled to the RF circuit, and having a thickness based on a magnetic field in the RF circuit; and an encapsulant material coupled to cover the RF circuit and non-gaseous dielectric material on at least one side of the RF circuit. A package manufacturing method, including: identifying an RF circuit; dispensing a non-gaseous dielectric material upon the RF circuit, wherein at least a portion of the non-gaseous dielectric material has a thickness based on a magnetic field in the RF circuit; and covering the RF circuit and non-gaseous dielectric material with an encapsulant material on at least one side of the RF circuit.

Abstract: Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region.

Abstract: A method for producing an optical assembly includes the steps of forming an optical semiconductor device including a substrate, a recess and an first optical waveguide, the optical semiconductor device having a principal surface, the recess extending from the principal surface to a middle portion of the substrate; forming an optical waveguide device including a through-hole and a second optical waveguide; positioning the optical semiconductor device and the optical waveguide device so that the principal surface of the optical semiconductor device and a back surface of the optical waveguide device face each other; aligning the optical semiconductor device and the optical waveguide device by inserting a guide pin into the through-hole and the recess so that the first optical waveguide is optically coupled with the second optical waveguide; and joining the optical semiconductor device and the optical waveguide device to each other.

Abstract: Disclosed are semiconductor packages and methods of forming the same. In the semiconductor packages and the methods, a package substrate includes a hole not overlapped with semiconductor chips. Thus, a molding layer may be formed without a void.

Abstract: RFID tags are assembled through affixing an antenna to an integrated circuit (IC) by forming one or more capacitors coupling the antenna and the IC with the dielectric material of the capacitor(s) including a non-conductive covering layer of the IC, a non-conductive covering layer of the antenna such as an oxide layer, and/or an additionally formed dielectric layer. Top and bottom plates of the capacitor(s) are formed by the antenna traces and one or more patches on a top surface of the IC.

Abstract: A semiconductor device includes a die having first contact pads and a second contact pad. Signal leads, each having embedded portion and an exposed portion, are electrically connected to respective ones of the first contact pads. A power bar extends in an area between the signal lead embedded portions and the die and has a first side opposing the signal leads and a second side opposing the die. The power bar is electrically connected to the second contact pad. An electrically grounded ground bar extends at least partially in the area. The ground bar has a first portion between the signal lead embedded portions and the first side of the power bar, and a second portion between the second side of the power bar and the die.

Abstract: Disclosed is an isolation mechanism and technique for packaging a MEMS transducer, such as a bulk acoustic wave gyroscope or accelerometer, to provide isolation from externally applied (or internally induced) stress, strain, vibration, shock and thermal transients. The disclosed methods and techniques enable the location of voids/air cavity/environmental isolations inside an encapsulant or over mold compound to be custom selected by treating at least a portion of the exterior surfaces of the MEMS device package with anti-stiction coatings to create opposing hydrophobic and hydrophilic conditions which during encapsulant and transfer molding steps create voids or air bubbles in the proximity of the anti-stiction coating due to the opposing water resistive characteristic of encapsulant.

Abstract: The present invention discloses a backlight module, comprising at least one back plate, a light guide plate, an optical film, a base, a plurality of fasteners and a plurality of optical fibers. The light guide plate is disposed in the back plate; the optical film is disposed on the light guide plate; the base is installed at one side of the light guide plate, and comprising a plurality of corresponding holes spaced with each other; the fasteners are fastened on the corresponding holes; each of the fasteners comprises a pressing hole; the optical fibers used for transmitting a light source are passed through the pressing holes; the optical fibers are tightly fixed by the fasteners. Fasteners are passed through the corresponding holes to narrow the pressing hole; Optical fibers are pressed and fixed to prevent the axial movement of optical fibers and to stabilize transmission quality of light source.

Abstract: A wiring board includes a base wiring board 10 and a frame wiring board 20. The base wiring board 10 has an element mounting portion 1a and a frame-shaped frame joining portion 1b on the upper surface and a solder resist layer 4 deposited in a portion between the element mounting portion 1a and the frame joining portion 1b. In the wiring board 10, a first joining pad 6 provided in the frame joining portion 1b and a second joining pad 16 provided in a lower surface of the frame wiring board 20 are joined together via a solder bump H so that a gap may be formed between the frame joining portion 1b and the frame wiring board 20. The base wiring board 10 has a resin injection hole 8 penetrating through the base wiring board 10 in the frame joining portion 1b, and the gap is filled with a sealing resin 18.

Abstract: A method for fabricating interlayer dielectric (ILD) layer is disclosed. The method includes the steps of first forming a first tensile dielectric layer on a substrate, and then forming a second tensile dielectric layer on the first tensile dielectric layer.

Abstract: A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.

Abstract: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.

Abstract: A bonding pad for use in attaching a semiconductor chip to a printed circuit board, includes: a copper layer; an organic layer disposed over the copper layer in a pattern such that part of the copper layer is exposed; and a gold layer disposed over the organic layer and in contact with the exposed part of the copper layer.

Abstract: A coil component 1 includes a substrate 2, a planar spiral conductor 10a formed on a top surface 2t of the substrate 2, a lead conductor 11a connected to an outer peripheral end of the planar spiral conductor 10a, a dummy lead conductor 15a formed on the top surface of the substrate 2 and between an outermost turn of the planar spiral conductor 10a and an end 2X2 of the substrate 2 and free from an electrical connection with another conductor within the same plane, external electrodes 26a and 26b arranged in parallel with the top surface of the substrate 2, and a bump electrode 25a formed on a surface of the lead conductor 11a and connects the lead conductor 11a with the external electrode 26a. The external terminals 26a and 26b have a larger area than the bump electrodes 15a and 15b for securing a bonding strength.

Abstract: A conductive-layer-integrated flexible printed circuit includes: (A) an electromagnetic-shielding conductive layer; (B) a photosensitive resin composition layer; and (C) a wiring-pattern-equipped film, (A) the electromagnetic-shielding conductive layer, (B) the photosensitive resin composition layer, and (C) the a wiring-pattern-equipped film being laminated in this order, and (B) the photosensitive resin composition layer being formed from a photosensitive resin composition containing at least (a) carboxyl-group-containing resin, (b) a photo-polymerization initiator, and (c) thermosetting resin.