Including Organic Insulating Material Between Metal Levels Patents (Class 257/759)
  • Patent number: 10199261
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James McMahon, Ryan S. Smith, Nicholas V. LiCausi, Errol Todd Ryan, Xunyuan Zhang, Shao Beng Law
  • Patent number: 10168075
    Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 10159148
    Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 18, 2018
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh, Belgacem Haba, Ilyas Mohammed
  • Patent number: 10109701
    Abstract: An organic EL display device includes: a lower electrode; an upper electrode; a first organic layer which is disposed between the lower electrode and the upper electrode and is formed of a plurality of layers including a light emitting layer formed of an organic material that emits light; a metal wire that extends between the pixels within the display region; and a second organic layer which is formed of a plurality of layers the same as that of the first organic layer and which comes into contact with a part of the metal wire and does not come into contact with the first organic layer. The upper electrode comes into contact with the metal wire in the periphery of the second organic layer. Accordingly, it is possible to uniformize the potential of the upper electrode without reducing the light emission area.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 23, 2018
    Assignee: Japan Display Inc.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 10090284
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Tien-Chung Yang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10074704
    Abstract: An organic light-emitting display apparatus includes: a first substrate; an insulating layer on the first substrate; a signal wiring on the insulating layer; an organic light-emitting device on the first substrate, the organic light-emitting device defining an active area and including a first electrode, a second electrode, and an intermediate layer between the first and second electrodes; a passivation layer on the insulating layer; and a metal layer on the passivation layer at an outer region adjacent to the active area, separated from the first electrode, and contacting the second electrode and the signal wiring, wherein a first opening is in the passivation layer at the outer region, and the metal layer contacts the insulating layer at the first opening.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 11, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Kwak, Han-Sung Bae, Sun-Youl Lee
  • Patent number: 10008630
    Abstract: An inorganic insulating film containing nitrogen, which has high adhesion to a sealant and an excellent effect of blocking hydrogen, water, and the like, is used as a layer in contact with the sealant. Further, the sealant is provided on the outer side than a side surface of an end portion of the organic insulating film provided over the transistor or the inorganic insulating film containing nitrogen is provided to cover an area from a region which is on the outer side than the edge of the organic insulating film to the side surface and the top surface of the end portion of the organic insulating film. Accordingly, the entry of hydrogen, water, and the like existing outside the display device into the oxide semiconductor included in the transistor can be suppressed, so that the display device can have high reliability.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata
  • Patent number: 9997400
    Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Kyoung Hee Nam, Jeonggil Lee, Hyunseok Lim, Seungjong Park, Seulgi Bae, Jaejin Lee, Kwangtae Hwang
  • Patent number: 9941214
    Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Kuang-Yuan Hsu
  • Patent number: 9859356
    Abstract: A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 2, 2018
    Assignee: MediaTek, Inc.
    Inventors: Ming-Da Tsai, Tao-Yi Lee, Cheng-Chou Hung, Tung-Hsing Lee
  • Patent number: 9837309
    Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Patent number: 9833927
    Abstract: Disclosed is a ceramic honeycomb structure comprising a honeycomb body and a multilayered outer layer formed of a thick core layer applied and rapidly dried and a thin clad layer dried more gently to form a crack free dual skin layer. The core layer may have properties that are closer to those of the ceramic honeycomb body in service than the clad layer that may provide a tough outer shell to withstand handling and assembly.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: December 5, 2017
    Assignee: Corning Incorporated
    Inventors: Thomas Richard Chapman, Jacob George, Ralph Henry Hagg, Amit Halder, Huthavahana Kuchibhotla Sarma
  • Patent number: 9716038
    Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9634031
    Abstract: To suppress change in electric characteristics and improve reliability of a semiconductor device including a transistor formed using an oxide semiconductor. A semiconductor device includes a transistor including a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, and a pair of electrodes. The gate electrode and the oxide semiconductor film overlap with each other. The oxide semiconductor film is located between the first insulating film and the second insulating film and in contact with the pair of electrodes. The first insulating film is located between the gate electrode and the oxide semiconductor film. An etching rate of a region of at least one of the first insulating film and the second insulating film is higher than 8 nm/min when etching is performed using a hydrofluoric acid.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: April 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Toshimitsu Obonai, Junichi Koezuka, Suzunosuke Hiraishi
  • Patent number: 9595473
    Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: March 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9570342
    Abstract: In a preferred embodiment of the invention, the via comprises one or more stacks, each stack comprising a seed layer of a first electrically conducting material formed on a smooth surface; a trace of a second electrically material that is electroplated on the seed layer; a column in electrical contact with the trace, the column comprising a third electrically conducting material that is electroplated on the trace; and an insulating material on the substrate and trace, the insulating material having a smooth upper surface in which the column is exposed. Additional vias may be stacked in tiers one on top of the other with the seed layer of one via making non-rectifying electrical contact with the exposed column of the via below it. Methods for forming the via structure are also disclosed.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 14, 2017
    Assignee: Altera Corporation
    Inventor: Yuanlin Xie
  • Patent number: 9520454
    Abstract: An organic light-emitting display apparatus includes: a first substrate; an insulating layer on the first substrate; a signal wiring on the insulating layer; an organic light-emitting device on the first substrate, the organic light-emitting device defining an active area and including a first electrode, a second electrode, and an intermediate layer between the first and second electrodes; a passivation layer on the insulating layer; and a metal layer on the passivation layer at an outer region adjacent to the active area, separated from the first electrode, and contacting the second electrode and the signal wiring, wherein a first opening is in the passivation layer at the outer region, and the metal layer contacts the insulating layer at the first opening.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Kwak, Han-Sung Bae, Sun-Youl Lee
  • Patent number: 9396990
    Abstract: The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chun Wang, Su-Jen Sung
  • Patent number: 9397659
    Abstract: A touch screen panel for a display device includes layers of polymer formed on both sides of a substrate for forming driving electrodes and sensing electrodes. The substrate may be made of materials such as polyethylene terephthalate (PET). Instead of bonding a window cover made of a heavy material, layers or polymer are formed on both sides of the substrate to afford rigidity to the touch screen panel. By removing the window cover, the weight and thickness of the touch screen panel can be reduced.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: July 19, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Namseok Lee, Soonsung Yoo, Chulho Kim, Yunho Kook
  • Patent number: 9299847
    Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qinghuang Lin, Minhua Lu, Robert L. Wisnieff
  • Patent number: 9190430
    Abstract: A method of manufacturing a display panel includes a sub-step of forming a photosensitive material layer for formation of a second layer on a first layer, a sub-step of disposing, over the photosensitive material layer, a photomask having a different degree of transparency in a first region and a second region thereof, the first region overlapping the photosensitive material layer, in plan view, at a location for formation of a second aperture, and the second region being a remainder of the photomask other than the first region, and a sub-step of exposing the photosensitive material layer via the photomask. In plan view, the area of the first region in the photomask is larger than the area of a first aperture in the first layer.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: November 17, 2015
    Assignee: JOLED INC.
    Inventors: Norishige Nanai, Akihito Miyamoto, Takaaki Ukeda
  • Patent number: 9166057
    Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 20, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Hiroshi Sunamura, Yoshihiro Hayashi
  • Patent number: 9142451
    Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil Kumar Singh, Matthew Herrick, Teck Jung Tang, Dewei Xu
  • Patent number: 9105727
    Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Masahiko Hayakawa, Shunpei Yamazaki
  • Patent number: 9076532
    Abstract: A semiconductor memory device comprises a first-supplied-voltage-supplying pad, a second-supplied-voltage-supplying pad, a data input/output pad, a memory body, a buffer circuit and an impedance-controlling circuit. A first supplied voltage is supplied to the memory body. A second supplied voltage is supplied to the buffer circuit. The impedance-controlling circuit controls an impedance of the buffer circuit on a side connected to the data input/output pad. The semiconductor memory device comprises a voltage-generating circuit generating a first inner voltage. The impedance-controlling circuit comprises a first P-channel transistor. A source terminal of the first P-channel transistor is connected to the first-supplied-voltage-supplying pad, and the first inner voltage generated from the voltage-generating circuit is selectively supplied to a gate terminal of the first P-channel transistor.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuui Shimizu, Satoshi Inoue
  • Patent number: 9061902
    Abstract: Electrodes, batteries, methods for use and manufacturing are implemented to provide ion-based electrical power sources and related devices. Consistent with one such method, a battery electrode is produced having nanowires of a first material. The electrode is produced using a single growth condition to promote growth of crystalline nanowires on a conductive substrate and of the first material, and promote, by maintaining the growth condition, growth of an amorphous portion that surrounds the crystalline nanowires.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: June 23, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Li-Feng Cui, Candace K. Chan, Riccardo Ruffo, Hailin Peng, Yi Cui
  • Patent number: 9018740
    Abstract: A field effect transistor (1) including: a semiconducting substrate (2) having two areas doped with electric charge carriers forming a source area (3) and a drain area (4), respectively; a dielectric layer positioned above the semiconducting substrate (2) between the source (3) and the drain (4) and forming the gate dielectric (9) of the field effect transistor (1); a gate (11) consisting of a reference electrode (8) and of a conductive solution (10), the solution (10) being in contact with the gate dielectric (9); and the gate dielectric (9) consists of a layer of lipids (13) in direct contact with the semiconducting layer (2). The invention also relates to a method for manufacturing such a field effect transistor (1) is disclosed.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: April 28, 2015
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S)
    Inventors: Anne Charrier, Hervé Dallaporta, Tuyen Nguyen Duc
  • Patent number: 9006715
    Abstract: A method of making an electronic device comprising a double bank well-defining structure, which method comprises: providing an electronic substrate; depositing a first insulating material on the substrate to form a first insulating layer; depositing a second insulating material on the first insulating layer to form a second insulating layer; removing a portion of the second insulating layer to expose a portion of the first insulating layer and form a second well-defining bank; depositing a resist on the second insulating layer and on a portion of the exposed first insulating layer; removing the portion of the first insulating layer not covered by the resist, to expose a portion of the electronic substrate and form a first well-defining bank within the second well-defining bank; and removing the resist. The method can provide devices with reduced leakage currents.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 14, 2015
    Assignee: Cambridge Display Technology Limited
    Inventors: Mark Crankshaw, Mark Dowling, Daniel Forsythe, Simon Goddard, Gary Williams, Ilaria Grizzi, Angela McConnell
  • Patent number: 9000594
    Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: John A. Ott, Ageeth A. Bol
  • Patent number: 8981563
    Abstract: A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: March 17, 2015
    Assignees: Renesas Electronics Corporation, Ulvac, Inc.
    Inventors: Shinichi Chikaki, Takahiro Nakayama
  • Patent number: 8975665
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 10, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: JinHee Jung, YoungDal Roh, KyoungHee Park
  • Patent number: 8957523
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 17, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Fan Zhang, Wei Shao, Juan Boon Tan, Yeow Kheng Lim, Mahesh Bhatkar, Soh Yun Siah
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946890
    Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: February 3, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Chung Chyung Han, Weidan Li, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu
  • Patent number: 8946884
    Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 3, 2015
    Assignee: Xilinx, Inc.
    Inventors: Woon-Seong Kwon, Suresh Ramalingam, Namhoon Kim, Joong-Ho Kim
  • Patent number: 8927414
    Abstract: A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: January 6, 2015
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Byoung-Iyong Choi, Eun-kyung Lee, Dong-mok Whang
  • Patent number: 8908345
    Abstract: In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 9, 2014
    Assignee: Hitachi,Ltd.
    Inventors: Futoshi Furuta, Kenichi Osada
  • Patent number: 8901549
    Abstract: The present invention provides an organic light emitting diode touch display panel including a substrate, a plurality of first electrodes and a plurality of second electrodes disposed on the substrate, a plurality of light emitting layers, a plurality of dielectric layers, a plurality of first electrode stripes, and a plurality of second stripes. Each light emitting layer is disposed on each first electrode, and each dielectric layer is disposed on each second electrode. Each first electrode stripe is disposed on the light emitting layers in each row, and each second electrode stripe is disposed on the dielectric layers in each row. Each first electrode, each light emitting layer and each first electrode stripe form an organic light emitting diode, and each second electrode, each dielectric layer and each second electrode stripe form a touch sensing capacitor.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 2, 2014
    Assignee: HannStar Display Corp.
    Inventors: Chien-Hsiang Huang, Kun-Hua Tsai, Jun-Shih Chung, Chun-Hsi Chen
  • Patent number: 8890318
    Abstract: A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Ying Zhang
  • Patent number: 8889491
    Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, John A. Fitzsimmons, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8884433
    Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 11, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8884288
    Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Qiang Li, Zhuanlan Sun, Changhui Yang
  • Patent number: 8872338
    Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Brian D. Young
  • Patent number: 8860009
    Abstract: A device having an easy production process and capable of achieving a long lifetime. The device has a substrate, two or more electrodes facing each other disposed on the substrate and a positive hole injection transport layer disposed between two electrodes among the two or more electrodes. The positive hole injection transport layer contains a reaction product of a molybdenum complex or tungsten complex.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: October 14, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shigehiro Ueno, Masato Okada, Keisuke Hashimoto
  • Patent number: 8860014
    Abstract: An organic electroluminescent member comprising: a positive electrode and a negative electrode on a substrate: multiple organic layers which include at least a positive hole transport layer, a light-emitting layer and an electron transport layer, and which are arranged between the positive electrode and the negative electrode; and an electron injection layer arranged between the electron transport layer and the negative electrode. The electron injection layer is formed from at least one selected from the group consisting of alkali metals and compounds containing alkali metals having a melting point of less than 90° C., and at least one selected from the group consisting of alkali metals, alkaline earth metals, compounds containing alkali metals, and compounds containing.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 14, 2014
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Kenji Arai, Toshihiko Iwasaki
  • Patent number: 8853858
    Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 8853659
    Abstract: A switchable electronic device comprises a hole blocking layer and a layer comprising a conductive material between first and second electrodes, wherein the conductivity of the device may be irreversibly switched upon application of a current having a current density of less than or equal to 100 A cm?2 to a conductivity at least 100 times lower than the conductivity of the device before switching. The conductive material is a doped organic material such as doped optionally substituted poly(ethylene dioxythiophene).
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: October 7, 2014
    Assignee: Cambridge Display Technology Limited
    Inventors: Neil Greenham, Jianpu Wang
  • Patent number: 8847367
    Abstract: Provided are a hole-injecting material for an organic electroluminescent device (organic EL device) exhibiting high luminous efficiency at a low voltage and having greatly improved driving stability, and an organic EL device using the material. The hole-injecting material for an organic EL device is selected from benzenehexacarboxylic acid anhydrides, benzenehexacarboxylic acid imides, or N-substituted benzenehexacarboxylic acid imides. Further, the organic EL device has at least one light-emitting layer and at least one hole-injecting layer between an anode and a cathode arranged opposite to each other, and includes the above-mentioned hole-injecting material for an organic EL device in the hole-injecting layer. The organic EL device may contain a hole-transporting material having an ionization potential (IP) of 6.0 eV or less in the hole-injecting layer or a layer adjacent to the hole-injecting layer.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: September 30, 2014
    Assignee: Nippon Steel & Sumikin Chemical Co., Ltd.
    Inventors: Takayuki Fukumatsu, Ikumi Ichihashi, Hiroshi Miyazaki, Atsushi Oda
  • Patent number: 8847215
    Abstract: An organic light-emitting diode includes an anode on a substrate; a first hole transporting layer on the anode; a second hole transporting layer on the first hole transporting layer and corresponding to the red and green pixel areas; a first emitting material pattern of a first thickness on the second hole transporting layer and corresponding to the red pixel area; a second emitting material pattern of a second thickness on the second hole transporting layer and corresponding to the green pixel area; a third emitting material pattern of a third thickness on the first hole transporting layer and corresponding to the blue pixel area; an electron transporting layer on the first, second and third emitting material patterns; and a cathode on the electron transporting layer, wherein the second thickness is less than the first thickness and greater than the third thickness.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 30, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jin-Ho Park, Kwang-Hyun Kim, Min-Na Kim
  • Patent number: RE45781
    Abstract: A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Jeffrey C. Hedrick, Kang-Wook Lee, Kelly Malone, Christy S. Tyberg