Including Organic Insulating Material Between Metal Levels Patents (Class 257/759)
  • Patent number: 11387193
    Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jiro Yota, Shiban Kishan Tiku
  • Patent number: 11342223
    Abstract: A semiconductor device manufacturing method includes burying a void formed in a substrate with a polymer having a urea bond; forming an oxide film on the substrate; and desorbing a depolymerized polymer obtained by depolymerizing the polymer from the void through the oxide film.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 24, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tatsuya Yamaguchi, Syuji Nozawa, Nagisa Sato
  • Patent number: 11245977
    Abstract: The invention relates to a simple to produce electric component for chips with sensitive component structures. Said component comprises a connection structure and a switching structure on the underside of the chip and a support substrate with at least one polymer layer.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 8, 2022
    Assignee: Snaptrack, Inc.
    Inventors: Christian Bauer, Hans Krüger, Jürgen Portmann, Alois Stelzl, Wolfgang Pahl
  • Patent number: 11222855
    Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: January 11, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jiro Yota, Shiban Kishan Tiku
  • Patent number: 11217481
    Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 4, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Christopher J. Penny, Robert Robison, Lawrence A. Clevenger
  • Patent number: 11121070
    Abstract: A device includes a package. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device further includes first sockets bonded to a top surface of the redistribution structure and a rigid/flexible substrate bonded to the top surface of the redistribution structure. The rigid/flexible substrate includes a first rigid portion, a second rigid portion, and a flexible portion interposed between the first rigid portion and the second rigid portion. The device further includes second sockets bonded to the first rigid portion of the rigid/flexible substrate and connector modules bonded to the second rigid portion of the rigid/flexible substrate.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Rong Chun, Tin-Hao Kuo, Chi-Hui Lai, Kuo Lung Pan, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11081596
    Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru Kadoshima, Masao Inoue
  • Patent number: 11013108
    Abstract: A display device including a display module configured to display an image, a printed circuit board provided below the display module, and a flexible substrate including a first bonding region, a bending region, and a second bonding region. The flexible substrate may be bent at the bending region and may be used to connect the display module to the printed circuit board. The flexible substrate may include a circuit layer electrically connecting the display module to the printed circuit board, a cover layer on the circuit layer, and a bubble-prevention layer, which is provided between the cover layer and the circuit layer and is overlapped with each of the first and second bonding regions of the flexible substrate.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jeungsoo Kim, Yun-ho Kim
  • Patent number: 10998291
    Abstract: Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Brent Keeth
  • Patent number: 10998136
    Abstract: Provided is a three-dimensional (3D) capacitor including conductors formed at a high density inside holes of an anodic oxide film, and a first electrode layer and a second electrode layer electrically connected to the conductors. Thus, a high capacitance relative to a size of the 3D capacitor may be easily achieved.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: May 4, 2021
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10957847
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: an Nth metal layer; a bottom electrode over the Nth metal layer; a magnetic tunneling junction (MTJ) over the bottom electrode; a top electrode over the MTJ; a spacer, including: a first spacer layer including SiN with a first atom density, the first spacer layer laterally encompassing the MTJ; and a second spacer layer including SiN with a second atom density different from the first atom density, the second spacer layer laterally encompassing at least a portion of the first spacer layer; and an (N+1)th metal layer over the top electrode. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Hung Cho Wang
  • Patent number: 10896804
    Abstract: A method and system for providing at least one of planarization, densification, and exfoliation of a porous material using ion beams. The method may use an ion beam generator to generate an ion beam, the ion beam having energy above 0.1 MeV. The ion beam generator may irradiate the surface of a porous material with the ion beam to produce at least one of planarization, densification, and exfoliation of the porous material.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: January 19, 2021
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Sergei Kucheyev, Swanee Shin
  • Patent number: 10896874
    Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: January 19, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guoxiang Ning, Ruilong Xie, Lei Sun
  • Patent number: 10889054
    Abstract: A sacrificial substrate for use in stereolithography, having a first surface configured to be attached to a build platform, and a second surface of the sacrificial substrate configured to be attached to a photopolymer part. The sacrificial substrate physically separates the build platform and the photopolymer part, and serves as the deposition surface for the photopolymer part in place of the build platform. The sacrificial substrate may be separated from the build platform and then separated from the photopolymer part via pyrolysis, oxidation, or etching to thereby yield the free photopolymer part without subjecting the part to excess physical force or damage.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 12, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Scott M. Biesboer, Jacob M. Hundley, Zak C. Eckel
  • Patent number: 10780675
    Abstract: This invention provides a gas barrier film, which can suppress blocking and winding deviation, and an optical film using the gas barrier film. The gas barrier film includes a flexible substrate and an inorganic thin film layer formed on at least one surface of the flexible substrate. A static friction coefficient between one surface of the gas barrier film and the other surface is not less than 0.85 and not more than 2.0, and when a 50 mm-square portion cut from the gas barrier film is placed on a horizontal surface such that a central portion of the 50 mm-square portion is in contact with the horizontal surface, an average value of distances from the horizontal surface to four corners of the 50 mm-square portion is not more than 2 mm.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: September 22, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Toshiyuki Ueno, Yasuhiro Yamashita, Mitsunori Nodono, Satoshi Okamoto
  • Patent number: 10770395
    Abstract: A method for fabricating an interconnect for integrated circuit is described. A recess is provided in a first dielectric layer comprising a first dielectric and a second dielectric layer comprised of a second dielectric. The first and second dielectric layers are disposed over a substrate. The second dielectric layer is disposed over the first dielectric layer. The recess is filled with a metal conductor. A chemical mechanical polishing process removes the metal conductor from field areas on the second dielectric layer. The second dielectric layer is removed. An interconnect element is created having a top face which protrudes higher than a top face of the first dielectric layer. The metal conductor of the interconnect element has direct contact with the first dielectric layer. In other aspects of the invention, the interconnect structure is described.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10676644
    Abstract: Provided is a shaped article including a hardcoat layer, where the hardcoat layer has surface hardness, flexibility, and heat resistance at high levels and offers excellent workability. The shaped article according to the present invention is a shaped article including a hardcoat layer, a substrate layer, and a thermoplastic resin layer and having a curved shape. The hardcoat layer defines an outermost surface of the shaped article. The hardcoat layer includes a cure product of a curable composition. The curable composition includes a cationically curable silicone resin and a leveling agent. The cationically curable silicone resin includes a silsesquioxane unit. The cationically curable silicone resin includes an epoxy-containing monomeric unit in a proportion of 50 mole percent or more of the totality of all monomeric units and has a number-average molecular weight of 1000 to 3000.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 9, 2020
    Assignee: DAICEL CORPORATION
    Inventor: Shinji Kikuchi
  • Patent number: 10671559
    Abstract: An apparatus includes a substrate, a classical computing processor formed on the substrate, a quantum computing processor formed on the substrate, and one or more coupling components between the classical computing processor and the quantum computing processor, the one or more coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: June 2, 2020
    Assignee: Google LLC
    Inventors: Masoud Mohseni, Hartmut Neven
  • Patent number: 10665652
    Abstract: An organic light-emitting display apparatus includes: a first substrate; an insulating layer on the first substrate; a signal wiring on the insulating layer; an organic light-emitting device on the first substrate, the organic light-emitting device defining an active area and including a first electrode, a second electrode, and an intermediate layer between the first and second electrodes; a passivation layer on the insulating layer; and a metal layer on the passivation layer at an outer region adjacent to the active area, separated from the first electrode, and contacting the second electrode and the signal wiring, wherein a first opening is in the passivation layer at the outer region, and the metal layer contacts the insulating layer at the first opening.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Kwak, Han-Sung Bae, Sun-Youl Lee
  • Patent number: 10643859
    Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Eric A. Joseph, Joe Lee, Takefumi Suzuki
  • Patent number: 10541203
    Abstract: Semiconductor fuses include a semiconductor fin having a metallized region between two non-metallized regions. Conductive layers are formed on the semiconductor fin above the two non-metallized regions. A dielectric layer is formed over the metallized region, between the conductive layers.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10535531
    Abstract: A method of etching is described. The method includes providing a substrate having a first material containing organic material and a second material that is different from the first material, forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing C and O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: January 14, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Vinayak Rastogi, Alok Ranjan
  • Patent number: 10513432
    Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Chun Weng, Lavanya Sanagavarapu, Ching-Hsiang Hu, Wei-Ding Wu, Shyh-Wei Cheng, Ji-Hong Chiang, Hsin-Yu Chen, Hsi-Cheng Hsu
  • Patent number: 10453700
    Abstract: A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ping Jiang, David Gerald Farber
  • Patent number: 10446791
    Abstract: A display device according to an embodiment of the present invention includes a display panel which has a display area having a pixel array part including a plurality of pixels, a frame area arranged on an outer peripheral side of the display area, and a driving part formation area having a driving part which drives the pixel array part. The display panel includes: a substrate; an organic light-emitting diode; an organic insulating film which is provided in the display area and the frame area, and has an opening in a light-emitting area of the organic light-emitting diode; and a first inorganic insulating film formed on an upper surface of the organic insulating film in the frame area. The organic insulating film includes a plurality of pieces of organic insulating film which are divided in the frame area.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: October 15, 2019
    Assignee: Japan Display Inc.
    Inventor: Keisuke Harada
  • Patent number: 10438893
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.
    Type: Grant
    Filed: October 15, 2017
    Date of Patent: October 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hsien Chen, Meng-Jun Wang, Ting-Chun Wang, Chih-Sheng Chang
  • Patent number: 10367015
    Abstract: Provided is a semiconductor device which can reduce leakage of current between wirings. Included steps are forming a first insulator over a first conductor which is formed over substrate; forming a first hard mask thereover; forming a first resist mask comprising a first opening, over the first hard mask; etching the first hard mask to form a second hard mask comprising a second opening; etching the first insulator using the second hard mask to form a second insulator comprising a third opening; forming a second conductor embedded in the second opening and the third opening; performing polishing treatment on the second hard mask and the second conductor to form a third conductor embedded in the third opening; forming a fourth conductor thereover; forming a second resist mask in a pattern over the fourth conductor; and dry-etching the fourth conductor to form a fifth conductor. The second hard mask can be dry-etched.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 30, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Shunpei Yamazaki
  • Patent number: 10199261
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James McMahon, Ryan S. Smith, Nicholas V. LiCausi, Errol Todd Ryan, Xunyuan Zhang, Shao Beng Law
  • Patent number: 10168075
    Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 10159148
    Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 18, 2018
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh, Belgacem Haba, Ilyas Mohammed
  • Patent number: 10109701
    Abstract: An organic EL display device includes: a lower electrode; an upper electrode; a first organic layer which is disposed between the lower electrode and the upper electrode and is formed of a plurality of layers including a light emitting layer formed of an organic material that emits light; a metal wire that extends between the pixels within the display region; and a second organic layer which is formed of a plurality of layers the same as that of the first organic layer and which comes into contact with a part of the metal wire and does not come into contact with the first organic layer. The upper electrode comes into contact with the metal wire in the periphery of the second organic layer. Accordingly, it is possible to uniformize the potential of the upper electrode without reducing the light emission area.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 23, 2018
    Assignee: Japan Display Inc.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 10090284
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Tien-Chung Yang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10074704
    Abstract: An organic light-emitting display apparatus includes: a first substrate; an insulating layer on the first substrate; a signal wiring on the insulating layer; an organic light-emitting device on the first substrate, the organic light-emitting device defining an active area and including a first electrode, a second electrode, and an intermediate layer between the first and second electrodes; a passivation layer on the insulating layer; and a metal layer on the passivation layer at an outer region adjacent to the active area, separated from the first electrode, and contacting the second electrode and the signal wiring, wherein a first opening is in the passivation layer at the outer region, and the metal layer contacts the insulating layer at the first opening.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 11, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Kwak, Han-Sung Bae, Sun-Youl Lee
  • Patent number: 10008630
    Abstract: An inorganic insulating film containing nitrogen, which has high adhesion to a sealant and an excellent effect of blocking hydrogen, water, and the like, is used as a layer in contact with the sealant. Further, the sealant is provided on the outer side than a side surface of an end portion of the organic insulating film provided over the transistor or the inorganic insulating film containing nitrogen is provided to cover an area from a region which is on the outer side than the edge of the organic insulating film to the side surface and the top surface of the end portion of the organic insulating film. Accordingly, the entry of hydrogen, water, and the like existing outside the display device into the oxide semiconductor included in the transistor can be suppressed, so that the display device can have high reliability.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata
  • Patent number: 9997400
    Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Kyoung Hee Nam, Jeonggil Lee, Hyunseok Lim, Seungjong Park, Seulgi Bae, Jaejin Lee, Kwangtae Hwang
  • Patent number: 9941214
    Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Kuang-Yuan Hsu
  • Patent number: 9859356
    Abstract: A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 2, 2018
    Assignee: MediaTek, Inc.
    Inventors: Ming-Da Tsai, Tao-Yi Lee, Cheng-Chou Hung, Tung-Hsing Lee
  • Patent number: 9833927
    Abstract: Disclosed is a ceramic honeycomb structure comprising a honeycomb body and a multilayered outer layer formed of a thick core layer applied and rapidly dried and a thin clad layer dried more gently to form a crack free dual skin layer. The core layer may have properties that are closer to those of the ceramic honeycomb body in service than the clad layer that may provide a tough outer shell to withstand handling and assembly.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: December 5, 2017
    Assignee: Corning Incorporated
    Inventors: Thomas Richard Chapman, Jacob George, Ralph Henry Hagg, Amit Halder, Huthavahana Kuchibhotla Sarma
  • Patent number: 9837309
    Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Patent number: 9716038
    Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9634031
    Abstract: To suppress change in electric characteristics and improve reliability of a semiconductor device including a transistor formed using an oxide semiconductor. A semiconductor device includes a transistor including a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, and a pair of electrodes. The gate electrode and the oxide semiconductor film overlap with each other. The oxide semiconductor film is located between the first insulating film and the second insulating film and in contact with the pair of electrodes. The first insulating film is located between the gate electrode and the oxide semiconductor film. An etching rate of a region of at least one of the first insulating film and the second insulating film is higher than 8 nm/min when etching is performed using a hydrofluoric acid.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: April 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Toshimitsu Obonai, Junichi Koezuka, Suzunosuke Hiraishi
  • Patent number: 9595473
    Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: March 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9570342
    Abstract: In a preferred embodiment of the invention, the via comprises one or more stacks, each stack comprising a seed layer of a first electrically conducting material formed on a smooth surface; a trace of a second electrically material that is electroplated on the seed layer; a column in electrical contact with the trace, the column comprising a third electrically conducting material that is electroplated on the trace; and an insulating material on the substrate and trace, the insulating material having a smooth upper surface in which the column is exposed. Additional vias may be stacked in tiers one on top of the other with the seed layer of one via making non-rectifying electrical contact with the exposed column of the via below it. Methods for forming the via structure are also disclosed.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 14, 2017
    Assignee: Altera Corporation
    Inventor: Yuanlin Xie
  • Patent number: 9520454
    Abstract: An organic light-emitting display apparatus includes: a first substrate; an insulating layer on the first substrate; a signal wiring on the insulating layer; an organic light-emitting device on the first substrate, the organic light-emitting device defining an active area and including a first electrode, a second electrode, and an intermediate layer between the first and second electrodes; a passivation layer on the insulating layer; and a metal layer on the passivation layer at an outer region adjacent to the active area, separated from the first electrode, and contacting the second electrode and the signal wiring, wherein a first opening is in the passivation layer at the outer region, and the metal layer contacts the insulating layer at the first opening.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Kwak, Han-Sung Bae, Sun-Youl Lee
  • Patent number: 9396990
    Abstract: The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chun Wang, Su-Jen Sung
  • Patent number: 9397659
    Abstract: A touch screen panel for a display device includes layers of polymer formed on both sides of a substrate for forming driving electrodes and sensing electrodes. The substrate may be made of materials such as polyethylene terephthalate (PET). Instead of bonding a window cover made of a heavy material, layers or polymer are formed on both sides of the substrate to afford rigidity to the touch screen panel. By removing the window cover, the weight and thickness of the touch screen panel can be reduced.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: July 19, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Namseok Lee, Soonsung Yoo, Chulho Kim, Yunho Kook
  • Patent number: 9299847
    Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qinghuang Lin, Minhua Lu, Robert L. Wisnieff
  • Patent number: 9190430
    Abstract: A method of manufacturing a display panel includes a sub-step of forming a photosensitive material layer for formation of a second layer on a first layer, a sub-step of disposing, over the photosensitive material layer, a photomask having a different degree of transparency in a first region and a second region thereof, the first region overlapping the photosensitive material layer, in plan view, at a location for formation of a second aperture, and the second region being a remainder of the photomask other than the first region, and a sub-step of exposing the photosensitive material layer via the photomask. In plan view, the area of the first region in the photomask is larger than the area of a first aperture in the first layer.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: November 17, 2015
    Assignee: JOLED INC.
    Inventors: Norishige Nanai, Akihito Miyamoto, Takaaki Ukeda
  • Patent number: 9166057
    Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 20, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Hiroshi Sunamura, Yoshihiro Hayashi
  • Patent number: RE45781
    Abstract: A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Jeffrey C. Hedrick, Kang-Wook Lee, Kelly Malone, Christy S. Tyberg