Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor chip, a method for manufacturing a semiconductor device, a semiconductor chip, a semiconductor device, a connection substrate and an electronic apparatus, in which semiconductor chips stacked in layers are electrically connected to one another without using wires. In one embodiment, after an electrode 18 is formed on a surface 16 of a first semiconductor chip 12, a hole 26 is formed from an opposite surface 24 thereof until a tungsten layer 20 of the electrode 18 is exposed. A protrusion 30 is formed by etching on a surface 31 of a second semiconductor chip 14 and thereafter an abutting electrode 32 is formed on an apex section of the protrusion 30. The first semiconductor chip 12 and the second semiconductor chip 14 are stacked on top of the other such that the abutting electrode 32 contacts the electrode 18.

Abstract: An integrated circuit including a reinforced bonding pad structure is disclosed. The reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. At least one metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame of the reinforced bonding pad structure.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory capacity.

Abstract: An organic semiconductor device (11) can be embedded within a printed wiring board (10). In various embodiments, the embedded device (11) can be accompanied by other organic semiconductor devices (31) and/or passive electrical components (26). When so embedded, conductive vias (41, 42, 43) can be used to facilitate electrical connection to the embedded device. In various embodiments, specific categories of materials and/or processing steps are used to facilitate the making of organic semiconductors and/or passive electrical components, embedded or otherwise.

Abstract: An inexpensive package for a semiconductor chip (1) that incorporates a stress relief buffer (13) between a side of the chip and the metal carrier layer (2) to absorb thermally induced stress produced by significantly different rates of thermal expansion of the wafer and the metal carrier. The buffer (13) is formed by a polymer that is flexible and can be etched, contains a coefficient of thermal expansion that does not significantly differ from that of the chip and/or a combination of CET and elasticity that retains a physical connection with the side of the chip and the metal carrier over the temperature range of operation anticipated for the chip. Polyimide or paraylene are preferred examples. Vias (15) extend through the buffer to place the metal carrier electrically in common with the metal layer (5) found on the back surface of the wafer so that an electrical ground applied to the metal carrier layer (2) may extend through to that surface.

Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a sacrificial material is used to occupy a closed interior volume in a semiconductor structure is disclosed. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, in one embodiment by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the sacrificial material. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween. Also disclosed are methods of forming multi-level air gaps and methods or forming over-coated conductive lines or leads wherein a portion of the overcoating is in contact with at least one air gap.

Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer As a result, the first structured dielectric layer has a substantially planar surface A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.

Abstract: An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface (105) essentially parallel to the first layer surface (102), thereon a respective second layer (106) for each interconnect (104), the second layers (106) of adjacent interconnects covering regions between the adjacent interconnects (104), and thereon a third layer (107), which completely closes off the regions between the adjacent interconnects (104) by means of coverage.

Abstract: A semiconductor device includes at least one semiconductor structure having a plurality of external connection portions on an upper surface, and an insulating member which is made of a resin containing reinforcing materials and arranged on a side of the semiconductor structure. An insulating film is formed on the upper surface of the semiconductor structure, except the external connection portions, and on an upper surface of the insulating member. A plurality of upper wirings each of which has a connection pad portion are located on an upper side of the insulating film and electrically connected to a corresponding one of the external connection portions of the semiconductor structure. The connection pad portion of at least one of the upper wirings is arranged above an upper surface of the insulating member.

Abstract: A semiconductor device having bump electrodes electrically connected to connection pads formed on a semiconductor chip of the semiconductor device, tips of the bump electrodes exposing at a surface of a sealing resin film formed on a surface of the semiconductor chip, wherein the sealing resin film is comprised of a low-elastic resin layer formed on the surface of the semiconductor chip and a high-elastic resin layer formed on a surface of the low-elastic resin layer and having an elastic coefficient higher than that of the low-elastic resin layer, a thickness of the high-elastic resin layer being between 5 ?m and 45 ?m.

Abstract: An apparatus including a contact point formed on a device layer of a circuit substrate or interconnect layer on a substrate; a first dielectric layer including cubic boron nitride on the substrate; and a different second dielectric layer on the substrate and separated from the device layer by the first dielectric layer. Also, an apparatus including a circuit substrate including a device layer and a composite dielectric layer. The composite dielectric includes a first dielectric material including cubic boron nitride and a different second dielectric material. The first dielectric material surrounds the second dielectric material.

Abstract: Specific embodiments of the invention provide a silicon-carbide-type or silicon oxycarbide (also often called carbon-doped-oxide [CDO] or organosilicate glass) capping material and method for depositing this capping material on ELK films which are used as a dielectric material in integrated circuits. The ELK film may include any ELK film including but not limited to inorganic, organic and hybrid dielectric materials and their respective porous versions. The silicon-carbide-type material may be an amorphous silicon carbide type material such as the commercially available BLOk™ material, or a carbon-doped oxide material such as the commercially available Black Diamond™ both of which are developed by Applied Materials of Santa Clara, Calif. The amorphous silicon carbide (a-SiC) material is deposited using a plasma process in a non-oxidizing environment and the CDO-type material is deposited using an oxygen-starved plasma process.

Abstract: An intermediate construction of an integrated circuit includes a semiconductive substrate and a raised mandril over the substrate. The raised mandril may be raised out from the substrate and have at least one edge substantially perpendicular to the substrate and at least one beveled edge. A layer of structural material may form an edge defined feature on the at least one perpendicular edge.

Abstract: A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.

Abstract: A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

Abstract: A semiconductor device having a structure in which no short circuit occurs between plug interconnections even when a void occurs in an insulating layer in a gap between wiring layers and a method of manufacturing the same are attained. The method includes: a step of forming transfer gates so as to be close to each other with a gap on a semiconductor substrate; a step of burying the gap and covering a wiring layer; a step of opening a contact hole in an insulating layer in the gap portion; a step of depositing a short-circuit preventing insulating film in the contact hole; an etch back step of removing the short-circuit preventing insulating film at least on the bottom of the gap to expose the semiconductor substrate; and a step of forming a plug interconnection.

Abstract: An electronic device includes a semiconductor layer in contact with a number of electrodes, wherein the semiconductive layer includes a compound wherein either or both of the following geometric isomers of the compound are present: wherein: n is 1, 2 or 3 for the polycyclic moiety; and R1 and R2 are independently selected from the group consisting of a hydrocarbon ring and a heterocyclic group, wherein R1 and R2 are the same or different hydrocarbon ring, the same or different heterocyclic group, or one of R1 and R2 is the hydrocarbon ring and the other the heterocyclic group.

Abstract: A semiconductor package seal ring including a plurality of insulating layers, a plurality of conductive runners each embedded in one of the insulating layers, and a plurality of conductive posts each contacting one of the conductive runners and extending through at least one of the insulating layers and at least partially through an opening in another one of the conductive runners.

Abstract: A semiconductor device includes a first wiring line having a first through hole, and a first connection member which extends through the first through hole at an interval from the first wiring line.

Abstract: A plurality of metal interconnections are formed on a semiconductor substrate. The semiconductor substrate is held on a sample stage in a reactor chamber of a plasma processing apparatus and a material gas containing C5F8, C3F6, or C4F6 as a main component is introduced into the reactor chamber, so that a first fluorine-containing organic film having cavities at positions between the metal interconnections is deposited between the metal interconnections and on the top surfaces of the metal interconnections.

Abstract: The present invention provides a deposition method and deposition apparatus capable of forming a fluorine-containing silicon inorganic insulating film of stable film properties and a method of manufacturing a semiconductor device. Deposition apparatus 10 comprises parallel plate type electrodes 16, 22 arranged within reaction chamber 12, gas supply sources 20, 32, 34 for feeding process gas containing SiH4, SiF4 and oxygen source substance into reaction chamber 12, valves 36, 38, 40, gas mixing chamber 28 and power source 44 that supplies RF power for generating the plasma of the process gas. In this deposition apparatus 10, power source 44 is capable of supplying RF power of at least 1000 Watts to parallel plate type electrodes 16, 22. In this apparatus 10, fluorine-containing silicon oxide film is deposited on wafer 14 by generating the plasma of process gas containing SiH4, SiF4 and N2O.

Abstract: A high frequency semiconductor device including wiring layers which are formed above a semiconductor substrate and in which transmission lines are formed by combining with a ground plate having a potential fixed at the ground potential, at least one crossing portion in which the wiring layers mutually cross, with insulating interlayers provided therebetween, and at least one separation electrode being selectively provided on one of the insulating interlayers, the at least one separation electrode having a potential fixed at the ground potential. Accordingly, in the high frequency semiconductor device, electrical interference between two crossing wiring layer is prevented and transmission loss is suppressed.

Abstract: A method for depositing a low k dielectric film comprising silicon, carbon, and nitrogen is provided. The low k dielectric film is formed by a gas mixture comprising a silicon source, a carbon source, and NR1R2R3, wherein R1, R2, and R3 are selected from the group consisting of alkyl and phenyl groups. The low k dielectric film may be used as a barrier layer, an etch stop, an anti-reflective coating, or a hard mask.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Abstract: There is disclosed a photoelectric conversion device which is manufactured by depositing numerous crystalline semiconductor particles of one conductivity type on a substrate having an electrode of one side to join the crystalline semiconductor particles to the substrate, interposing an insulator among the crystalline semiconductor particles, forming a semiconductor layer of the opposite conductivity type over the crystalline semiconductor particles, and connecting an electrode to the semiconductor layer of the opposite conductivity type, in which the insulator comprises a mixture or reaction product of polysiloxane and polycarbosilane. The insulator interposed among the crystalline semiconductor particles is free from defects such as cracking and peeling, so that a low cost photoelectric conversion device with high reliability can be provided.

Abstract: A semiconductor device comprises a semiconductor chip which has a first surface, a pad which is formed directly on the first surface, an oxide film which is formed on the first surface, an insulating film which is formed on the oxide film and a part of the pad, a conductive film which is formed on the insulating film and the pad, a sealing material which covers a part of the conductive film and the insulating film and a bump which is formed over the conductive film, wherein the bump is exposed from a surface of the sealing material.

Abstract: A semiconductor device has a first insulating film deposited over a semiconductor substrate, an interconnect opening portion formed in the first insulating film, an interconnect disposed in the interconnect opening portion, and a second insulating film formed over the first insulating film and the interconnect. The interconnect has a first conductor film, a second conductor film formed via the first conductor film and comprised of one of titanium silicon nitride, tantalum silicon nitride, tantalum nitride and titanium nitride, a third conductor film formed via the first and second conductor films and comprised of a material having good adhesion with copper; and a fourth conductor film formed via the first, second and third conductor conductor film having a copper as a main component. Thus, it is possible to improve adhesion between a conductor film composed mainly of copper and another conductor film having a copper-diffusion barrier function in the interconnect.

Abstract: An organic electronic device structure, according to a first aspect of the invention, includes: (a) a substrate layer; (b) an organic electronic region disposed over the substrate layer; (c) a pressure sensitive adhesive layer disposed over the organic electronic device; and (d) a barrier layer disposed over the adhesive layer. According to a second aspect of the present invention, an organic electronic device structure includes: (a) a substrate layer; (b) an organic electronic region disposed over the substrate layer; (c) a barrier layer disposed over the organic electronic region; (d) a pressure sensitive adhesive layer disposed over the substrate layer and over the barrier layer; and (e) an additional layer disposed over the adhesive layer. In many preferred embodiments, the organic electronic device region is an OLED region.

Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.

Abstract: A semiconductor device formed of an insulation layer having at least a laminated portion in which a first insulation film made of silicon oxide film and a second insulation film made of organic insulation film are laminated on each other, wherein said semiconductor device has a silicon oxide film structure in which moisture absorption is limited, said structure having characteristics showing that a ratio SI/SII of area integrations SI and SII of a desorption gas spectrum by ion current measurement of the temperature programmed desorption mass analysis measurement based on mass 18 relating to the laminated structure of the silicon oxide film and the organic insulation film and a single layer structure of the silicon oxide film is not less than 1 or not more than 1.5.

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layers of compliant material, and assembling the substrate into a stacked semiconductor device.

Abstract: Methods of selectively removing post-etch polymer material and dielectric antireflective coatings (DARC) without substantially etching an underlying carbon-doped low k dielectric layer, and compositions for the selective removal of a DARC layer and post-etch polymer material are provided. A composition comprising trimethylammonium fluoride is used to selectively etch a dielectric antireflective coating layer overlying a low k dielectric layer at an etch rate of the antireflective coating layer to the low k dielectric layer that is greater than the etch rate of the antireflective coating to a TEOS layer. The method and composition are useful, for example, in the formation of high aspect ratio openings in low k (carbon doped) silicon oxide dielectric layers and maintaining the integrity of the dimensions of the formed openings during a cleaning step to remove a post-etch polymer and antireflective coating.

Abstract: In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.

Abstract: In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive substrate and a second material is formed proximate the conductive material. A barrier layer is formed between the conductive material and the second material. The barrier layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material. In another aspect, the invention encompasses a composition of matter comprising silicon chemically bonded to both nitrogen and an organic material. The nitrogen is not bonded to carbon. In yet another aspect, the invention encompasses a semiconductor processing method. A semiconductive substrate is provided and a layer is formed over the semiconductive substrate. The layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material.

Abstract: An interconnect structure for a semiconductor device includes a metallization line formed within a low-k dielectric material, the metallization line being surrounded on bottom and side surfaces thereof by a liner material. An embedded dielectric cap is formed over a top surface of the metallization line, wherein the embedded dielectric cap has a sufficient thickness so as to separate a top surface of the liner material from a hardmask layer formed over the low-k dielectric material.

Abstract: This invention provides a semiconductor device that can ensure that stress on the nitride film is not increased or is reduced, and that can prevent an increase in interconnection capacity. The semiconductor device comprises a underlayer, a base oxide film that is formed on this underlayer, a nitride film pattern with a hole pattern that is provided on this base oxide film, holes that penetrate the base oxide film, an upper oxide film provided on the base oxide film to cover the nitride film pattern, wiring grooves provided through the upper oxide film in which part of the nitride film pattern including the hole pattern is exposed, and wiring metal that fills the holes and wiring grooves. The nitride film pattern is formed with such a shape and size that surrounds the outside of the wiring grooves and is separate from neighbouring nitride film patterns.

Abstract: An organic light emitting device display may be formed that is suitably passivated while still permitting electrical access to cathodes and anodes via electrical contacts. In one embodiment, a barrier layer may be formed over the light emitting material to prevent moisture or other ambient attack. The barrier layer may be covered with other layers to form an outer and inner via down to the cathode or anode to be contacted. A contact metal may be provided to the anode or cathode. The layers over the barrier layer permit patterning and contact formation while the barrier layer adequately protects the light emitting material during those steps and thereafter.

Abstract: Structures and methods for preventing fluorine diffusion from a fluorinated dielectric material having a low dielectric constant are disclosed. Various fluorine diffusion barriers are described, each of which comprises doped or undoped silicon in combination with tantalum, tantalum nitride, tantalum silicide, cobalt, cobalt silicide, or mixtures thereof. Fluorine diffusion from fluorinated dielectrics is stopped by the barriers at temperatures as high as 450° C. In practice, one of the disclosed fluorine diffusion barriers is positioned between a fluorine-containing insulator and a conductive metal interconnect or metal interconnect diffusion barrier, thereby preventing diffusion of the fluorine atoms into the adjacent interconnect/barrier.

Abstract: An integrated device comprises a first conductive region and a first insulating region of dielectric material covering the first conductive region. A first through region of electrically conductive material extends inside the first insulating region, and is in direct electrical contact with the first conductive region. A second conductive region, arranged above the first insulating region, is in a position not aligned and not in contact with the first through region. A second insulating region of dielectric material covers the second conductive region. A second through region of electrically conductive material extends inside the second insulating region as far as the first through region and is aligned and in direct electrical contact with the first through region. A third conductive region, arranged above the second insulating region, is aligned and in direct electrical contact with the second through region.

Abstract: Defect-free dielectric coatings comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The dielectric coatings are useful in a number of contexts, including the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric coatings are prepared by admixing, in a solvent, a polymeric nitrogenous porogen with a high temperature, thermosetting host polymer miscible therewith, coating a substrate surface with the admixture, heating the uncured coating to cure the host polymer and provide a vitrified, two-phase matrix, and then decomposing the porogen. The dielectric coatings so prepared have few if any defects, and depending on the amount and molecular weight of porogen used, can be prepared so as to have an exceptionally low dielectric constant on the order of 2.5 or less, preferably less than about 2.0.

Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: A reinforced semiconductor interconnect structure, having the following components: (1) A first metal interconnect disposed in a first material, the first metal interconnect having a line portion and at least one via portion, an anode section and a cathode section, the via portion of the first metal interconnect located in the anode section, the line portion of the first metal interconnect having a top, bottom and terminus side, wherein at least a part of the bottom side of the line portion of the first metal interconnect in contact with the first dielectric; and (2) a first reinforcement disposed in the first material, the first reinforcement in contact with at least the bottom side of the first metal interconnect, the first reinforcement comprising a second material, the second material being electrically nonconductive; and wherein the second material has a greater mechanical rigidity than the first material.

Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits. good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.