Abstract: A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer.

Abstract: A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.

Abstract: A system and methodology are disclosed for forming a passive layer on a conductive layer. The formation can be done during fabrication of an organic memory cell, where the passive layer generally includes a conductivity facilitating compound, such as copper sulfide (Cu2S). The conductivity facilitating compound is deposited onto the conductive layer via plasma enhanced chemical vapor deposition (PECVD) utilizing a metal organic (MO) precursor. The precursor facilitates depositing the conductivity facilitating compound in the absence of toxic hydrogen sulfide (H2S), and at a relatively low temperature and pressure (e.g., between about 400 to 600 K and 0.05 to 0.5 Pa., respectively). The deposition process can be monitored and controlled to facilitate, among other things, depositing the conductivity facilitating compound to a desired thickness.

Abstract: A wiring line to which a high-frequency signal is applied is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an interlayer insulting film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively and waveform rounding of an applied high-frequency signal can be reduced without increasing the number of manufacturing steps.

Abstract: An organic light emitting device display may include transverse row and column lines. In a passively driven OLED display, a fuse may be positioned between the OLED material and the row electrode. When a short occurs, the single pixel may be separated from the circuit by the fuse, avoiding the possibility that an entire row of pixels may be adversely affected by the short associated with one single pixel along a row.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.

Abstract: A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A look material is then deposited to fill the gaps bet n metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A prove layer is deposited on top of the metal lines and the look material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photoresist, and to clean the vias.

Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.

Abstract: A wiring which is formed by filling a via hole and a wiring trench with Cu via a base film is formed by a damascene method. Thereafter, an SiC:H film is formed to cover an upper surface of the wiring. At this time, an N atom content thereof is controlled to be 8 (atm %) to 20 (atm %) by adding an N-containing gas at the time of forming the SiC:H film, thereby causing the film density of the SiC:H film to be 2.1 (g/cm3) or higher.

Abstract: An electrode structure includes a conductive film 24c formed on a base substrate 10 through an insulation film. The insulation film comprises a plurality of poles 36 of polyimide, a first film 38 formed on the side surfaces of the poles and formed of an insulation material of a high hardness than polyimide, and a second film 40 of polyimide buried among the plural poles with the first film formed on the side surfaces thereof. Because of the first film of an insulation material having high hardness formed on the side surfaces of the poles of polyimide, even when a strong force is applied upon the bonding, the poles are prevented from being distorted, and the conductive film is protected from peeling off. Because of the thick polyimide layer below the conductive film, a parasitic capacity between the conductive film and the lower layer can be small, whereby radio-frequency signals can be used.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: The present invention provides a low-k dielectric constant structure and method of forming the same on a substrate 10 that features having a dielectric layer 20 with differing regions of density 12 and 18. To that end, the method includes depositing, upon the substrate, a dielectric layer having first and second density regions. The density associated with the second density region being greater than the density associated with the first density region, and the first density region being disposed between the substrate and the second density region.

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: A method and apparatus for forming a relatively thin releasable layer of copper on a carrier substrate. First, a separation facilitating layer is provided on the carrier substrate. A layer of vapor-deposited copper is then formed over the separation facilitating layer to protect the separation facilitating layer during subsequent processing. Thereafter, the thickness of the copper layer is increased by the electrodeposition of copper onto the vapor-deposited layer. The copper layer is applied to a dielectric and is released from the carrier substrate at the separation facilitating layer.

Abstract: A polymer or organic light emitting display may be formed on a substrate by patterning the light emitting material using a screen printing technique. In this way, displays may be formed economically, overcoming the difficulties associated with photoprocessing light emitting materials. A binary optic material may be selectively incorporated into sol gel coatings coated over light emitting elements formed from the light emitting material. A tricolor display may be produced using a light emitting material that produces a single color.

Abstract: There is provided a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms and having a covalently bonded tri-dimensional network structure and a dielectric constant of not more than 2.6. The dielectric constant film may additionally have a covalently bonded ring network. The covalently bonded tri-dimensional (i.e., three dimensional) network structure comprises Si—O, Si—C, Si—H, C—H and C—C covalent bonds and may optionally contain F and N. In the film, the Si atoms may optionally be partially substituted with Ge atoms. The dielectric constant film has a thickness of not more than 1.3 micrometers and a crack propagation velocity in water of less than 10−10 meters per second. There is further provided a back-end-of-the-line (BEOL) interconnect structure comprising the inventive dielectric film as a BEOL insulator, cap or hardmask layer.

Abstract: The present invention provides for improved alignment of an opening in a lower dielectric layer with an opening in an upper dielectric layer. This improved alignment is beneficial as it improves the functionality of devices with dual damascene material arrangements, as normal misalignments do not deem the devices inferior or non-functional. Further, the present invention is beneficial as it allows for a designer, such as a microprocessor designer, to depend on more predictable conductive characteristics of contacts between a first conductive region and a second conductive region.

Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer of dielectric material; a second layer of material selected from the group including: amorphous Silicon (a-Si), amorphous Ge (a-Ge) or alloys thereof, located on top of the first layer; and, a third layer located on top of the a-Si, a-Ge, or alloys thereof layer, wherein the second layer provides adhesion between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective a-Si, a-Ge, or alloys thereof bonding layers disposed to enhance adhesion between the different layers.

Abstract: A semiconductor device includes a lower wiring layer, a first insulating layer formed on the lower wiring layer and having a via hole with a width, a via mask layer formed on the first insulating layer and having an opening with a width larger than the width of the via hole, a second insulating layer formed on the via mask layer and having an upper wiring, groove whose width coincides with the width of the via hole, a via contact structure buried in the via hole, and an upper wiring layer buried in the upper wiring groove.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a porous insulating film formed above the semiconductor substrate, the porous insulating film having a relative dielectric constant of 2.5 or less and including a first insulating material, at least a portion of pores in the porous insulating film having on the inner wall thereof a layer of a second insulating material which differs in nature from the first insulating material, and a plug and/or a wiring layer buried in the porous insulating film.

Abstract: A substrate (300) for use in semiconductor devices, having first (301a) and second (301b) surfaces and a base structure including insulating material. A plurality of I/O terminal pads (302, 303) is distributed on the first and second surfaces, respectively, and these terminal pads are interconnected by conducting traces integral to the base structure. A plurality of selected metal layers (304 to 309) is distributed in the structure; the metal layers are substantially parallel to the surfaces and separated by the insulating material from each other and from the surfaces. At least one metal layer (304 or 307, respectively) opposite each of the surfaces has openings (320a, 320b) therein configured so that the metal areas (307a) directly opposite each of the terminal pads (303) are electrically isolated from the remainder of the layer. The width of these openings is selected to provide a pre-determined capacitance between each of the terminals (303) and the remainder of the metal layer (307).

Abstract: A method for manufacturing electronic devices using multiple layers of pre-porous dielectric materials that are made porous subsequent to etching and metal filling of apertures is provided. The pre-porous layers may be made porous sequentially or during a single processing step. Such pre-porous dielectric layers are selected not only to provide low dielectric constants after being made porous, but also to provide a difference in etch rates. Structures having such multiple layers of pre-porous dielectric layers are also provided.

Abstract: Carborane may be used as a precursor to form low dielectric constant dielectrics. The carborane material may be modified to enable it to be deposited by chemical vapor deposition.

Abstract: A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

Abstract: In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).

Abstract: An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the carbon content of the dielectric material in two regions of the integrated circuit structure. The first region comprises the region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines, while the second region comprises the region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the dielectric layer to an overlying layer of metal interconnects.

Abstract: In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping layer.

Abstract: A semiconductor device and a method of making it involve the semiconductor device (10, 71, 101, 121, 151, 201) having a substrate (11, 73, 153) with spaced source and drain regions (13-14, 76-78, 154). A gate section (21, 81-82, 123, 203) projects upwardly from between an adjacent pair of the regions, into an insulating layer (31, 83, 103, 122, 157). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (36, 87, 126), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (41-42, 91-93, 107-108, 138-139, 158) on opposite sides of and immediately adjacent the gate section. A conductive layer (51, 96, 111, 161, 171) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: A dielectric device has a multi-layer oxide artificial lattice. The artificial lattice is a stacked structure with a plurality of dielectrics. The dielectric film is deposited at a single atomic layer thickness or at a unit lattice thickness. The dielectric film is formed by repeatedly depositing with layer-by-layer growth process at least two dielectric materials having dielectric constant different from each other at least one time in a range of the single atomic layer thickness to 20 nm or by depositing at least two dielectric materials in a predetermined alignment adapted for a functional device, thereby forming one artificial lattice having an identical directional feature. By utilizing the stress applied to an interfacial surface of the consisting layers in the artificial oxide lattice, the dielectric constant and tunability are greatly improved, so the artificial lattice can be adapted for high-speed switching and high-density semiconductor devices and high-frequency response telecommunication devices.

Abstract: A connection via hole is formed in an inter layer insulation film that covers a copper pad. Copper is formed within the connection via hole to form a connection copper via metal. An aluminum pad having a barrier metal thereunder for preventing reaction between copper and aluminum is formed on the connection copper via metal, thereby electrically connecting the copper pad and the aluminum pad to each other through the connection copper via metal. A step formed by the connection via hole that is formed in the inter layer insulation film is made substantially equal to zero with the aid of the connection copper via metal and at the same time, a film thickness of aluminum constituting the aluminum pad is reduced, thereby reducing manufacturing cost of the semiconductor device.

Abstract: A two-step via cleaning process which removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer which are disposed over a metal-containing trace, pad, or other such circuitry, wherein the metal-containing trace, pad, or other circuitry is disposed on a semiconductor substrate. When such a via is formed, the sidewalls of the via are coated with a residue layer. The residue layer generally has a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip which removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip which removes the oxide polymer component.

Abstract: A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.

Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous matrix using supercritical carbon dioxide leaving voids in positions previously occupied by portions of the sacrificial dielectric layer. The resultant structure has a desirably low k value as a result of the voids and materials comprising the porous matrix and other structures. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.

Abstract: An improved method for making a semiconductor device is described. That method includes forming a first dielectric layer on a substrate, then forming on the first dielectric layer a second dielectric layer. The second dielectric layer is made from a material that is more sensitive to radiation of a specified wavelength and energy than is the material from which the first dielectric layer is made. After the first dielectric layer and the second dielectric layer are exposed to radiation of a specified wavelength and energy, a portion of the first dielectric layer is removed to form a via, and a portion of the second dielectric layer is removed to form a trench. The via and trench are then filled with a conductive material.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: It is an object to provide a semiconductor device having a copper wiring structure in which a copper diffusion preventing capability of a silicon carbide film can be improved and a lifetime maintained until a dielectric breakdown caused by copper diffusion can be increased, and furthermore, a method of manufacturing the semiconductor device. A first copper diffusion preventive film (8) is provided between a first copper wiring (7) and a second low permittivity interlayer insulating film (9). A silicon carbide film containing oxygen atoms or the oxygen atoms and nitrogen atoms in 30 atomic % or more is employed for the first copper diffusion preventive film (8). By employing such a silicon carbide film, a copper diffusion preventing function can be improved and a lifetime maintained until a dielectric breakdown caused by the copper diffusion can be increased.

Abstract: The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0<y≦(4−x)×0.1 and 0.5<z<1.

Abstract: A method of forming an insulating material for use in an integrated circuit includes providing a substrate of the integrated circuit and forming a polymeric material on the substrate. At least a portion of the polymeric material is converted to a foamed polymeric material. The converting of the polymeric material includes exposing at least a portion of the polymeric material to a supercritical fluid. Further, an integrated circuit includes a substrate of the integrated circuit and a foamed polymeric material on at least a portion of the substrate. The integrated circuit may further include a conductive layer adjacent the foamed polymeric material. The conductive layer may be a metal line on the foamed polymeric material, or the conductive layer may be an interconnect, e.g., a contact or a via, adjacent the foamed polymeric material.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: The present invention provides gas layer formation material selected from the group consisting of acenaphthylene homopolymers; acenaphthylene copolymers; poly(arylene ether); polyamide; B-staged multifunctional acrylate/methacrylate; crosslinked styrene divinyl benzene polymers; and copolymers of styrene and divinyl benzene with maleimide or bis-maleimides. The formed gas layers are used in microchips and multichip modules.

Abstract: A semiconductor device has a multilayer interconnection structure in which a plurality of interconnection layers is formed in an insulating film. The multilayer interconnection structure has a first metal film made of a first material and functioning as a first interconnection belonging to an interconnection layer other than an uppermost interconnection layer, a second metal film made of a second material and functioning as a second interconnection belonging to the uppermost interconnection layer, a third metal film made of the first material and belonging to an interconnection layer other than the uppermost interconnection layer and functioning as a bonding pad, an opening formed in the insulating film and having its bottom defined by the third metal film, and a bonding wire connected to the third metal film through the opening. The second material has a lower resistance and is more susceptible to oxidation than the first material.

Abstract: Porous insulation films 28, 40, 50 are formed of an insulation forming material including a silicon compound having a skeleton containing C—C bonds, a pore forming compound which is decomposed or evaporated by a heat treatment, and a solvent which dissolves the silicon compound with the pore forming compound, whereby the porous insulation film can have good mechanical strength and low dielectric constant.

Abstract: A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.

Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.